TWI420630B - 半導體封裝結構與半導體封裝製程 - Google Patents

半導體封裝結構與半導體封裝製程 Download PDF

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Publication number
TWI420630B
TWI420630B TW099131048A TW99131048A TWI420630B TW I420630 B TWI420630 B TW I420630B TW 099131048 A TW099131048 A TW 099131048A TW 99131048 A TW99131048 A TW 99131048A TW I420630 B TWI420630 B TW I420630B
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Taiwan
Prior art keywords
wafer
conductive substrate
forming
metal plating
top surface
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TW099131048A
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English (en)
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TW201212190A (en
Inventor
Guo Cheng Liao
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Advanced Semiconductor Eng
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Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW099131048A priority Critical patent/TWI420630B/zh
Priority to US13/026,991 priority patent/US8531017B2/en
Publication of TW201212190A publication Critical patent/TW201212190A/zh
Priority to US13/975,717 priority patent/US20140001621A1/en
Application granted granted Critical
Publication of TWI420630B publication Critical patent/TWI420630B/zh

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Description

半導體封裝結構與半導體封裝製程
本發明大體而言是有關於一種電子元件封裝(electronic device package)。更具體而言，本發明是有關於一種進階四方扁平無引腳(advanced quad flat no-lead,aQFN)封裝結構，以及其製造方法。
在射頻(radio frequency,RF)、無線、攜帶型應用及個人電腦(personal computer,PC)周邊設備市場中，一般對於提高較小封裝之效能以及增加之輸入或輸出(input/output,I/O)數目存在較高的需求。例如四方扁平無引腳(quad flat no-lead,QFN)封裝已被廣泛接受，且通常適用於包括高頻傳輸(諸如經由RF頻寬進行之高頻傳輸)的晶片封裝。
對於QFN封裝結構而言，通常以銲線架製成晶片墊(die pad)以及周圍引腳(lead)。QFN封裝結構通常透過表面黏著技術(surface mounting technology,SMT)焊接至印刷電路板(printed circuit board,PCB)。因此，QFN封裝結構之晶片墊及引腳應設計成可與封裝處理能力相配，並可提升長期焊點可靠性。
另一方面，為了提升接點密度，申請人更提出進階式四方扁平無引腳(advanced Quad Flat No Lead,aQFN)封裝結構。如圖1所示，aQFN封裝結構100包括晶片110、晶片墊122、多個引腳124、多條銲線130以及一封裝膠體140。晶片墊122與引腳124是經由同一金屬板蝕刻而成，且分別暴露於封裝膠體140的底部。暴露的引腳124作為aQFN封裝結構110的對外接點。銲線130連接於晶片110與引腳124之間。
雖然引腳124成面陣列配置於晶片110外圍，但晶片110下方的空間仍舊被晶片墊122所佔用，而無法被有效利用。
本發明提供一種半導體封裝結構，具有滿球墊(full array)的引腳設計，而可提高接點密度。
本發明提供一種半導體封裝製程，可形成具有滿球墊(full array)之引腳分佈的封裝結構。
為具體描述本發明之內容，在此提出一種半導體封裝結構，包括一晶片、多個引腳、多個接墊、多條重佈線路、多條銲線、一填充材以及一封裝膠體。所述多個引腳陣列配置於一平面上，且包括位於晶片外圍的多個第一引腳以及位於晶片下方且鄰近晶片的多個第二引腳。每一引腳包括一上表面、一下表面、一上傾斜部，其配置鄰近於各引腳的上表面，以及一下傾斜部，其配置鄰近於各引腳的下表面。接墊位於晶片之外，而重佈線路分別連接於接墊與第二引腳之間。銲線分別連接於晶片與接墊之間以及晶片與第一引腳之間。填充材填入晶片與第二引腳之間。封裝膠體形成於晶片、接墊、重佈線路、銲線以及引腳上，以實質上覆蓋引腳的上傾斜部，且引腳的下傾斜部至少部分從封裝膠體的一下表面向外延伸。
在本發明之一實施例中，所述半導體封裝結構更包括一第一金屬鍍層，其配置於每一第一引腳的上表面、每一第二引腳的上表面、接墊以及重佈線路上。每一第一引腳的上表面及其上的第一金屬鍍層被包封於封裝膠體內，而每一第二引腳的上表面及其上的第一金屬鍍層被包封於填充材內。
在本發明之一實施例中，所述半導體封裝結構更包括一第二金屬鍍層，其配置於每一第一引腳的下表面與每一第二引腳的下表面上。接墊以及重佈線路未被第二金屬鍍層覆蓋。
在本發明之一實施例中，填充材的材質與封裝膠體的材質相同。
在本發明之一實施例中，所述半導體封裝結構更包括一黏著層，配置於晶片的底面與填充材之間。
本發明又提出一種半導體封裝製程。首先，提供一導電基板，其具有一頂面以及相對於頂面的一背面。導電基板的頂面具有一晶片接著區域。接著，形成圖案化的一第一金屬鍍層於導電基板的頂面。第一金屬鍍層包括位於晶片接著區域之外的多個第一引腳金屬圖案、位於晶片接著區域之外的多個接墊金屬圖案、位於晶片接著區域內的多個第二引腳金屬圖案以及分別連接於第二引腳金屬圖案以及接墊金屬圖案之間的多個重佈線路金屬圖案。並且，形成圖案化的一第二金屬鍍層於導電基板的底面。然後，以第一金屬鍍層為罩幕來半蝕刻導電基板，以在導電基板未被第一金屬鍍層覆蓋的區域上形成一凹陷。接著，形成一填充材於晶片接著區域內的凹陷內。並且，接合一晶片至導電基板的晶片接著區域。晶片被放置於填充材以及第二引腳金屬圖案上，並且藉由多條銲線分別連接晶片與接墊金屬圖案以及分別連接晶片與第一引腳金屬圖案。然後，形成一封裝膠體於導電基板的頂面上，以使封裝膠體包封晶片以及銲線，且封裝膠體填滿凹陷的其餘部分。之後，以第二金屬鍍層為罩幕來蝕刻導電基板，以形成位於晶片接著區域之外的多個第一引腳、位於晶片接著區域之外的多個接墊、位於晶片接著區域內的多個第二引腳以及分別連接於第二引腳以及接墊之間的多條重佈線路。
本發明提出另一種半導體封裝製程。首先，提供一導電基板，其具有一頂面以及相對於頂面的一背面。導電基板的頂面具有一晶片接著區域。接著，形成圖案化的一第一金屬鍍層於導電基板的頂面。第一金屬鍍層包括位於晶片接著區域之外的多個第一引腳金屬圖案、位於晶片接著區域之外的多個接墊金屬圖案、位於晶片接著區域內的多個第二引腳金屬圖案以及分別連接於第二引腳金屬圖案以及接墊金屬圖案之間的多個重佈線路金屬圖案。並且，形成圖案化的一第二金屬鍍層於導電基板的底面。然後，以第一金屬鍍層為罩幕來蝕刻導電基板，以在導電基板未被第一金屬鍍層覆蓋的區域上形成一凹陷。接著，接合一晶片至導電基板的晶片接著區域，並且藉由多條銲線分別連接晶片與接墊金屬圖案以及分別連接晶片與第一引腳金屬圖案。然後，形成一封裝膠體於導電基板的頂面上，以使封裝膠體包封晶片以及銲線，且封裝膠體填滿凹陷。之後，以第二金屬鍍層為罩幕來蝕刻導電基板，以形成位於晶片接著區域之外的多個第一引腳、位於晶片接著區域之外的多個接墊、位於晶片接著區域內的多個第二引腳以及分別連接於第二引腳以及接墊之間的多條重佈線路。
本發明提出又一種半導體封裝製程。首先，提供一導電基板，其具有一頂面以及相對於頂面的一背面。導電基板的頂面具有一晶片接著區域。接著，形成圖案化的一第一金屬鍍層於導電基板的頂面。第一金屬鍍層包括位於晶片接著區域之外的多個第一引腳金屬圖案以及位於晶片接著區域之外的多個接墊金屬圖案。並且，形成圖案化的一第二金屬鍍層於導電基板的底面。然後，形成圖案化的一光阻層於導電基板的頂面。光阻層包括位於晶片接著區域之外的多個第一引腳光阻圖案、位於晶片接著區域之外的多個接墊光阻圖案、位於晶片接著區域內的多個第二引腳光阻圖案以及分別連接於第二引腳光阻圖案以及接墊光阻圖案之間的多個重佈線路光阻圖案。之後，以光阻層為罩幕來半蝕刻導電基板，以在導電基板未被光阻層覆蓋的區域上形成一凹陷。接著，移除光阻層，並且接合一晶片至導電基板的晶片接著區域。晶片藉由多條銲線分別連接晶片與接墊金屬圖案以及分別連接晶片與第一引腳金屬圖案。然後，形成一封裝膠體於導電基板的頂面上，以使封裝膠體包封晶片以及銲線，且封裝膠體填滿凹陷。之後，以第二金屬鍍層為罩幕來蝕刻導電基板，以形成位於晶片接著區域之外的多個第一引腳、位於晶片接著區域之外的多個接墊、位於晶片接著區域內的多個第二引腳以及分別連接於第二引腳以及接墊之間的多條重佈線路。
本發明提出再一種半導體封裝製程。首先，提供一導電基板，其具有一頂面以及相對於頂面的一背面。導電基板的頂面具有一晶片接著區域。接著，形成圖案化的一第一金屬鍍層於導電基板的頂面。第一金屬鍍層包括位於晶片接著區域之外的多個第一引腳金屬圖案以及位於晶片接著區域之外的多個接墊金屬圖案。並且，形成圖案化的一第二金屬鍍層於導電基板的底面。然後，形成圖案化的一光阻層於導電基板的頂面。光阻層包括位於晶片接著區域之外的多個第一引腳光阻圖案、位於晶片接著區域之外的多個接墊光阻圖案、位於晶片接著區域內的多個第二引腳光阻圖案以及分別連接於第二引腳光阻圖案以及接墊光阻圖案之間的多個重佈線路光阻圖案。之後，以光阻層為罩幕來半蝕刻導電基板，以在導電基板未被光阻層覆蓋的區域上形成一凹陷。接著，移除光阻層，並且形成一填充材於晶片接著區域內的凹陷內。然後，接合一晶片至導電基板的晶片接著區域。晶片被放置於填充材上，並且藉由多條銲線分別連接晶片與接墊金屬圖案以及分別連接晶片與第一引腳金屬圖案。之後，形成一封裝膠體於導電基板的頂面上，以使封裝膠體包封晶片以及銲線，且封裝膠體填滿凹陷的其餘部分。接著，以第二金屬鍍層為罩幕來蝕刻導電基板，以形成位於晶片接著區域之外的多個第一引腳、位於晶片接著區域之外的多個接墊、位於晶片接著區域內的多個第二引腳以及分別連接於第二引腳以及接墊之間的多條重佈線路。
在本發明之一實施例中，形成前述填充材的方法包括貼附一乾膜於晶片接著區域上或是在晶片接著區域進行點膠。
在本發明之一實施例中，形成前述圖案化的第一金屬鍍層的方法包括：先形成一第一圖案化罩幕於導電基板的頂面上，之後，電鍍形成第一金屬鍍層於該頂面被第一圖案化罩幕所暴露的區域上。
在本發明之一實施例中，形成前述圖案化的第二金屬鍍層的方法包括：先形成一第二圖案化罩幕於導電基板的底面上，之後，電鍍形成第二金屬鍍層於該底面被第二圖案化罩幕所暴露的區域上。
在本發明之一實施例中，前述圖案化的第二金屬鍍層可在形成封裝膠體於導電基板的頂面之後，才被形成於導電基板的底面。本發明不限定第二金屬鍍層與封裝膠體的形成順序。
基於上述，本發明除了在晶片外圍形成第一引腳之外，更在晶片下方形成第二引腳，使得晶片下方的空間得以被有效利用。如此，可形成滿球墊的引腳設計，以提高半導體封裝結構的接點密度。
現將詳細參考本發明之一些實施例，其實例說明於附圖中。相同參考數字將在諸圖及本說明書中盡可能用以指代相同或類似部件。
定義
以下定義部份或全部適用於下文所述之實施態樣。
如下文中所述，除非上下文另有明確表示，單數形式「一」以及「該」可包括多個指示物。舉例而言，「一凹陷」實際上可能包括多個凹陷。
如下文中所述，術語「鄰近」指接近或鄰接。鄰近組件可彼此間隔開或可彼此實際或直接接觸。在某些情況下，鄰近組件可彼此連接或可彼此整體形成。
如下文中所述，諸如「內部」、「頂部」、「底部」、「在......上」、「在......下」、「向上」、「向下」、「側」以及「橫向」等術語係指根據圖示之組件集合的相對關係，但並非限定此等組件在製造或使用時的方向。
如下文中所述，術語「連接」泛指藉由電性或結構性而直接或間接連接。所連接組件可直接彼此耦接或可經由另一組件間接地彼此連接。
本發明之態樣可用於製造各種封裝結構，諸如，堆疊型封裝、多晶片封裝或高頻裝置封裝。
圖2A為依照本發明之一實施例的一種半導體封裝結構的剖面圖。圖2B為圖2A之半導體封裝結構的上視圖。請同時參考圖2A與2B，本實施例的半導體封裝結構200包括晶片210、多個引腳222與224、多個接墊226、多條重佈線路228、多條銲線230、一填充材240以及一封裝膠體250。引腳222與224陣列配置於同一平面上，且包括位於晶片210外圍的多個第一引腳222以及位於晶片210下方且鄰近晶片的多個第二引腳224。為清楚表達第一引腳222、接墊226、重佈線路228以及晶片210的位置關係，圖2B省略了銲線230，且圖2B的封裝膠體250為可透視的。
每一第一引腳222包括一上表面222a、一下表面222b、一上傾斜部222c，其配置鄰近於上表面222a，以及一下傾斜部222d，其配置鄰近於下表面222b。此外，每一第二引腳224包括一上表面224a、一下表面224b、一上傾斜部224c，其配置鄰近於上表面224a，以及一下傾斜部224d，其配置鄰近於下表面224b。接墊226位於晶片210之外，而重佈線路228分別連接於接墊226與第二引腳224之間。銲線230分別連接於晶片210與接墊226之間以及晶片210與第一引腳222之間。由於第二引腳224位於晶片210下方，因此藉由重佈線路228與接墊226將第二引腳224外拉(fan out)，再經由銲線230連接接墊226與晶片210，使得位於晶片210下方的第二引腳224可以順利與晶片210電連接。
填充材240填入晶片210與第二引腳224之間。封裝膠體250形成於晶片210、接墊226、重佈線路228、銲線230以及引腳222與224上，以實質上覆蓋第一引腳222的上傾斜部222c以及第二引腳224的上傾斜部224c，且第一引腳222的下傾斜部222d以及第二引腳224的下傾斜部224d至少部分從封裝膠體250的下表面250a向外延伸，即，突出於封裝膠體250的下表面250a。
在本實施例中，填充材240與封裝膠體250例如具有相同或不同材質。換言之，在製程上，可以選擇先形成填充材240，之後再形成封裝膠體250，或是可以省略先形成填充材240的步驟，而在形成封裝膠體250的同時填入封膠材料於晶片210與第二引腳224之間，以取代填充材240。選擇預先形成填充材240的好處在於可形成供晶片210放置的平坦區，提高配置晶片210時的平穩度。在本發明的不同實施例中，填充材240的高度可視實際需求高於、等於或低於第二引腳224的上表面224a。此外，本實施例的半導體封裝結構200可能包括一黏著層270，其配置於晶片210的底面210a與填充材240之間，而此填充材240也可以避免晶片210底部可能存在的黏著層270在後續製程中外露。填充材240的材質例如是高分子材料、綠漆、乾膜型態或點膠形成的環氧樹脂，其中若採用環氧樹脂作為填充材240，則填充材240可提供黏著與固定晶片210的效果，而可省略黏著層270。
每一第一引腳222的上表面222a、每一第二引腳224的上表面224a、接墊226以及重佈線路228上可具有第一金屬鍍層262。每一第一引腳222的上表面222a及其上的第一金屬鍍層262被包封於封裝膠體250內，而每一第二引腳224的上表面224a及其上的第一金屬鍍層262被包封於填充材240內。在此，第一金屬鍍層262可作為在形成第一引腳222與第二引腳224時的蝕刻罩幕，並有助於提高第一引腳222及第二引腳224與銲線230之間的接合性(bondibility)。更具體而言，第一引腳222與第二引腳224的材質例如是銅，而可選擇由鎳/金疊層組成的第一金屬鍍層262，使銲線230與第一金屬鍍層262表面的金層有效接合。類似地，每一第一引腳222的下表面222b與每一第二引腳224的下表面224b上可具有第二金屬鍍層264，且接墊226以及重佈線路228未被第二金屬鍍層264覆蓋。
下文進一步列舉多個實施例來說明製作前述半導體封裝結構的方法。在該些實施例中僅可以採用相同元件符號來表示相同或類似地元件，而相同或類似的步驟可能被簡略或省略說明，以清楚表達各實施例間的差異。
圖3A-3J繪示依照本發明之一實施例的一種半導體封裝製程。
首先，請參考圖3A-3C，提供一導電基板202，並且在導電基板202的頂面202a與背面202b上分別形成第一金屬鍍層262與第二金屬鍍層264。更詳細而言，形成第一金屬鍍層262與第二金屬鍍層264的方法例如是如圖3A所示，先形成一第一圖案化罩幕282於導電基板202的頂面202a上。導電基板202的頂面202a具有一晶片接著區域204。在本實施例中，第一圖案化罩幕282例如是乾膜光阻或是濕式光阻。接著如圖3B所示，電鍍形成第一金屬鍍層262於頂面202a被第一圖案化罩幕282所暴露的區域上。所形成的第一金屬鍍層262包括位於晶片接著區域204之外的多個第一引腳金屬圖案262a、位於晶片接著區域204之外的多個接墊金屬圖案262b、位於晶片接著區域204內的多個第二引腳金屬圖案262c以及分別連接於第二引腳金屬圖案262c以及接墊金屬圖案262b之間的多個重佈線路金屬圖案262d。然後，再如圖3C所示，移除第一圖案化罩幕282。
類似地，形成圖案化的第二金屬鍍層264的方法包括先如圖3A所示，形成一第二圖案化罩幕284於導電基板202的底面202b上。之後，如圖3B所示，電鍍形成第二金屬鍍層264於底面202b被第二圖案化罩幕284所暴露的區域上。然後，再如圖3C所示，移除第二圖案化罩幕284。
接著，如圖3D-3F所示，以第一金屬鍍層262為罩幕來半蝕刻導電基板202，以在導電基板202未被第一金屬鍍層262覆蓋的區域上形成凹陷208。在進行此半蝕刻步驟時，可如圖3D所示，在導電基板202的底面202b形成光阻層292，以覆蓋並保護第二金屬鍍層264。待半蝕刻步驟完成後，再如圖3F所示，移除光阻層292。
然後，如圖3G所示，形成填充材240於晶片接著區域204內的凹陷208內，以形成可供後續晶片210接合時的平坦區域。在此，形成填充材240的方法例如是貼附一乾膜於晶片接著區域204上或是在晶片接著區域204進行點膠。
之後，如圖3H所示，接合晶片210至導電基板202的晶片接著區域204。晶片210被放置於填充材240以及第二引腳金屬圖案262c上，並且進行打線製程，以藉由銲線230分別連接晶片210與接墊金屬圖案262b以及分別連接晶片210與第一引腳金屬圖案262a。晶片210可能藉由黏著層270配置於填充材240上。或者，若採用環氧樹脂等具有黏性的材料來形成填充材240，則填充材240本身即可提供黏著與固定晶片210的效果，而可省略黏著層270。
接著，如圖3I所示，形成封裝膠體250於導電基板202的頂面202a上，以使封裝膠體250包封晶片210以及銲線230，且封裝膠體250填滿凹陷208的其餘部分。之後，如圖3J所示，以第二金屬鍍層264為罩幕，由導電基板202的背側來蝕刻導電基板202，以形成位於晶片接著區域204之外的第一引腳222、位於晶片接著區域204之外的接墊226、位於晶片接著區域204內的第二引腳224以及分別連接於第二引腳224以及接墊226之間的重佈線路228。
經由前述圖3A-3J的步驟可以大致形成如圖2A所示的半導體封裝結構。本領域中具有通常知識者應能理解，前述圖3A-3J的步驟可依據實際需求來做合理的調整。例如，圖3B與3C所示的第二金屬鍍層264可以在圖3I的形成封裝膠體250的步驟之後才被形成於導電基板202的底面202b。此外，已知的各種製程方法可被考慮應用於前述步驟中，以達到相同或類似的效果。
圖4A-4I繪示依照本發明之另一實施例的半導體封裝製程。本實施例與前述圖3A-3J所示的實施例相似，兩者的主要差異在於：本實施例省略了形成填充材240的步驟，且在後續的步驟中使封裝膠體250填入所有的凹陷208，包括晶片210下方的凹陷208中。
圖4A-4I的製程簡述如下：首先，如圖4A-4C所示，提供導電基板202，並且藉由第一圖案化罩幕282電鍍形成圖案化的第一金屬鍍層262於導電基板202的頂面202a。第一金屬鍍層262包括位於晶片接著區域204之外的第一引腳金屬圖案262a、位於晶片接著區域204之外的接墊金屬圖案262b、位於晶片接著區域內的第二引腳金屬圖案262c以及分別連接於第二引腳金屬圖案262c以及接墊金屬圖案262b之間的重佈線路金屬圖案262d。此外，藉由第二圖案化罩幕284電鍍形成圖案化的第二金屬鍍層264於導電基板202的底面202b。
然後，如圖4D-4F所示，以第一金屬鍍層262為罩幕來蝕刻導電基板202，以在導電基板202未被第一金屬鍍層262覆蓋的區域上形成凹陷208。接著，如圖4G所示，打線接合晶片210至導電基板202的晶片接著區域204。此外，本實施例的半導體封裝結構可能包括一黏著層270，其配置於晶片210的底面與第二引腳之間。然後，如圖4H所示，形成封裝膠體250於導電基板202的頂面202a上，以使封裝膠體250包封晶片210以及銲線230，且封裝膠體250填滿晶片210下方的凹陷208以及晶片210外圍的凹陷208。
之後，如圖4I所示，以第二金屬鍍層264為罩幕來蝕刻導電基板202，以形成位於晶片接著區域204之外的第一引腳222、位於晶片接著區域204之外的接墊226、位於晶片接著區域204內的第二引腳224以及分別連接於第二引腳224以及接墊226之間的重佈線路228。
圖4B與4C所示的第二金屬鍍層264可以在圖4H的形成封裝膠體250的步驟之後才被形成於導電基板202的底面202b。此外，已知的各種製程方法可被考慮應用於前述步驟中，以達到相同或類似的效果。
圖5A-5J繪示依照本發明之又一實施例的半導體封裝製程。本實施例與前述圖3A-3J所示的實施例相似，兩者的主要差異在於：本實施例是以光阻來作為形成凹陷208的蝕刻罩幕。此外，本實施例所形成的第一金屬鍍層262的圖案也與前述實施例不同。更詳細而言，由於是採用光阻來作為蝕刻罩幕，因此本實施例僅需形成作為接點的第一引腳金屬圖案262a以及接墊金屬圖案262b，而可省略第二引腳金屬圖案262c以及重佈線路金屬圖案262d。相較於前述實施例以第一金屬鍍層262來作為蝕刻罩幕的方法，本實施例形成凹陷208時，導電基板202的上下兩側可以覆蓋相同的光阻材料，因此蝕刻液的選擇較為簡單。
圖5A-5J的製程簡述如下：首先，如圖5A-5C所示，提供導電基板202，並且藉由第一圖案化罩幕282電鍍形成圖案化的第一金屬鍍層262於導電基板202的頂面202a。第一金屬鍍層262包括位於晶片接著區域204之外的第一引腳金屬圖案262a以及位於晶片接著區域204之外的接墊金屬圖案262b。此外，藉由第二圖案化罩幕284電鍍形成圖案化的第二金屬鍍層264於導電基板202的底面202b。
然後，如圖5D所示，形成圖案化的光阻層294於導電基板202的頂面202a，以及形成光阻層292於導電基板202的底面202b。光阻層294包括位於晶片接著區域204之外的多個第一引腳光阻圖案294a、位於晶片接著區域204之外的多個接墊光阻圖案294b、位於晶片接著區域240內的多個第二引腳光阻圖案294c以及分別連接於第二引腳光阻圖案294c以及接墊光阻圖案294b之間的多個重佈線路光阻圖案294d。
之後，如圖5E所示，以光阻層294為罩幕來半蝕刻導電基板202，以在導電基板202未被光阻層294覆蓋的區域上形成凹陷208。接著，如圖5F所示，移除光阻層292與294。並且，如圖5G所示，形成填充材240於晶片接著區域204內的凹陷208內。
然後，如圖5H所示，接合晶片210至導電基板202的晶片接著區域204。晶片210被放置於填充材240上，並且藉由銲線230分別連接晶片210與接墊金屬圖案262b以及分別連接晶片210與第一引腳金屬圖案262a。之後，如圖5I所示，形成封裝膠體250於導電基板202的頂面202a上，以使封裝膠體250包封晶片210以及銲線230，且封裝膠體250填滿凹陷208的其餘部分。接著，如圖5J所示，以第二金屬鍍層264為罩幕來蝕刻導電基板202，以形成位於晶片接著區域204之外的第一引腳222、位於晶片接著區域204之外的接墊226、位於晶片接著區域204內的第二引腳224以及分別連接於第二引腳224以及接墊226之間的重佈線路228。
圖5B與5C所示的第二金屬鍍層264可以在圖5I的形成封裝膠體250的步驟之後才被形成於導電基板202的底面202b。此外，已知的各種製程方法可被考慮應用於前述步驟中，以達到相同或類似的效果。
圖6A-6I繪示依照本發明之再一實施例的半導體封裝製程。本實施例與前述圖5A-5J所示的實施例相似，兩者主要差異在於：本實施例省略了形成填充材240的步驟，且在後續的步驟中使封裝膠體250填入所有的凹陷208，包括晶片210下方的凹陷208中。
圖6A-6I的製程簡述如下：首先，如圖6A-6C所示，提供導電基板202，並且藉由第一圖案化罩幕282電鍍形成圖案化的第一金屬鍍層262於導電基板202的頂面202a。第一金屬鍍層262包括位於晶片接著區域204之外的第一引腳金屬圖案262a以及位於晶片接著區域204之外的接墊金屬圖案262b。此外，藉由第二圖案化罩幕284電鍍形成圖案化的第二金屬鍍層264於導電基板202的底面202b。
然後，如圖6D所示，形成圖案化的光阻層294於導電基板202的頂面202a，以及形成光阻層292於導電基板202的底面202b。光阻層294包括位於晶片接著區域204之外的多個第一引腳光阻圖案294a、位於晶片接著區域204之外的多個接墊光阻圖案294b、位於晶片接著區域240內的多個第二引腳光阻圖案294c以及分別連接於第二引腳光阻圖案294c以及接墊光阻圖案294b之間的多個重佈線路光阻圖案294d。
之後，如圖6E所示，以光阻層294為罩幕來半蝕刻導電基板202，以在導電基板202未被光阻層294覆蓋的區域上形成凹陷208。接著，如圖6F所示，移除光阻層292與294。並且，如圖6G所示，打線接合晶片210至導電基板202的晶片接著區域204。此外，本實施例的半導體封裝結構可能包括一黏著層270，其配置於晶片210的底面與第二引腳之間。
然後，如圖6H所示，形成封裝膠體250於導電基板202的頂面202a上，以使封裝膠體250包封晶片210以及銲線230，且封裝膠體250填滿晶片210下方的凹陷208以及晶片210外圍的凹陷208。之後，如圖6I所示，以第二金屬鍍層264為罩幕來蝕刻導電基板202，以形成位於晶片接著區域204之外的第一引腳222、位於晶片接著區域204之外的接墊226、位於晶片接著區域204內的第二引腳224以及分別連接於第二引腳224以及接墊226之間的重佈線路228。
圖6B與6C所示的第二金屬鍍層264可以在圖6H的形成封裝膠體250的步驟之後才被形成於導電基板202的底面202b。此外，已知的各種製程方法可被考慮應用於前述步驟中，以達到相同或類似的效果。
綜上所述，本發明提出的半導體封裝結構具有滿球墊的設計，除了在晶片外圍具有第一引腳，晶片下方更具有可作為接點的第二引腳，使得晶片下方的空間得以被有效利用，而有助於提高半導體封裝結構的接點密度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．傳統的aQFN封裝結構
110．．．晶片
122．．．晶片墊
124．．．引腳
130．．．銲線
140．．．封裝膠體
200．．．半導體封裝結構
202．．．導電基板
202a．．．導電基板的頂面
202b．．．導電基板的背面
204．．．晶片接著區域
208．．．凹陷
210．．．晶片
210a．．．晶片的底面
222．．．第一引腳
222a．．．第一引腳的上表面
222b．．．第一引腳的下表面
222c．．．第一引腳的上傾斜部
222d．．．第一引腳的下傾斜部
224．．．第二引腳
224a．．．第二引腳的上表面
224b．．．第二引腳的下表面
224c．．．第二引腳的上傾斜部
224d．．．第二引腳的下傾斜部
226．．．接墊
228．．．重佈線路
230．．．銲線
240．．．填充材
250．．．封裝膠體
250a．．．封裝膠體的下表面
262．．．第一金屬鍍層
262a．．．第一引腳金屬圖案
262b．．．接墊金屬圖案
262c．．．第二引腳金屬圖案
262d．．．重佈線路金屬圖案
264．．．第二金屬鍍層
270．．．黏著層
282．．．第一圖案化罩幕
284．．．第二圖案化罩幕
292．．．光阻層
294．．．光阻層
294a．．．第一引腳光阻圖案
294b．．．接墊光阻圖案
294c．．．第二引腳光阻圖案
294d．．．重佈線路光阻圖案
圖1繪示傳統的aQFN封裝結構。
圖2A為依照本發明之一實施例的一種半導體封裝結構的剖面圖。
圖2B為圖2A之半導體封裝結構的上視圖。
圖3A-3J繪示依照本發明之一實施例的一種半導體封裝製程。
圖4A-4I繪示依照本發明之另一實施例的半導體封裝製程。
圖5A-5J繪示依照本發明之又一實施例的半導體封裝製程。
圖6A-6I繪示依照本發明之再一實施例的半導體封裝製程。
200．．．半導體封裝結構
210．．．晶片
210a．．．晶片的底面
222．．．第一引腳
222a．．．第一引腳的上表面
222b．．．第一引腳的下表面
222c．．．第一引腳的上傾斜部
222d．．．第一引腳的下傾斜部
224．．．第二引腳
224a．．．第二引腳的上表面
224b．．．第二引腳的下表面
224c．．．第二引腳的上傾斜部
224d．．．第二引腳的下傾斜部
226．．．接墊
228．．．重佈線路
230．．．銲線
240．．．填充材
250．．．封裝膠體
250a．．．封裝膠體的下表面
262．．．第一金屬鍍層
264．．．第二金屬鍍層
270．．．黏著層

Claims (19)

  1. 一種半導體封裝結構，包括：一晶片；多個引腳(lead)，陣列配置於一平面上，該些引腳包括位於該晶片之外的多個第一引腳以及位於該晶片下方且鄰近(adjacent)該晶片的多個第二引腳，其中各該引腳包括：一上表面；一下表面；一上傾斜部，配置鄰近於各該引腳的一上表面；一下傾斜部，配置鄰近於各該引腳的一下表面；多個接墊，位於該晶片之外；多條重佈線路，分別連接於該些接墊與該些第二引腳之間；多條銲線，分別連接於該晶片與該些接墊之間以及該晶片與該些第一引腳之間；一填充材，填入(interposed)該晶片與該些第二引腳之間。一封裝膠體，形成於該晶片、該些接墊、該些重佈線路、該些銲線以及該些引腳上，以實質上覆蓋該些引腳的該些上傾斜部，且該些引腳的該些下傾斜部至少部分從該封裝膠體的一下表面向外延伸。
  2. 如申請專利範圍第1項所述之半導體封裝結構，更包括：一第一金屬鍍層，配置於每一第一引腳的該上表面、每一第二引腳的該上表面、該些接墊以及該些重佈線路上，其中每一第一引腳的該上表面及其上的該第一金屬鍍層被包封於該封裝膠體內，而每一第二引腳的該上表面及其上的該第一金屬鍍層被包封於該填充材內。
  3. 如申請專利範圍第1項所述之半導體封裝結構，更包括：一第二金屬鍍層，配置於每一第一引腳的該下表面與每一第二引腳的該下表面上，其中該些接墊以及該些重佈線路未被第二金屬鍍層覆蓋。
  4. 如申請專利範圍第1項所述之半導體封裝結構，其中該填充材的材質與該封裝膠體的材質相同。
  5. 如申請專利範圍第1項所述之半導體封裝結構，更包括一黏著層，配置於該晶片的一底面與該填充材之間。
  6. 一種半導體封裝製程，包括：提供一導電基板，該導電基板具有一頂面以及相對於該頂面的一背面，該導電基板的該頂面具有一晶片接著區域；形成圖案化的一第一金屬鍍層於該導電基板的該頂面，該第一金屬鍍層包括位於該晶片接著區域之外的多個第一引腳金屬圖案、位於該晶片接著區域之外的多個接墊金屬圖案、位於該晶片接著區域內的多個第二引腳金屬圖案以及分別連接於該些第二引腳金屬圖案以及該些接墊金屬圖案之間的多個重佈線路金屬圖案；形成圖案化的一第二金屬鍍層於該導電基板的該底面；以該第一金屬鍍層為罩幕來半蝕刻該導電基板，以在該導電基板未被該第一金屬鍍層覆蓋的區域上形成一凹陷；形成一填充材於該晶片接著區域內的該凹陷內；接合一晶片至該導電基板的該晶片接著區域，該晶片被放置於該填充材以及該些第二引腳金屬圖案上，並且藉由多條銲線分別連接該晶片與該些接墊金屬圖案以及分別連接該晶片與該些第一引腳金屬圖案；形成一封裝膠體於該導電基板的該頂面上，以使該封裝膠體包封該晶片以及該些銲線，且該封裝膠體填滿該凹陷的其餘部分；以及以該第二金屬鍍層為罩幕來蝕刻該導電基板，以形成位於該晶片接著區域之外的多個第一引腳、位於該晶片接著區域之外的多個接墊、位於該晶片接著區域內的多個第二引腳以及分別連接於該些第二引腳以及該些接墊之間的多條重佈線路。
  7. 如申請專利範圍第6項所述之半導體封裝製程，其中形成該填充材的方法包括貼附一乾膜於該晶片接著區域上或是在該晶片接著區域進行點膠。
  8. 如申請專利範圍第6項所述之半導體封裝製程，其中形成圖案化的該第一金屬鍍層的方法包括：形成一第一圖案化罩幕於該導電基板的該頂面上；以及電鍍形成該第一金屬鍍層於該頂面被該第一圖案化罩幕所暴露的區域上。
  9. 如申請專利範圍第6項所述之半導體封裝製程，其中圖案化的該第二金屬鍍層是在形成該封裝膠體於該導電基板的該頂面之後，才被形成於該導電基板的該底面。
  10. 一種半導體封裝製程，包括：提供一導電基板，該導電基板具有一頂面以及相對於該頂面的一背面，該導電基板的該頂面具有一晶片接著區域；形成圖案化的一第一金屬鍍層於該導電基板的該頂面，該第一金屬鍍層包括位於該晶片接著區域之外的多個第一引腳金屬圖案、位於該晶片接著區域之外的多個接墊金屬圖案、位於該晶片接著區域內的多個第二引腳金屬圖案以及分別連接於該些第二引腳金屬圖案以及該些接墊金屬圖案之間的多個重佈線路金屬圖案；形成圖案化的一第二金屬鍍層於該導電基板的該底面；以該第一金屬鍍層為罩幕來蝕刻該導電基板，以在該導電基板未被該第一金屬鍍層覆蓋的區域上形成一凹陷；接合一晶片至該導電基板的該晶片接著區域，並且藉由多條銲線分別連接該晶片與該些接墊金屬圖案以及分別連接該晶片與該些第一引腳金屬圖案；形成一封裝膠體於該導電基板的該頂面上，以使該封裝膠體包封該晶片以及該些銲線，且該封裝膠體填滿該凹陷；以及以該第二金屬鍍層為罩幕來蝕刻該導電基板，以形成位於該晶片接著區域之外的多個第一引腳、位於該晶片接著區域之外的多個接墊、位於該晶片接著區域內的多個第二引腳以及分別連接於該些第二引腳以及該些接墊之間的多條重佈線路。
  11. 如申請專利範圍第10項所述之半導體封裝製程，其中形成圖案化的該第二金屬鍍層的方法包括：形成一第二圖案化罩幕於該導電基板的該底面上；以及電鍍形成該第二金屬鍍層於該底面被該第二圖案化罩幕所暴露的區域上。
  12. 如申請專利範圍第10項所述之半導體封裝製程，其中圖案化的該第二金屬鍍層是在形成該封裝膠體於該導電基板的該頂面之後，才被形成於該導電基板的該底面。
  13. 一種半導體封裝製程，包括：提供一導電基板，該導電基板具有一頂面以及相對於該頂面的一背面，該導電基板的該頂面具有一晶片接著區域；形成圖案化的一第一金屬鍍層於該導電基板的該頂面，該第一金屬鍍層包括位於該晶片接著區域之外的多個第一引腳金屬圖案以及位於該晶片接著區域之外的多個接墊金屬圖案；形成圖案化的一第二金屬鍍層於該導電基板的該底面；形成圖案化的一光阻層於該導電基板的該頂面，該光阻層包括位於該晶片接著區域之外的多個第一引腳光阻圖案、位於該晶片接著區域之外的多個接墊光阻圖案、位於該晶片接著區域內的多個第二引腳光阻圖案以及分別連接於該些第二引腳光阻圖案以及該些接墊光阻圖案之間的多個重佈線路光阻圖案；以該光阻層為罩幕來半蝕刻該導電基板，以在該導電基板未被該光阻層覆蓋的區域上形成一凹陷；移除該光阻層；接合一晶片至該導電基板的該晶片接著區域，該晶片藉由多條銲線分別連接該晶片與該些接墊金屬圖案以及分別連接該晶片與該些第一引腳金屬圖案；形成一封裝膠體於該導電基板的該頂面上，以使該封裝膠體包封該晶片以及該些銲線，且該封裝膠體填滿該凹陷；以及以該第二金屬鍍層為罩幕來蝕刻該導電基板，以形成位於該晶片接著區域之外的多個第一引腳、位於該晶片接著區域之外的多個接墊、位於該晶片接著區域內的多個第二引腳以及分別連接於該些第二引腳以及該些接墊之間的多條重佈線路。
  14. 如申請專利範圍第13項所述之半導體封裝製程，其中形成圖案化的該第一金屬鍍層的方法包括：形成一第一圖案化罩幕於該導電基板的該頂面上；以及電鍍形成該第一金屬鍍層於該頂面被該第一圖案化罩幕所暴露的區域上。
  15. 如申請專利範圍第13項所述之半導體封裝製程，其中形成圖案化的該第二金屬鍍層的方法包括：形成一第二圖案化罩幕於該導電基板的該底面上；以及電鍍形成該第二金屬鍍層於該底面被該第二圖案化罩幕所暴露的區域上。
  16. 如申請專利範圍第13項所述之半導體封裝製程，其中圖案化的該第二金屬鍍層是在形成該封裝膠體於該導電基板的該頂面之後，才被形成於該導電基板的該底面。
  17. 一種半導體封裝製程，包括：提供一導電基板，該導電基板具有一頂面以及相對於該頂面的一背面，該導電基板的該頂面具有一晶片接著區域；形成圖案化的一第一金屬鍍層於該導電基板的該頂面，該第一金屬鍍層包括位於該晶片接著區域之外的多個第一引腳金屬圖案以及位於該晶片接著區域之外的多個接墊金屬圖案；形成圖案化的一第二金屬鍍層於該導電基板的該底面；形成圖案化的一光阻層於該導電基板的該頂面，該光阻層包括位於該晶片接著區域之外的多個第一引腳光阻圖案、位於該晶片接著區域之外的多個接墊光阻圖案、位於該晶片接著區域內的多個第二引腳光阻圖案以及分別連接於該些第二引腳光阻圖案以及該些接墊光阻圖案之間的多個重佈線路光阻圖案；以該光阻層為罩幕來半蝕刻該導電基板，以在該導電基板未被該光阻層覆蓋的區域上形成一凹陷；移除該光阻層；形成一填充材於該晶片接著區域內的該凹陷內；接合一晶片至該導電基板的該晶片接著區域，該晶片被放置於該填充材上，並且藉由多條銲線分別連接該晶片與該些接墊金屬圖案以及分別連接該晶片與該些第一引腳金屬圖案；形成一封裝膠體於該導電基板的該頂面上，以使該封裝膠體包封該晶片以及該些銲線，且該封裝膠體填滿該凹陷的其餘部分；以及以該第二金屬鍍層為罩幕來蝕刻該導電基板，以形成位於該晶片接著區域之外的多個第一引腳、位於該晶片接著區域之外的多個接墊、位於該晶片接著區域內的多個第二引腳以及分別連接於該些第二引腳以及該些接墊之間的多條重佈線路。
  18. 如申請專利範圍第17項所述之半導體封裝製程，其中形成該填充材的方法包括貼附一乾膜於該晶片接著區域上或是在該晶片接著區域進行點膠。
  19. 如申請專利範圍第17項所述之半導體封裝製程，其中圖案化的該第二金屬鍍層是在形成該封裝膠體於該導電基板的該頂面之後，才被形成於該導電基板的該底面。
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