TWI588949B - 具有整合式承載表面的微電子封裝 - Google Patents

具有整合式承載表面的微電子封裝 Download PDF

Info

Publication number
TWI588949B
TWI588949B TW103127154A TW103127154A TWI588949B TW I588949 B TWI588949 B TW I588949B TW 103127154 A TW103127154 A TW 103127154A TW 103127154 A TW103127154 A TW 103127154A TW I588949 B TWI588949 B TW I588949B
Authority
TW
Taiwan
Prior art keywords
wire
metal
conductive
bonding tool
component
Prior art date
Application number
TW103127154A
Other languages
English (en)
Other versions
TW201511197A (zh
Inventor
依利亞斯 穆罕默德
Original Assignee
英凡薩斯公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 英凡薩斯公司 filed Critical 英凡薩斯公司
Publication of TW201511197A publication Critical patent/TW201511197A/zh
Application granted granted Critical
Publication of TWI588949B publication Critical patent/TWI588949B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Description

具有整合式承載表面的微電子封裝
本案為一種微電子封裝，尤指一種具有整合式承載表面的微電子封裝。
例如半導體晶片的微電子裝置通常需要許多對於其他電子元件的輸入與輸出連接。半導體晶片或其他類似裝置的輸入與輸出接點通常設置成類似格柵的型態，其實質上覆蓋裝置的表面(通常稱為「區域陣列」)，或者設置成伸長的列，其可延伸平行於裝置的前表面的每一邊緣且相鄰於每一邊緣，或在前表面的中心中。通常，例如晶片的裝置必須實體安裝於基板上(例如印刷電路板)，且裝置的接點必須電連接於電路板的導電結構。
半導體晶片通常設置於封裝中，封裝促進在製造期間以及在安裝晶片於外部基板上(例如電路板或其他電路平板)的期間晶片的處理。例如，許多半導體晶片設置於適於表面安裝的封裝中。已經提出此種一般類型的數種封裝來用於多種應用。最一般的，此種封裝包含介電質元件(通 常稱為「晶片載體」)，具有形成為板狀或蝕刻金屬結構的端子在介電質上。這些端子通常藉由例如沿著晶片載體本身延伸的細線路之特徵以及藉由延伸於晶片接點與端子或線路之間的細引線或導線，而連接於晶片本身的接點。在表面安裝操作中，封裝係置於電路板上，使得封裝上的每一端子對準於電路板上的對應接墊。焊錫或其他接合材料設置於端子與接墊之間。藉由加熱組件來熔化或「迴焊」焊錫或者活化接合材料，封裝可永久地接合在定位。
許多封裝包含焊錫塊係為焊錫球的形式，通常直徑為大約0.1mm與大約0.8mm(5與30密爾)之間，附接於封裝的端子。具有焊錫球陣列從其底表面突伸的封裝通常稱為球柵陣列或「BGA(ball grid array)」封裝。其他封裝(稱為平面柵格陣列或「LGA(land grid array)」封裝)藉由形成自焊錫的薄層或平面而固定至基板。此種封裝可以很精小。一些封裝(通常稱為「晶片級封裝」)占據電路平板的面積係等於(或僅稍微大於)封裝中所併入的裝置的面積。這是有利的，因為它減小組件的整體尺寸，並且允許使用基板上的各種裝置之間的短互連，這接著限制了裝置之間的信號傳輸時間，且因此促成組件以高速操作。
已封裝的半導體晶片通常設置成「堆疊」的配置，其中例如提供一封裝於電路板上，且另一封裝係安裝於第一封裝的頂部上。這些配置可允許多個不同的晶片安裝於電路板上的單一面積內，且藉由提供封裝之間的短互連，可另外促成高速操作。通常，此互連距離僅稍微大於晶片本身的厚度。為了達成晶片封裝的堆疊內的互連，需要在每一封裝的兩側上(除了最頂部的封裝之外)提供用於機械與電連接的結構。這已經實行， 例如藉由提供接觸墊或平面於安裝有晶片之基板的兩側上，接墊藉由導電通孔或類似者而連接通過基板。已經使用焊錫球或類似者來橋接下基板的頂部上的接點至下個較高基板的底部上的接點之間的縫隙。焊錫球必須高於晶片的高度，以連接接點。堆疊式晶片配置與互連結構的範例係提供於美國專利申請案公開號第2010/0232129號中(「’129公開案」)，其揭示內容在此以引用之方式將其全部併入。
伸長柱或接腳形式的微接觸元件可用於連接微電子封裝至電路板，並且用於微電子封裝中的其他連接。在一些實例中，藉由蝕刻金屬結構來形成微接觸，金屬結構包含一或更多個金屬層來形成微接觸。蝕刻處理會限制微接觸的尺寸。傳統的蝕刻處理通常無法形成具有高度對最大寬度的大比率之微接觸，本文稱為「縱橫比」。很難或不可能形成微接觸陣列係具有可感知的高度與相鄰微接觸之間的超小間距或間隔。另外，藉由傳統的蝕刻處理所形成的微接觸的結構係受限的。已經發展出多種封裝，其使用打線來取代用於互連微電子封裝的伸長柱或接腳。但是，形成此種打線的速度與準確性有相當的挑戰性，特別是關於打線的端部的定位與一致高度。
本揭示案的一形式係關於用於形成具有一自由端部的一打線之一種方法。方法包含：接合一金屬打線的一端部至在一第一元件的一表面處的一導電元件，金屬打線的端部緊鄰於一接合工具的一表面，接合工具相鄰於一孔，金屬打線延伸通過孔；以及從孔拉出金屬打線的一預定 長度。之後，使用接合工具的表面來塑性地變形在表面與第一元件的表面處的一金屬元件之間的金屬打線的一區域。方法之後包含：使用接合工具來施加張力至金屬打線，以導致具有端部接合於導電元件之金屬打線的一第一部分從在塑性地變形的區域處的金屬打線的一剩餘部分分離，其中第一部分形成一打線，打線從接合端部延伸至遠離導電元件的打線的一自由端部。
在一範例中，金屬元件可為包含於第一元件內的一導電電路結構的一部分。導電電路結構的部分係選自一線路、一接墊、一電鍍線、一電源面、與一接地面之至少一者。
接合工具可為一瓷嘴(capillary)，且表面可為瓷嘴的一面。在一範例中，接合工具可為一接合楔形物，且表面可為接合楔形物的一面。
方法可另包含：移動接合工具至金屬元件之上的一位置，使得打線的長度的一部分係在表面與金屬元件之間。接合工具的移動可之後用於表面與接合端部之間的打線的一部分中的一第一彎曲。在施加壓力的步驟之後，方法可另包含：移動接合工具至一預定位置，預定位置緊鄰於打線的自由端部的一特定位置，藉此形成相鄰於接合端部的打線的一部分中的一第二彎曲。施加張力的步驟可導致第一彎曲的至少部分強化。在另一範例中，施加壓力與施加張力的步驟可賦予打線的一形狀，使得打線界定自由端部與基部之間的一軸，打線被彎曲，以延伸遠離一平面上的軸，全部的打線係實質上定位於在軸的單一側上的平面上。
金屬打線的塑性地變形的區域可界定一軸，軸係以至少一方向從打線的一相鄰部分的一軸位移。
導電元件可為在基板的表面處的複數導電元件之一者，且金屬元件可為在基板的表面處的複數金屬元件之一者。在此種範例中，施加張力的步驟可形成另一端部於打線的剩餘部分上，且方法可包含重複接合、拉出、塑性地變形、與施加張力的步驟，以形成複數打線係從至少一些導電元件延伸遠離至遠離導電元件的個別自由端部。此種方法可另包含形成一介電質封裝層，以至少部分覆蓋基板的表面與打線的部分，使得打線的未封裝部分係藉由打線未被封裝層覆蓋的至少端部而界定。
本揭示案的另一形式係關於用於製造一微電子封裝的一種方法。方法包含形成複數打線於一處理中的單元上。處理中的單元包含一基板，基板具有一第一表面與遠離處的一第二表面，複數導電元件係曝露於第一表面處，且複數金屬元件在基板的表面處並且界定為與導電元件分離。至少一些打線的形成包含：接合一金屬打線的一端部至導電元件的一者，金屬打線的端部緊鄰於一接合工具的一表面，接合工具相鄰於一孔，金屬打線延伸通過孔。形成另包含：從孔拉出金屬打線的一預定長度，且之後使用接合工具的表面來塑性地變形在表面與金屬元件的一者之間的金屬打線的一區域。使用接合工具，來施加張力至金屬打線，以導致具有端部接合於導電元件之金屬打線的一第一部分從在塑性地變形的區域處的金屬打線的一剩餘部分分離。第一部分形成一打線，打線從接合端部延伸至遠離導電元件的打線的一自由端部。之後形成一介電質封裝層於處理中的單元上。封裝層係形成為至少部分覆蓋第一表面與打線的部分，使得打線的未封裝部分係藉由未被封裝層覆蓋的打線的至少端部而界定。
方法可另包含：安裝一微電子元件至基板，且電互連微電子 元件於至少一些導電元件。
在一範例中，至少一些打線的形成可包含：在施加張力的步驟之前，形成一彎曲於打線段。在另一範例中，從剩餘部分分離的打線的第一部分可形成打線的尖部，其上界定了端部。在此種範例中，打線可界定基部與尖部之間的一第一直徑，且尖部可具有至少一維度係小於個別第一直徑。
本揭示案的另一形式係關於一種微電子封裝，其包含一基板，基板具有一第一表面；在第一表面處的複數導電元件；以及曝露於第一表面處並且界定為與導電元件分離的複數金屬元件。封裝另包含複數打線，其具有第一端部係接合於至少一些導電元件並且從處延伸遠離至遠離導電元件的個別自由端部。一介電質封裝層至少部分覆蓋基板的表面且完全覆蓋金屬元件。介電質封裝層另外覆蓋打線的部分，使得打線的未封裝部分係藉由打線未被封裝層覆蓋的至少自由端部而界定。
微電子封裝可另包含一微電子元件係安裝於基板上並且電連接於至少一些導電元件。
在一範例中，打線的至少一者可界定自由端部與其基部之間的一軸。此種打線可彎曲，以延伸遠離一平面上的軸，其中全部的打線係實質上定位於在軸的單一側上的平面上。
至少一些金屬元件可與在複數導電金屬接墊中的至少一些導電元件為單一件，使得金屬元件係界定為藉由延伸超過導電金屬接墊的部分而與導電元件分離，導電金屬接墊的部分的尺寸係用於接收打線的基部於其上。額外地或替代地，金屬元件可另外界定為藉由具有小於導電元 件的一直徑之一寬度而與導電元件分離。至少一些金屬元件可具有打線標記於其上。另外，至少一些打線可包含接合工具標記於其上。
10、10’‧‧‧微電子組件
12‧‧‧基板
14‧‧‧第一表面
15‧‧‧導電元件
16‧‧‧第二表面
17‧‧‧導電元件
18‧‧‧第一區域
20‧‧‧第二區域
22‧‧‧微電子元件
23‧‧‧接點
24‧‧‧主要表面
25‧‧‧導電凸塊
26‧‧‧承載部
28、28a、28b、28c‧‧‧導電元件
30‧‧‧接觸部
32‧‧‧打線
34‧‧‧基部
35‧‧‧基部端部
36‧‧‧自由端部
37‧‧‧邊緣表面
38‧‧‧端部表面
40‧‧‧端子
41‧‧‧通孔
42‧‧‧封裝層
44‧‧‧主要表面
46‧‧‧線路
48‧‧‧承載片
49‧‧‧彎曲部分
50‧‧‧軸
52‧‧‧第一部分
54‧‧‧第二部分
56‧‧‧頂峰部
58‧‧‧角度
60‧‧‧軸
62‧‧‧尖部
70‧‧‧瓷嘴
72、72’‧‧‧前端部
74‧‧‧打線
76‧‧‧面
78‧‧‧區域
110‧‧‧組件
112‧‧‧基板
114‧‧‧第一表面
116‧‧‧第二表面
122‧‧‧微電子元件
126‧‧‧承載部
128a、128b、128c‧‧‧導電元件
132a‧‧‧打線
134a、134B‧‧‧基部
136、136A‧‧‧端部
138‧‧‧端部
144‧‧‧表面
170‧‧‧瓷嘴
174‧‧‧打線
第1圖為本案較佳實施例之微電子封裝，其包含複數打線於其上；第2圖為類似第1圖的微電子封裝之示意側部示意圖；第3圖為第1圖的微電子封裝的詳細示意圖；第4-9圖為本案較佳實施例之另一製造方法的各種步驟期間的微電子封裝；第10A-10C圖係各種打線的詳細示意圖，其可根據本揭示案的方法來製造，並且可包含於類似於第2圖的微電子封裝之微電子封裝中；第11圖係第10A圖所示的打線的部分的進一步詳細視圖；第12與13圖本案的另一實施例，替代的製造方法的各種步驟期間的微電子封裝。
第14圖為一種系統，包含本案所述的微電子封裝。
請參照圖式，其中類似的元件符號係用於表示類似的特徵，根據本發明的實施例，第1圖為微電子組件10。第1圖的實施例係已封裝微電子元件之微電子組件，例如用於電腦或其他電子應用的半導體晶片組件。
第1與2圖的微電子組件10包含基板12，基板12具有第一表面 14與第二表面16。基板12通常為介電質元件，實質平坦。介電質元件為薄片狀。在特定的實施例中，介電質元件可包含一或更多層的有機介電質材料或複合介電質材料，例如(但不限於)：聚酰亞胺、聚四氟乙烯("PTFE",polytetrafluoro-ethylene)、環氧樹脂、環氧樹脂-玻璃、FR-4、BT樹脂、熱塑膠、或熱固性塑膠材料。第一表面14與第二表面16彼此平行，並且分隔一距離，垂直於表面14、16之距離界定基板12厚度。基板12的厚度在一般可接受的厚度範圍內，以用於特定應用。在一實施例中，第一表面14與第二表面16之間的距離係在大約25與500μm之間。針對此討論的目的，第一表面14之敘述可定位成相對或遠離第二表面16。此種敘述以及參考此種元件的垂直或水平位置而在本文所用的元件的相對位置的任何其他敘述係僅為了例示的目的，以對應於圖式內的元件的位置，且並非限制。
在一範例中，基板12分成第一區域18與第二區域20。第一區域18位於第二區域20之間，並且包含基板12的中心部分，且從中心向外延伸。第二區域20圍繞第一區域18並且延伸至基板12的外部邊緣。在此實施例中，基板本身沒有具體的分成兩區域；但是，標示區域係為了本文相關於應用至其或包含於其中的處理或特徵之討論的目的。
微電子元件22可安裝於第一區域18內的基板12的第一表面14。微電子元件22可為半導體晶片或另外的相似裝置。在第1圖的實施例中，微電子元件22係以熟知為「覆晶」或面向下的配置而安裝於第一表面14，其中微電子元件22上的接點23可面向第一區域18內的導電元件17並且藉由導電凸塊25(例如，焊錫凸塊、微柱、或類似者)而連接於導電元件17，導電凸塊25位於微電子元件22之下。在另外的配置中，微電子元件可 面向上安裝於基板上，且可藉由延伸於基板的面向外表面之上的打線引線而電連接於晶片上的導電結構。在此種範例中，打線引線可通過基板中的開孔並且可藉由包覆成型來封裝。在另一範例中，微電子元件可用傳統或「面向上」的方式安裝。在此種配置中，打線引線(未圖示)可用於電連接微電子元件至在第一表面14處的複數導電元件28的一些導電元件28。此種打線引線也可接合於基板12內的線路46或其他導電結構，線路46或其他導電結構接著連接至導電元件28。
導電元件28係在基板12的第一表面14處並且包含個別的接觸部30。當在本說明書中使用時，當導電元件為在具有介電質結構的另一元件的表面「處」時，表示導電結構可用於接觸於一理論點，理論點移動於垂直於介電質結構的表面的方向中、從介電質結構外部朝向介電質結構的表面。因此，在介電質結構的表面處的端子或其他導電結構可從此種表面突伸；可齊平於此種表面；或可相對於此種表面凹陷且透過介電質中的孔或凹部而曝露。
導電元件28可為平坦且薄的元件，其中接觸部30係在基板12的第一表面14處。導電元件28可為固體金屬材料，例如銅、金、鎳、或此種應用可接受的其他材料，包含包含有銅、金、鎳、或其組合之一或更多者的各種合金。在一範例中，導電元件28可為圓形，且可互連於彼此之間或藉由線路(未圖示)互連至微電子元件22。
如同第3圖的詳細視圖所示，至少一些導電元件28可另包含承載部26，承載部26也在基板12的第一表面14處。承載部26可連接接觸部30且從接觸部30向外延伸或相鄰於接觸部30，且可提供額外的金屬表面或 區域來用於組件10的額外特徵的製造，如同下面將討論的。接觸部30與承載部26兩者在至少一些導電元件28內的配置使導電元件28有長形的形狀，例如橢圓形、圓角的矩形、梨子或茄子形狀的配置。其他形狀與配置也可以實行下面敘述的承載部26的功能。做為另外的替代例，一些導電元件28可僅包含承載部26而沒有接觸部30，且可出現在基板12的表面14處，基板12的表面14之導電元件28可同時包含接觸部30與承載部26兩者，或僅包含接觸部30。
導電元件28可形成在基板12的第二區域20內。另外，在一些範例中，一些導電元件17可形成於第一區域18內。當以第1與2圖的覆晶配置來安裝微電子元件22時，此種配置特別有用。在此種範例中，導電元件15可沒有承載部。
至少一些導電元件28可互連基板12的第二表面16處之對應的端子40(例如導電接墊)。使用基板12中的通孔41，可完成此種互連，通孔41可為有襯裡者，或充填有導電金屬，充填導電金屬與導電元件28,40相同的材料。選擇性地，導電元件40可藉由基板12上的線路而另外互連。
微電子組件10另包含複數打線32，打線32接合至接觸部30的一些導電元件28。打線32在基部34處接合至導電元件28並且延伸至基部34與基板12的對應自由端部36。打線32的端部36的位置不是固定的，因為它們不連接或接合至微電子元件22或微電子組件10內的任何其他導電結構，導電結構接著連接至微電子元件22。換句話說，自由端部36可用於電連接(直接或間接地(如同透過焊錫球或本文討論的其他特徵))連接至組件10外部的元件的導電結構，例如另一個此種組件10、微電子元件、或微 電子封裝。事實上，端部36藉由例如封裝層42(繪示在第2圖中)固定位置中或者接合或電連接至另一外部元件並不表示它們就此固定。反之，基部34才是固定的，因為基部34直接或間接地電連接於微電子元件22。如第2圖所示，基部34形狀為圓的，打線32位於基部34與端部36之間，端部36從邊緣表面(例如，如同第10A-C圖所示)向外延伸。基部34的特定尺寸與形狀可根據下述來改變：打線32的材料類型、打線32與導電元件28之間的連接的特定強度、或打線32的特定處理。打線32方法係敘述於Otremba的美國專利第7,391,121號以及美國專利申請案公開號第2012/0280386(「'386公開案」)號與第2005/0095835號(「'835公開案」，其敘述可視為打線的一種形式之楔形接合)中，其內容在此引用併入。替代的配置也可能將打線32接合至基板12的第二表面16上的導電元件。
打線32可為導電材料，例如銅、金、鎳、焊錫、鋁或類似者。另外，打線32可為材料之組合，例如導電材料(例如銅或鋁)的核心之上施加有塗覆。塗覆可為第二導電材料，例如鋁、鎳或類似者。另外，塗覆可為絕緣材料，例如絕緣護套。在一範例中，打線32可具有大約15μm與150μm之間的厚度(亦即，在橫越打線的長度之維度中)。在其他範例中，包含使用楔形接合，打線32可具有高達大約500μm的厚度。通常，使用專門的設備將打線形成於導電元件上，例如接觸部30內的導電元件28。
關於打線的形成，打線時前端要壓低並加熱，以接合表面，一般而言，可形成球或球狀的基部34來接合導電元件28的表面。打線線段的長度係從接合工具拉出，接合工具可之後在特定長度處切斷打線。楔形接合(其可用於鋁的打線，舉例來說)係一種處理，其中打線的加熱部分 被拖拉橫越接收表面，以形成大體上平行於表面的楔形物。楔形接合的打線可之後向上彎曲(若需要的話)，且在切斷之前延伸至特定長度或位置。在特定的實施例中，打線的橫剖面可為圓柱形。另外，從工具饋送來的打線(打線或楔形接合的打線)可具有多邊形的橫剖面，例如矩形或梯形，舉例來說。
打線32的自由端部36具有端部表面38。端部表面38至少形成陣列接點的一部分，陣列接點係由複數打線32的個別端部表面38所形成。第1圖之接點陣列為端部表面38所形成的範例樣式。此種陣列可為區域陣列配置，其變化型可使用本案所述的結構來實施。此種陣列可電性與機械性連接微電子組件10至另一微電子結構(例如至印刷電路板(PCB))或至其他已封裝的微電子元件。在此種堆疊配置中，打線32與導電元件28可傳送多個電子信號，各具有不同的信號電位，以允許不同的信號被單一堆疊中的不同微電子元件處理(在一範例中，導電元件28可利用延伸通過基板12的通孔(未圖示)而連接於第二表面16處的額外接點，或者導電元件28本身可為通孔)。焊錫塊可用於互連此種堆疊中的微電子組件，例如藉由電性與機械性附接端部表面至導電元件。使用具有打線的曝露端部陣列之微電子組件的範例堆疊配置係顯示與敘述在例如’386公開案中。
微電子組件10另包含封裝層42，封裝層42由介電質材料形成。如第2圖所示，封裝層42延伸於基板12的第一表面14的部份未被微電子元件22或導電元件28占據或覆蓋。相似的，封裝層42延伸於導電元件28的部分，包含未被打線32的基部34覆蓋的接觸部30的區域與承載部26。封裝層42也可覆蓋微電子元件22、打線32(包含基部34與其邊緣表面37的至少 一部分)。打線32的一部分可維持未被微封裝層42覆蓋，其可稱為未封裝部，藉此使打線可用於電連接位於封裝層42外部的元件或結構。如圖所示，表面(例如封裝層42的主要表面44)可間隔於基板12的第一表面14一距離，距離足夠大來覆蓋微電子元件22。因此，微電子組件10的範例(其中打線32的端部38齊平於表面44)將包含高於微電子元件22的打線32以及用於覆晶連接的任何下方的焊錫凸塊。但是，也可能用於封裝層42的其他配置。例如，封裝層可具有多個表面係具有變化的高度。在此種配置中，表面44(其內定位有端部38)可高於或低於微電子元件22上表面。
封裝層42用以保護微電子組件10內的其他元件，特別是打線32。這允許更穩固耐用的結構，其較不可能在測試時、或者運輸或組裝至其他微電子結構的期間受到損傷。封裝層42可由絕緣特性的介電質材料形成，例如美國專利申請案公開號第2010/0232129號中所述，其內容在此引用併入。
第2圖的打線32的範例(其進一步詳細繪示在第10A與11圖中)界定特定的曲線形狀，藉由使用導電元件28的承載部26來製作打線32的處理，可賦予曲線形狀至打線32。此種方法進一步連結第4-9圖敘述於下。打線32的路徑係從端部表面38沿著軸50對準於打線32的基部端部35，基部端部35緊鄰於基部34。在第2與10A圖的打線32的範例中，軸大體上垂直於接觸部30，使得端部表面38位於基部端部35之上。此種配置對於陣列中的複數打線32有用，其中封裝層42主要表面44上的連接陣列具有大體上匹配於打線32所個別接合之導電元件28之間距。在此種配置中，軸50相對於接觸部30可有一角度，使得端部表面38稍微從基部端部35偏移，但是仍舊位 於基部34之上。在此種範例中，軸50相對於接觸部30可以有85°至90°的角度。
打線32之配置可使得其第一部分52(其上界定了端部表面38)大體上沿著軸50的一部分延伸。第一部分52之長度係為打線32的總長度大約10%與50%之間(如同軸50的長度界定的，舉例來說)。打線32的第二部分54為曲線狀或彎曲，從相鄰於第一部分52的位置偏離軸延伸至頂峰部56，頂峰部56間隔軸50。第二部分54進一步彎曲，沿著軸50定位在基部端部35或附近的位置，且從基部端部35到頂峰部56也延伸偏離軸50。注意，第一部分52不需要是直的或完全沿著軸50，且可有某種程度的彎曲或變化。另須注意，第一部分52與第二部分54之間突然或平順的轉折係因本身可以彎曲。但是注意，第2與10A圖的打線32(包含第二部分54)係另外配置於，與軸50相同的單一平面上。
另外，打線32的第一部分52與第二部分54之配置，使得不相交於軸50之其任何部分係都在軸50的一側上。亦即，第一與第二部分52,54的一些部分可在第二部分54界定的彎曲形狀的頂峰部56相反之軸50的一側上；但是，任何此部分在軸50相交之打線32的區域中。換句話說，打線32的第一與第二部分52與54之配置，不完全橫越軸50，使得第一與第二部分52與54僅在軸50的單一側上。在第10A圖的範例中，打線32所呈現的平面如圖的頁面。
第10B與10C圖為打線32的範例，其中端部36不直接位於其個別基部34上。亦即，基板12的第一表面14有兩個橫向方向(以實質上界定一平面)，打線32的端部36可從基部34的對應橫向方向，位移於其中一橫向方向。如第10B與10C圖所示，打線32如第10A圖的形狀，且端部36係對 準於緊鄰其基部34之打線32的部分，以界定軸50。打線32可包含延伸於軸50的第一部分52以及彎曲的第二部分54，在其單一側上間隔於軸50的頂峰部56，以界定沿著軸50延伸的平面。但是，第10B與10C圖的打線32之配置，可使得軸50相對於接觸部30成一角度，例如小於85°。在另一範例中，角度58可為大約30°與75°之間。
打線32可使得第二部分54內的頂峰部56在角度58外(如第10B圖所示)或在角度58內(如第10C圖所示)。另外，軸50可相對於接觸部30成一角度，使得打線32的端部表面38在相對於接觸部30的多個橫向方向中橫向位移。在此例中，第二部分54與軸50所界定的平面本身相對於接觸部30及/或第一表面14可成一角度。此角度可等於或不同於角度58。亦即，端部36相對於基部34的位移可在兩橫向方向中，且各方向的位移可為相同或不同的距離。
在整個組件10中，打線32可以不同方向與不等數量來配置。此配置允許組件10在表面44層上，相對於基板12層，可以有不同架構的陣列。例如，陣列在表面44上可比在第一表面14的位準處覆蓋較小的整體區域或具有較小的間距，相較於基板12的第一表面14。另外，一些打線32之端部38係定位於微電子元件22之上，以調節不同尺寸的已封裝微電子元件的堆疊配置。在另一範例中，打線132可配置成使得一個打線132A的端部136A係實質上定位於另一個打線134B的基部134B之上，打線134B的端部132B係定位於別處。此種配置可稱為改變接點陣列內的接點端部表面136的相對位置，相較於在第二表面116上的對應接點陣列的位置來說。在此種陣列內，接點端部表面的相對位置之改變或變化，取決於微電子組件的應 用或其他要求。
第10B-10C圖為微電子組件10的另外實施例，其具有打線32，打線32具有相對於基部34橫移位置的端部36。在第10C圖的實施例中，打線32藉由彎曲部分49達成此橫移。彎曲部分49可在打線處理期間於額外的步驟中形成，且當打線部分被拉出特定長度時發生。此步驟可使用打線設備來實行，其可包含使用單一機器。
在第2圖的組件10的變化例中，打線32可有角度，如同第10B圖、第10C圖所示或其組合，使得打線32的至少一些端部36延伸進微電子元件22的主要表面24上的區域中。此種區域可藉由微電子元件22的外部周邊來界定並且可從處延伸向上。
如第11圖所示，至少一些打線的自由端部36可具有非對稱的配置，打線32的尖部62上的端部表面38係窄於其鄰近部分(至少在一方向中)。藉由製造自由端部36的處理，自由端部36的窄尖部62可賦予在打線32上，其範例另外討論於下。如同所示，窄尖部62可偏移，使得軸50可從打線32中心軸60偏移。另外，端部表面38的尖心64(Centroid)可沿著軸60，使得它從相鄰的打線部分偏移。打線32的尖部62也可在垂直於第11圖所示的維度之方向中變窄，或可為與打線32的相鄰部分相同的寬度，或可為較寬。
第4圖至第9圖為微電子組件10的製造方法的各步驟的微電子組件10。第4圖的微電子組件10’，其中微電子元件22已經在第一區域18與第一表面14電性與機械性連接至基板12，如第1圖與第2圖所述。第4圖之打線工具的瓷嘴70緊鄰基板12的第一表面14。瓷嘴70以及相關接合工具(未圖示)可大體上為上面敘述的那種，且可配置來加熱打線74的前端部72與 對準瓷嘴70(以及打線74的前端部72)於導電元件28的接觸部30，而形成複數連續的打線於組件中，打線74的前端部72通過瓷嘴70且對準瓷嘴70。藉由適當地移動瓷嘴70將已加熱的自由端部72壓抵接觸部30，之後形成打線的基部34z以接合至接觸部30，如第5圖。
打線74的長度已經從瓷嘴70抽拉出，以打線要形成的高度之適當距離，延伸於基板12的表面14之後(第6圖)，切斷打線74並且適當地定位。如第7圖，藉由移動瓷嘴70至導電元件28的承載部26之上的位置，開始切斷與定位。如第7圖，瓷嘴70定位在相同導電元件的承載部26上，其中基部34接合於接觸部30內。下面討論其他範例，其中瓷嘴70定位在另一導電元件28的承載部26之上，包含只有承載部26的導電元件28。在瓷嘴70適當地定位之後，它朝向承載表面26擠壓，其中承載表面26與瓷嘴70的面76之間的打線74的部分可從打線74向外延伸。之後施加壓力至打線，以移動面76朝向接觸部30，這將壓縮打線74於其間，導致區域78中的打線74的塑性變形，例如打線的平坦化或壓縮。透過此種變形，打線74的區域78變得比打線74的任一側上的剩餘部分更不牢固，且比基部34與接觸部30之間的接合更不牢固。例如，相對於打線74的任一側上的打線74的剩餘部分，區域78可稍微平坦化、壓縮、或扭曲。
在打線74的區域78的變形之後，瓷嘴70之後朝向將形成打線32的自由端部36之最終特定位置移動回去，如第8圖。此位置可直接在基部34之上，或者稍微偏移，參考第10B圖與第10C圖所述。瓷嘴70的位置可大致在自由端部36的特定橫向區域中，且可以比特定的最終位置剛好有點比較靠近第一表面14。另外，打線可維持部分彎曲，形狀係類似於上面討論 的第一部分52與第二部分54的最終打線32的形狀。
瓷嘴70可之後移動離開表面14，以施加張力至瓷嘴70與基部34之間的打線74段(其可夾持或固定於瓷嘴70內)。此張力導致打線74在區域78內斷裂，如同第9圖所示，打線74之區域78分開後，可形成打線32與自由端部32的尖部62(其中界定端部表面38)。區域78的剩餘部分維持在打線74的新的前端部72’上。可以重複這些步驟於基板12的表面14處的其他導電元件28上，以形成打線32陣列。
根據上面討論，使用導電元件28的承載部26可以提供特定的表面，形成打線32的期間，可在特定的表面上形成打線74的區域78。使用導電元件30是有利的，因為做成導電元件30的金屬材料比基板12的材料更堅硬，因此，在瓷嘴70的施力下，較不易受損傷。另外，藉由導電元件28或承載表面26，可維持特定接觸部30的整體性。例如，打線74相抵於承載部26的壓縮，可導致其上的表面刮擦，這可能負面影響基部34與接觸部30之間的接合的強度，如果此種刮擦存在於其上的話。
導電元件28的承載部26之配置，可來用以壓抵打線74，如上所述，承載部26的形狀係基於使用涉及之因素而異。例如，承載部26之定位可相對於接觸部30，延伸離開一距離，距離足以讓瓷嘴70移動打線74，離開基部34，以形成打線32的最終特定高度。另外，承載部26的寬度可足夠延打線74的寬度(當接觸於此時)。換句話說，承載部26的最終寬度至少等寬於區域78(其可能受打線74的計量器或直徑影響)。
在形成特定數量的打線32之後，藉由沉積樹脂在微電子組件10上，可形成封裝層42。藉由將組件10放置於適當配置的模具中，可完成 此事，模具有腔部，腔部係可接收組件10之封裝層42的特定形狀。此種模具以及形成封裝層的方法可如美國專利申請案公開號第2012/0232129號(「'386公開案」)所示，其揭示內容在此引用併入。封裝層之形成，使得一開始其表面44係間隔於打線32的端部表面38之上。為了曝露端部表面38，在端部表面38上的封裝層42的部分可移除，曝露出實質上齊平於端部表面38的新表面44。另外，封裝層42之形成，可使得表面44已經實質上齊平於端部表面38，或者使得表面44定位於端部表面38之下。移除封裝層42的部分(若需要的話)可藉由研磨、乾蝕刻、雷射蝕刻、濕蝕刻、研磨(lapping)、或類似者來達成。若需要的話，打線32的自由端部36的部分也可在相同或額外步驟中移除，以達成實質上對齊於表面44的實質上平坦端部表面38。
承載部26可用於第4-9圖討論的打線形成方法的變化例中，以達成不同高度的打線132a，如同第12與13圖所示。具體而言，如第12圖所示，數個不同的導電元件128可在基板112的表面114處。基板112上可包含每個不同種類的導電元件128的一個或複數，取決於打線132的特定配置與其特定布局或陣列。如同所示的範例中，一些導電元件128a僅包含接觸部130。其他導電元件128b包含接觸部130與承載部126兩者，以相似於上面相關於第3圖所討論的那些配置之配置，舉例來說。還有其他導電元件128c可僅包含承載部126。此種導電元件128c可為適當大小與個別承載部126，其可相似於第3圖所示的承載部26，但是缺少附接的接觸部30。另外，此種導電元件128c可為承載片48的形式，其範例在第3圖中。承載片可圍繞導電元件28陣列的區域的整個外部，或可部分沿著此種陣列的外部延伸，或可散置於其間。
如第12圖，打線174可接合於導電元件128a的基部134a處，導電元件128a僅包含接觸部130。相同的打線174可之後壓縮(以類似於先前相關於第7圖討論的方式)相抵於不同導電元件128的承載部126，例如，導電元件128b的承載部。在打線174以類似於上面相關於第8與9圖討論的方式切斷之後，如此做可以調節已經抽拉出瓷嘴170的打線174的較長長度，這接著可導致較高的打線132a，如同第13圖所示。類似的，基部134b可形成於導電元件128b的接觸部130上，且打線段174可壓縮相抵於導電元件128c(導電元件128c僅包含承載部126)，以形成打線於導電元件128b上，大體相同於打線132a的高度。針對包含超過兩列打線的類似基板，具有接觸部與承載部兩者的額外導電元件可設於導電元件128c與128a之間。使用類似的原理可做出其他配置。
雖然本發明在此已經參照特定實施例來敘述，可瞭解到，這些實施例僅是本發明的應用與原理的例示。因此，可瞭解到，可對例示的實施例做出各種修改，且可設想出其他配置，而未偏離所附申請專利範圍所界定之本發明的範圍與精神。
10‧‧‧微電子組件
12‧‧‧基板
14‧‧‧第一表面
16‧‧‧第二表面
17‧‧‧導電元件
18‧‧‧第一區域
20‧‧‧第二區域
22‧‧‧微電子元件
23‧‧‧接點
25‧‧‧導電凸塊
26‧‧‧承載部
28‧‧‧導電元件
30‧‧‧接觸部
32‧‧‧打線
36‧‧‧自由端部
38‧‧‧端部表面
40‧‧‧端子
41‧‧‧通孔
42‧‧‧封裝層
44‧‧‧主要表面

Claims (14)

  1. 一種微電子封裝的方法，用於形成一打線之一自由端部，該方法包含：接合一金屬打線的一端部至位於一第一元件的一表面的一導電元件，該金屬打線的端部緊鄰於一接合工具的一表面，該接合工具相鄰於一孔，該金屬打線延伸通過該孔；從該孔拉出該金屬打線的一預定長度；接著使用該接合工具的該表面來塑性變形位於該接合工具的該表面與該第一元件的該表面的一金屬元件之間的該金屬打線的一區域；及接著使用該接合工具來施加張力至該金屬打線，以導致具有接合於該導電元件之該端部之該金屬打線的一第一部分，從位於該塑性變形的區域的該金屬打線的一剩餘部分分離，該第一部分形成一打線，該打線從該接合端部延伸至遠離該導電元件的該打線的一自由端部；其中該導電元件係為該基板的該表面的複數導電元件之一個，且該金屬元件係為該基板的該表面的複數金屬元件之一個，且其中施加張力的該步驟，係形成另一端部於該打線的該剩餘部分上，該方法包含重複接合、拉出、塑性變形、與施加張力的該步驟，其所形成之複數打線，係從至少一些該導電元件延伸離開至遠離該導電元件的個別自由端部。
  2. 如申請專利範圍第1項之方法，其中該金屬元件係為該第一元件內的一導電電路結構的一部分。
  3. 如申請專利範圍第1項之方法，其中該接合工具係為一瓷嘴，且該接合工具的該表面係為該瓷嘴的一面。
  4. 如申請專利範圍第1項之方法，其中該接合工具係為一接合楔形物，且該接合工具的該表面係為該接合楔形物的一面。
  5. 如申請專利範圍第1項之方法，另包含：移動該接合工具至該金屬元件上的一位置，使得該打線長度的一部分係位於該接合工具的該表面與該金屬元件之間，該接合工具之該移動形成之一第一彎曲，係位於該接合工具的該表面與該接合端部之間的該打線的一部分中。
  6. 如申請專利範圍第1項之方法，其中施加壓力與施加張力的該步驟賦予一形狀於該打線上，使得該打線界定之一軸，係位於該自由端部與該基部之間，而該打線之彎曲，係延伸遠離一平面上的該軸，且全部的該打線之位置，係實質位於在該軸的單一側上。
  7. 如申請專利範圍第1項之方法，其中該金屬元件與一導電金屬接墊中的該導電元件係構成單一元件(Unitary)，該金屬元件之界定，係藉由延伸超過該導電金屬接墊的一部分而與該導電元件分離，該導電金屬接墊的該部分之尺寸，係用於接合該金屬打線，以形成該接合端部。
  8. 如申請專利範圍第1項之方法，其中複數導電元件與複數金屬元件係位於該基板的該表面，該導電元件與金屬元件之配置，係沿著該表面成為一對，且其中接合該打線的該導電元件係在一第一對中。
  9. 如申請專利範圍第1項之方法，其中施加壓力的該步驟，係產生接合工具標記於該打線的該塑性變形的區域內。
  10. 如申請專利範圍第1項之方法，其中該金屬打線的該塑性變形的區域所界定之一軸，係以至少一方向，從該打線的一相鄰部分的一軸位移。
  11. 如申請專利範圍第1項之方法，其中該金屬打線的一第一表面部分係藉由該接合工具的該表面而壓縮於一第一方向中。
  12. 如申請專利範圍第1項之方法，另包含：形成一介電質封裝層，藉以至少部分覆蓋該基板的該表面與該打線的部分，使得該打線的未封裝部分係藉由未被該封裝層覆蓋的該打線的至少該端部而界定。
  13. 如申請專利範圍第1項之方法，其中該複數導電元件與該複數金屬元件的至少一些，係配置為導電元件與金屬元件對的一陣列，該陣列具有一預定數量的列，且其中接合的該步驟的一實例係實行於一第一列中的一導電元件，且使用該表面來塑性變形該金屬打線的一區域之該對應步驟，係實行於一第二列中的一金屬元件上。
  14. 一種微電子封裝的方法，用於製造一微電子封裝，該方法包含：形成複數打線於一處理中的單元上，該處理中的單元包含：一基板，該基板具有一第一表面與相隔之一第二表面；複數導電元件，係曝露於該第一表面處；以及複數金屬元件，該複數金屬元件在該基板的該表面，並且界定為與該導電元件分離；至少一些該打線的形成包含：接合一金屬打線的端部至該導電元件之一者，該金屬打線的該端部緊鄰於一接合工具的一表面，該接合工具相鄰於一孔，該金屬打線延伸通過該孔；從該孔拉出一預定長度之該金屬打線；之後使用該接合工具的該表面來塑性變形位於該接合工具的該表面與該金屬元件之一者之間的該金屬打線的一區域；及之後使用該接合工具來施加張力至該金屬打線，以導致具有接合於該導電元件之該端部之該金屬打線的一第一部分從該塑性變形的區域的該金屬打線的一剩餘部分分離，該第一部分形成一打線，該打線從該接合端部延伸至遠離該導電元件之該打線的一自由端部；及形成一介電質封裝層於該處理中的單元上，其中該封裝層之形成，係至少部分覆蓋該第一表面與該打線的部分，使得該打線的未封裝部分係藉由該打線未被該封裝層覆蓋的至少該端部而界定。
TW103127154A 2013-08-08 2014-08-07 具有整合式承載表面的微電子封裝 TWI588949B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/962,332 US9685365B2 (en) 2013-08-08 2013-08-08 Method of forming a wire bond having a free end

Publications (2)

Publication Number Publication Date
TW201511197A TW201511197A (zh) 2015-03-16
TWI588949B true TWI588949B (zh) 2017-06-21

Family

ID=51453843

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103127154A TWI588949B (zh) 2013-08-08 2014-08-07 具有整合式承載表面的微電子封裝

Country Status (3)

Country Link
US (1) US9685365B2 (zh)
TW (1) TWI588949B (zh)
WO (1) WO2015021277A2 (zh)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
JP2015072983A (ja) * 2013-10-02 2015-04-16 イビデン株式会社 プリント配線板、プリント配線板の製造方法、パッケージ−オン−パッケージ
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9659848B1 (en) * 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
CN106941101A (zh) * 2016-01-05 2017-07-11 恒劲科技股份有限公司 封装基板及其制作方法
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
CN107991572B (zh) * 2017-10-24 2020-04-03 大唐微电子技术有限公司 一种芯片顶层覆盖完整性保护方法及装置
US20190254546A1 (en) * 2018-02-22 2019-08-22 General Electric Company Neural multielectrode arrays and their manufacture and use
US11764161B2 (en) * 2019-12-06 2023-09-19 Micron Technology, Inc. Ground connection for semiconductor device assembly
CA3235026A1 (en) * 2021-10-15 2023-04-20 Thomas M. LIJNSE Microneedle and array and method of fabricating same
TWI812124B (zh) * 2022-03-28 2023-08-11 李銘洛 電子模組及其承載結構與製法
CN116754627B (zh) * 2023-08-21 2024-03-08 苏州矽联传感科技有限公司 一种生物电极制作方法、生物电极及生物传感装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3430835A (en) * 1966-06-07 1969-03-04 Westinghouse Electric Corp Wire bonding apparatus for microelectronic components
US4213556A (en) * 1978-10-02 1980-07-22 General Motors Corporation Method and apparatus to detect automatic wire bonder failure
US4327860A (en) * 1980-01-03 1982-05-04 Kulicke And Soffa Ind. Inc. Method of making slack free wire interconnections

Family Cites Families (544)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1439262B2 (de) 1963-07-23 1972-03-30 Siemens AG, 1000 Berlin u. 8000 München Verfahren zum kontaktieren von halbleiterbauelementen durch thermokompression
US3358897A (en) 1964-03-31 1967-12-19 Tempress Res Co Electric lead wire bonding tools
US3623649A (en) 1969-06-09 1971-11-30 Gen Motors Corp Wedge bonding tool for the attachment of semiconductor leads
DE2119567C2 (de) 1970-05-05 1983-07-14 International Computers Ltd., London Elektrische Verbindungsvorrichtung und Verfahren zu ihrer Herstellung
DE2228703A1 (de) 1972-06-13 1974-01-10 Licentia Gmbh Verfahren zum herstellen einer vorgegebenen lotschichtstaerke bei der fertigung von halbleiterbauelementen
JPS5150661A (zh) 1974-10-30 1976-05-04 Hitachi Ltd
US4067104A (en) 1977-02-24 1978-01-10 Rockwell International Corporation Method of fabricating an array of flexible metallic interconnects for coupling microelectronics components
US4422568A (en) 1981-01-12 1983-12-27 Kulicke And Soffa Industries, Inc. Method of making constant bonding wire tail lengths
US4437604A (en) 1982-03-15 1984-03-20 Kulicke & Soffa Industries, Inc. Method of making fine wire interconnections
JPS59189069A (ja) 1983-04-12 1984-10-26 Alps Electric Co Ltd 電気部品の端子のハンダ塗布装置
JPS61125062A (ja) 1984-11-22 1986-06-12 Hitachi Ltd ピン取付け方法およびピン取付け装置
US4604644A (en) 1985-01-28 1986-08-05 International Business Machines Corporation Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making
US4642889A (en) 1985-04-29 1987-02-17 Amp Incorporated Compliant interconnection and method therefor
US5917707A (en) 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
US5476211A (en) 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
US4924353A (en) 1985-12-20 1990-05-08 Hughes Aircraft Company Connector system for coupling to an integrated circuit chip
US4716049A (en) 1985-12-20 1987-12-29 Hughes Aircraft Company Compressive pedestal for microminiature connections
JPS62158338A (ja) 1985-12-28 1987-07-14 Tanaka Denshi Kogyo Kk 半導体装置
US4793814A (en) 1986-07-21 1988-12-27 Rogers Corporation Electrical circuit board interconnect
US4695870A (en) 1986-03-27 1987-09-22 Hughes Aircraft Company Inverted chip carrier
JPS62226307A (ja) 1986-03-28 1987-10-05 Toshiba Corp ロボツト装置
US4771930A (en) 1986-06-30 1988-09-20 Kulicke And Soffa Industries Inc. Apparatus for supplying uniform tail lengths
JPS6397941A (ja) 1986-10-14 1988-04-28 Fuji Photo Film Co Ltd 感光材料
US4955523A (en) 1986-12-17 1990-09-11 Raychem Corporation Interconnection of electronic components
DE3703694A1 (de) * 1987-02-06 1988-08-18 Dynapert Delvotec Gmbh Ball-bondverfahren und vorrichtung zur durchfuehrung derselben
US5138438A (en) 1987-06-24 1992-08-11 Akita Electronics Co. Ltd. Lead connections means for stacked tab packaged IC chips
JP2642359B2 (ja) 1987-09-11 1997-08-20 株式会社日立製作所 半導体装置
KR970003915B1 (ko) 1987-06-24 1997-03-22 미다 가쓰시게 반도체 기억장치 및 그것을 사용한 반도체 메모리 모듈
US4804132A (en) 1987-08-28 1989-02-14 Difrancesco Louis Method for cold bonding
US4845354A (en) 1988-03-08 1989-07-04 International Business Machines Corporation Process control for laser wire bonding
JPH01313969A (ja) 1988-06-13 1989-12-19 Hitachi Ltd 半導体装置
US4998885A (en) 1989-10-27 1991-03-12 International Business Machines Corporation Elastomeric area array interposer
US5077598A (en) 1989-11-08 1991-12-31 Hewlett-Packard Company Strain relief flip-chip integrated circuit assembly with test fixturing
US5095187A (en) 1989-12-20 1992-03-10 Raychem Corporation Weakening wire supplied through a wire bonder
CA2034703A1 (en) 1990-01-23 1991-07-24 Masanori Nishiguchi Substrate for packaging a semiconductor device
AU637874B2 (en) 1990-01-23 1993-06-10 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
US5948533A (en) 1990-02-09 1999-09-07 Ormet Corporation Vertically interconnected electronic assemblies and compositions useful therefor
US5376403A (en) 1990-02-09 1994-12-27 Capote; Miguel A. Electrically conductive compositions and methods for the preparation and use thereof
US5083697A (en) 1990-02-14 1992-01-28 Difrancesco Louis Particle-enhanced joining of metal surfaces
US4975079A (en) 1990-02-23 1990-12-04 International Business Machines Corp. Connector assembly for chip testing
US4999472A (en) 1990-03-12 1991-03-12 Neinast James E Electric arc system for ablating a surface coating
US5241456A (en) 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5067382A (en) 1990-11-02 1991-11-26 Cray Computer Corporation Method and apparatus for notching a lead wire attached to an IC chip to facilitate severing the wire
KR940001149B1 (ko) 1991-04-16 1994-02-14 삼성전자 주식회사 반도체 장치의 칩 본딩 방법
JPH04346436A (ja) 1991-05-24 1992-12-02 Fujitsu Ltd バンプ製造方法とバンプ製造装置
US5316788A (en) 1991-07-26 1994-05-31 International Business Machines Corporation Applying solder to high density substrates
US5203075A (en) 1991-08-12 1993-04-20 Inernational Business Machines Method of bonding flexible circuit to cicuitized substrate to provide electrical connection therebetween using different solders
US5133495A (en) 1991-08-12 1992-07-28 International Business Machines Corporation Method of bonding flexible circuit to circuitized substrate to provide electrical connection therebetween
WO1993004375A1 (en) 1991-08-23 1993-03-04 Nchip, Inc. Burn-in technologies for unpackaged integrated circuits
US5220489A (en) 1991-10-11 1993-06-15 Motorola, Inc. Multicomponent integrated circuit package
US5238173A (en) * 1991-12-04 1993-08-24 Kaijo Corporation Wire bonding misattachment detection apparatus and that detection method in a wire bonder
JP2931936B2 (ja) 1992-01-17 1999-08-09 株式会社日立製作所 半導体装置用リードフレームの製造方法及び半導体装置用リードフレーム並びに樹脂封止型半導体装置
US5831836A (en) 1992-01-30 1998-11-03 Lsi Logic Power plane for semiconductor device
US5222014A (en) 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5438224A (en) 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
US5494667A (en) 1992-06-04 1996-02-27 Kabushiki Kaisha Hayahibara Topically applied hair restorer containing pine extract
US6054756A (en) 1992-07-24 2000-04-25 Tessera, Inc. Connection components with frangible leads and bus
US5977618A (en) 1992-07-24 1999-11-02 Tessera, Inc. Semiconductor connection components and methods with releasable lead support
WO1994003036A1 (en) 1992-07-24 1994-02-03 Tessera, Inc. Semiconductor connection components and methods with releasable lead support
US20050062492A1 (en) 2001-08-03 2005-03-24 Beaman Brian Samuel High density integrated circuit apparatus, test probe and methods of use thereof
US5371654A (en) 1992-10-19 1994-12-06 International Business Machines Corporation Three dimensional high performance interconnection package
US6295729B1 (en) 1992-10-19 2001-10-02 International Business Machines Corporation Angled flying lead wire bonding process
JP2716336B2 (ja) 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
JPH06268101A (ja) 1993-03-17 1994-09-22 Hitachi Ltd 半導体装置及びその製造方法、電子装置、リ−ドフレ−ム並びに実装基板
US5340771A (en) 1993-03-18 1994-08-23 Lsi Logic Corporation Techniques for providing high I/O count connections to semiconductor dies
US7368924B2 (en) 1993-04-30 2008-05-06 International Business Machines Corporation Probe structure having a plurality of discrete insulated probe tips projecting from a support surface, apparatus for use thereof and methods of fabrication thereof
US5811982A (en) 1995-11-27 1998-09-22 International Business Machines Corporation High density cantilevered probe for electronic devices
US20030048108A1 (en) 1993-04-30 2003-03-13 Beaman Brian Samuel Structural design and processes to control probe position accuracy in a wafer test probe assembly
JP2981385B2 (ja) 1993-09-06 1999-11-22 シャープ株式会社 チップ部品型ｌｅｄの構造及びその製造方法
US5346118A (en) 1993-09-28 1994-09-13 At&T Bell Laboratories Surface mount solder assembly of leadless integrated circuit packages to substrates
US6835898B2 (en) 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US5455390A (en) 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
EP0751561A4 (en) 1994-03-18 1997-05-07 Hitachi Chemical Co Ltd PROCESS FOR MANUFACTURING SEMICONDUCTOR PACKAGES AND SEMICONDUCTOR PACKAGES
US5802699A (en) 1994-06-07 1998-09-08 Tessera, Inc. Methods of assembling microelectronic assembly with socket for engaging bump leads
US5615824A (en) 1994-06-07 1997-04-01 Tessera, Inc. Soldering with resilient contacts
JPH07335783A (ja) 1994-06-13 1995-12-22 Fujitsu Ltd 半導体装置及び半導体装置ユニット
US5468995A (en) 1994-07-05 1995-11-21 Motorola, Inc. Semiconductor device having compliant columnar electrical connections
US5688716A (en) 1994-07-07 1997-11-18 Tessera, Inc. Fan-out semiconductor chip assembly
US6177636B1 (en) 1994-12-29 2001-01-23 Tessera, Inc. Connection components with posts
US6117694A (en) 1994-07-07 2000-09-12 Tessera, Inc. Flexible lead structures and methods of making same
US5518964A (en) 1994-07-07 1996-05-21 Tessera, Inc. Microelectronic mounting with multiple lead deformation and bonding
US6828668B2 (en) 1994-07-07 2004-12-07 Tessera, Inc. Flexible lead structures and methods of making same
US5989936A (en) 1994-07-07 1999-11-23 Tessera, Inc. Microelectronic assembly fabrication with terminal formation from a conductive layer
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5659952A (en) 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
US5541567A (en) 1994-10-17 1996-07-30 International Business Machines Corporation Coaxial vias in an electronic substrate
US5495667A (en) 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects
US5736074A (en) 1995-06-30 1998-04-07 Micro Fab Technologies, Inc. Manufacture of coated spheres
US5971253A (en) 1995-07-31 1999-10-26 Tessera, Inc. Microelectronic component mounting with deformable shell terminals
US5872051A (en) 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US5810609A (en) 1995-08-28 1998-09-22 Tessera, Inc. Socket for engaging bump leads on a microelectronic device and methods therefor
US5766987A (en) 1995-09-22 1998-06-16 Tessera, Inc. Microelectronic encapsulation methods and equipment
US6211572B1 (en) 1995-10-31 2001-04-03 Tessera, Inc. Semiconductor chip package with fan-in leads
JPH09134934A (ja) 1995-11-07 1997-05-20 Sumitomo Metal Ind Ltd 半導体パッケージ及び半導体装置
JP3332308B2 (ja) 1995-11-07 2002-10-07 新光電気工業株式会社 半導体装置及びその製造方法
US5718361A (en) 1995-11-21 1998-02-17 International Business Machines Corporation Apparatus and method for forming mold for metallic material
US5731709A (en) 1996-01-26 1998-03-24 Motorola, Inc. Method for testing a ball grid array semiconductor device and a device for such testing
US5994152A (en) 1996-02-21 1999-11-30 Formfactor, Inc. Fabricating interconnects and tips using sacrificial substrates
JP3146345B2 (ja) 1996-03-11 2001-03-12 アムコー テクノロジー コリア インコーポレーティド バンプチップスケール半導体パッケージのバンプ形成方法
US6000126A (en) 1996-03-29 1999-12-14 General Dynamics Information Systems, Inc. Method and apparatus for connecting area grid arrays to printed wire board
US6821821B2 (en) 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
DE19618227A1 (de) 1996-05-07 1997-11-13 Herbert Streckfus Gmbh Verfahren und Vorrichtung zum Verlöten von elektronischen Bauelementen auf einer Leiterplatte
KR100186333B1 (ko) 1996-06-20 1999-03-20 문정환 칩 사이즈 반도체 패키지 및 그 제조방법
JPH1012769A (ja) 1996-06-24 1998-01-16 Ricoh Co Ltd 半導体装置およびその製造方法
JPH10135220A (ja) 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
JPH10135221A (ja) 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
US6492719B2 (en) 1999-07-30 2002-12-10 Hitachi, Ltd. Semiconductor device
US5976913A (en) 1996-12-12 1999-11-02 Tessera, Inc. Microelectronic mounting with multiple lead deformation using restraining straps
US6121676A (en) 1996-12-13 2000-09-19 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6225688B1 (en) 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6054337A (en) 1996-12-13 2000-04-25 Tessera, Inc. Method of making a compliant multichip package
US6133072A (en) 1996-12-13 2000-10-17 Tessera, Inc. Microelectronic connector with planar elastomer sockets
JP3400279B2 (ja) 1997-01-13 2003-04-28 株式会社新川 バンプ形成方法
US5898991A (en) 1997-01-16 1999-05-04 International Business Machines Corporation Methods of fabrication of coaxial vias and magnetic devices
US5839191A (en) 1997-01-24 1998-11-24 Unisys Corporation Vibrating template method of placing solder balls on the I/O pads of an integrated circuit package
JPH1118364A (ja) 1997-06-27 1999-01-22 Matsushita Electric Ind Co Ltd キャプスタンモータ
WO1999009595A1 (en) 1997-08-19 1999-02-25 Hitachi, Ltd. Multichip module structure and method for manufacturing the same
CA2213590C (en) 1997-08-21 2006-11-07 Keith C. Carroll Flexible circuit connector and method of making same
JP3859318B2 (ja) 1997-08-29 2006-12-20 シチズン電子株式会社 電子回路のパッケージ方法
US6525414B2 (en) 1997-09-16 2003-02-25 Matsushita Electric Industrial Co., Ltd. Semiconductor device including a wiring board and semiconductor elements mounted thereon
JP3937265B2 (ja) 1997-09-29 2007-06-27 エルピーダメモリ株式会社 半導体装置
JP3262531B2 (ja) 1997-10-02 2002-03-04 インターナショナル・ビジネス・マシーンズ・コーポレーション 曲げられたフライング・リード・ワイヤ・ボンデイング・プロセス
JP2978861B2 (ja) 1997-10-28 1999-11-15 九州日本電気株式会社 モールドｂｇａ型半導体装置及びその製造方法
US6038136A (en) 1997-10-29 2000-03-14 Hestia Technologies, Inc. Chip package with molded underfill
JP3393800B2 (ja) 1997-11-05 2003-04-07 新光電気工業株式会社 半導体装置の製造方法
JPH11219984A (ja) 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
US6222136B1 (en) 1997-11-12 2001-04-24 International Business Machines Corporation Printed circuit board with continuous connective bumps
US6002168A (en) 1997-11-25 1999-12-14 Tessera, Inc. Microelectronic component with rigid interposer
US6038133A (en) 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
JPH11163022A (ja) 1997-11-28 1999-06-18 Sony Corp 半導体装置、その製造方法及び電子機器
US6124546A (en) 1997-12-03 2000-09-26 Advanced Micro Devices, Inc. Integrated circuit chip package and method of making the same
US6260264B1 (en) 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
US6052287A (en) 1997-12-09 2000-04-18 Sandia Corporation Silicon ball grid array chip carrier
US5973391A (en) 1997-12-11 1999-10-26 Read-Rite Corporation Interposer with embedded circuitry and method for using the same to package microelectronic units
JPH11220082A (ja) 1998-02-03 1999-08-10 Oki Electric Ind Co Ltd 半導体装置
JP3536650B2 (ja) 1998-02-27 2004-06-14 富士ゼロックス株式会社 バンプ形成方法および装置
JPH11260856A (ja) 1998-03-11 1999-09-24 Matsushita Electron Corp 半導体装置及びその製造方法並びに半導体装置の実装構造
KR100260997B1 (ko) 1998-04-08 2000-07-01 마이클 디. 오브라이언 반도체패키지
US6329224B1 (en) 1998-04-28 2001-12-11 Tessera, Inc. Encapsulation of microelectronic assemblies
US6180881B1 (en) 1998-05-05 2001-01-30 Harlan Ruben Isaak Chip stack and method of making same
JPH11330134A (ja) 1998-05-12 1999-11-30 Hitachi Ltd ワイヤボンディング方法およびその装置並びに半導体装置
KR100266693B1 (ko) 1998-05-30 2000-09-15 김영환 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법
KR100265563B1 (ko) 1998-06-29 2000-09-15 김영환 볼 그리드 어레이 패키지 및 그의 제조 방법
US6414391B1 (en) 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
US6164523A (en) 1998-07-01 2000-12-26 Semiconductor Components Industries, Llc Electronic component and method of manufacture
US5854507A (en) 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly
US6399426B1 (en) 1998-07-21 2002-06-04 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US6515355B1 (en) 1998-09-02 2003-02-04 Micron Technology, Inc. Passivation layer for packaged integrated circuits
JP2000091383A (ja) 1998-09-07 2000-03-31 Ngk Spark Plug Co Ltd 配線基板
US6194250B1 (en) 1998-09-14 2001-02-27 Motorola, Inc. Low-profile microelectronic package
US6158647A (en) 1998-09-29 2000-12-12 Micron Technology, Inc. Concave face wire bond capillary
US6684007B2 (en) 1998-10-09 2004-01-27 Fujitsu Limited Optical coupling structures and the fabrication processes
JP2000311915A (ja) 1998-10-14 2000-11-07 Texas Instr Inc <Ti> 半導体デバイス及びボンディング方法
JP3407275B2 (ja) 1998-10-28 2003-05-19 インターナショナル・ビジネス・マシーンズ・コーポレーション バンプ及びその形成方法
US6332270B2 (en) 1998-11-23 2001-12-25 International Business Machines Corporation Method of making high density integral test probe
KR100502222B1 (ko) 1999-01-29 2005-07-18 마츠시타 덴끼 산교 가부시키가이샤 전자부품의 실장방법 및 그 장치
US6206273B1 (en) 1999-02-17 2001-03-27 International Business Machines Corporation Structures and processes to create a desired probetip contact geometry on a wafer test probe
KR100319609B1 (ko) 1999-03-09 2002-01-05 김영환 와이어 어래이드 칩 사이즈 패키지 및 그 제조방법
US6177729B1 (en) 1999-04-03 2001-01-23 International Business Machines Corporation Rolling ball connector
US6211574B1 (en) 1999-04-16 2001-04-03 Advanced Semiconductor Engineering Inc. Semiconductor package with wire protection and method therefor
US6258625B1 (en) 1999-05-18 2001-07-10 International Business Machines Corporation Method of interconnecting electronic components using a plurality of conductive studs
US6376769B1 (en) 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
JP3398721B2 (ja) 1999-05-20 2003-04-21 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ及びその製造方法
US6228687B1 (en) 1999-06-28 2001-05-08 Micron Technology, Inc. Wafer-level package and methods of fabricating
TW417839U (en) 1999-07-30 2001-01-01 Shen Ming Tung Stacked memory module structure and multi-layered stacked memory module structure using the same
JP5333337B2 (ja) 1999-08-12 2013-11-06 富士通セミコンダクター株式会社 半導体装置の製造方法
US6168965B1 (en) 1999-08-12 2001-01-02 Tower Semiconductor Ltd. Method for making backside illuminated image sensor
JP4526651B2 (ja) 1999-08-12 2010-08-18 富士通セミコンダクター株式会社 半導体装置
CN101232779B (zh) 1999-09-02 2013-03-27 揖斐电株式会社 印刷布线板
US6867499B1 (en) 1999-09-30 2005-03-15 Skyworks Solutions, Inc. Semiconductor packaging
JP3513444B2 (ja) 1999-10-20 2004-03-31 株式会社新川 ピン状ワイヤ等の形成方法
JP2001127246A (ja) 1999-10-29 2001-05-11 Fujitsu Ltd 半導体装置
US6362525B1 (en) 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
JP3619410B2 (ja) 1999-11-18 2005-02-09 株式会社ルネサステクノロジ バンプ形成方法およびそのシステム
JP3798597B2 (ja) 1999-11-30 2006-07-19 富士通株式会社 半導体装置
JP3566156B2 (ja) 1999-12-02 2004-09-15 株式会社新川 ピン状ワイヤ等の形成方法
KR100426494B1 (ko) 1999-12-20 2004-04-13 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이것의 제조방법
US6790757B1 (en) 1999-12-20 2004-09-14 Agere Systems Inc. Wire bonding method for copper interconnects in semiconductor devices
KR20010061849A (ko) 1999-12-29 2001-07-07 박종섭 웨이퍼 레벨 패키지
JP2001196407A (ja) 2000-01-14 2001-07-19 Seiko Instruments Inc 半導体装置および半導体装置の形成方法
US6710454B1 (en) 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
JP2001339011A (ja) 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
JP3980807B2 (ja) 2000-03-27 2007-09-26 株式会社東芝 半導体装置及び半導体モジュール
JP2001274196A (ja) 2000-03-28 2001-10-05 Rohm Co Ltd 半導体装置
KR100583491B1 (ko) 2000-04-07 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조방법
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6531335B1 (en) 2000-04-28 2003-03-11 Micron Technology, Inc. Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods
JP2001326236A (ja) 2000-05-12 2001-11-22 Nec Kyushu Ltd 半導体装置の製造方法
JP2001326304A (ja) 2000-05-15 2001-11-22 Toshiba Corp 半導体装置及びその製造方法
US6522018B1 (en) 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US6647310B1 (en) 2000-05-30 2003-11-11 Advanced Micro Devices, Inc. Temperature control of an integrated circuit
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6560117B2 (en) 2000-06-28 2003-05-06 Micron Technology, Inc. Packaged microelectronic die assemblies and methods of manufacture
US6476583B2 (en) 2000-07-21 2002-11-05 Jomahip, Llc Automatic battery charging system for a battery back-up DC power supply
SE517086C2 (sv) 2000-08-08 2002-04-09 Ericsson Telefon Ab L M Förfarande för säkring av lodkulor och eventuella komponenter, vilka är fästa på en och samma sida av ett substrat
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6462575B1 (en) 2000-08-28 2002-10-08 Micron Technology, Inc. Method and system for wafer level testing and burning-in semiconductor components
JP3874062B2 (ja) 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
US6507104B2 (en) 2000-09-07 2003-01-14 Siliconware Precision Industries Co., Ltd. Semiconductor package with embedded heat-dissipating device
US7009297B1 (en) 2000-10-13 2006-03-07 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal particle
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
JP4505983B2 (ja) 2000-12-01 2010-07-21 日本電気株式会社 半導体装置
JP3798620B2 (ja) 2000-12-04 2006-07-19 富士通株式会社 半導体装置の製造方法
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
KR100393102B1 (ko) 2000-12-29 2003-07-31 앰코 테크놀로지 코리아 주식회사 스택형 반도체패키지
AUPR244801A0 (en) 2001-01-10 2001-02-01 Silverbrook Research Pty Ltd A method and apparatus (WSM01)
US6388322B1 (en) 2001-01-17 2002-05-14 Aralight, Inc. Article comprising a mechanically compliant bump
US6653170B1 (en) 2001-02-06 2003-11-25 Charles W. C. Lin Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit
JP2002280414A (ja) 2001-03-22 2002-09-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2002289769A (ja) 2001-03-26 2002-10-04 Matsushita Electric Ind Co Ltd 積層型半導体装置およびその製造方法
SG108245A1 (en) 2001-03-30 2005-01-28 Micron Technology Inc Ball grid array interposer, packages and methods
US7115986B2 (en) 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
US6825552B2 (en) 2001-05-09 2004-11-30 Tessera, Inc. Connection components with anisotropic conductive material interconnection
TW544826B (en) 2001-05-18 2003-08-01 Nec Electronics Corp Flip-chip-type semiconductor device and manufacturing method thereof
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
US6754407B2 (en) 2001-06-26 2004-06-22 Intel Corporation Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board
US20030006494A1 (en) 2001-07-03 2003-01-09 Lee Sang Ho Thin profile stackable semiconductor package and method for manufacturing
US6451626B1 (en) 2001-07-27 2002-09-17 Charles W.C. Lin Three-dimensional stacked semiconductor package
US6765287B1 (en) 2001-07-27 2004-07-20 Charles W. C. Lin Three-dimensional stacked semiconductor package
JP4023159B2 (ja) 2001-07-31 2007-12-19 ソニー株式会社 半導体装置の製造方法及び積層半導体装置の製造方法
US6550666B2 (en) 2001-08-21 2003-04-22 Advanpack Solutions Pte Ltd Method for forming a flip chip on leadframe semiconductor package
WO2003019654A1 (en) 2001-08-22 2003-03-06 Tessera, Inc. Stacked chip assembly with stiffening layer
US7176506B2 (en) 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
US20030057544A1 (en) 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol
WO2003032370A2 (en) 2001-10-09 2003-04-17 Tessera, Inc. Stacked packages
US6977440B2 (en) 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
JP2003122611A (ja) 2001-10-11 2003-04-25 Oki Electric Ind Co Ltd データ提供方法及びサーバ装置
JP4257771B2 (ja) 2001-10-16 2009-04-22 シンジーテック株式会社 導電性ブレード
US20030094666A1 (en) 2001-11-16 2003-05-22 R-Tec Corporation Interposer
JP3875077B2 (ja) 2001-11-16 2007-01-31 富士通株式会社 電子デバイス及びデバイス接続方法
JP2003174124A (ja) 2001-12-04 2003-06-20 Sainekkusu:Kk 半導体装置の外部電極形成方法
JP3507059B2 (ja) 2002-06-27 2004-03-15 沖電気工業株式会社 積層マルチチップパッケージ
JP2003197669A (ja) 2001-12-28 2003-07-11 Seiko Epson Corp ボンディング方法及びボンディング装置
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
JP3935370B2 (ja) 2002-02-19 2007-06-20 セイコーエプソン株式会社 バンプ付き半導体素子の製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
SG115456A1 (en) 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
US6653723B2 (en) 2002-03-09 2003-11-25 Fujitsu Limited System for providing an open-cavity low profile encapsulated semiconductor package
KR100452819B1 (ko) 2002-03-18 2004-10-15 삼성전기주식회사 칩 패키지 및 그 제조방법
US6979230B2 (en) 2002-03-20 2005-12-27 Gabe Cherian Light socket
US7323767B2 (en) 2002-04-25 2008-01-29 Micron Technology, Inc. Standoffs for centralizing internals in packaging process
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US7078822B2 (en) 2002-06-25 2006-07-18 Intel Corporation Microelectronic device interconnects
JP2004047702A (ja) 2002-07-11 2004-02-12 Toshiba Corp 半導体装置積層モジュール
US6756252B2 (en) 2002-07-17 2004-06-29 Texas Instrument Incorporated Multilayer laser trim interconnect method
US6987032B1 (en) 2002-07-19 2006-01-17 Asat Ltd. Ball grid array package and process for manufacturing same
TW549592U (en) 2002-08-16 2003-08-21 Via Tech Inc Integrated circuit package with a balanced-part structure
AU2003265417A1 (en) 2002-08-16 2004-03-03 Tessera, Inc. Microelectronic packages with self-aligning features
US6740546B2 (en) 2002-08-21 2004-05-25 Micron Technology, Inc. Packaged microelectronic devices and methods for assembling microelectronic devices
US6964881B2 (en) 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
JP3765778B2 (ja) 2002-08-29 2006-04-12 ローム株式会社 ワイヤボンディング用キャピラリ及びこれを用いたワイヤボンディング方法
JP2004095799A (ja) 2002-08-30 2004-03-25 Toshiba Corp 半導体装置およびその製造方法
US7294928B2 (en) 2002-09-06 2007-11-13 Tessera, Inc. Components, methods and assemblies for stacked packages
US7246431B2 (en) 2002-09-06 2007-07-24 Tessera, Inc. Methods of making microelectronic packages including folded substrates
US7071547B2 (en) 2002-09-11 2006-07-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
US7229906B2 (en) 2002-09-19 2007-06-12 Kulicke And Soffa Industries, Inc. Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine
KR20050071524A (ko) 2002-09-30 2005-07-07 어드밴스드 인터커넥트 테크놀로지스 리미티드 블럭 몰드 조립체용 열 강화 패키지
US7045884B2 (en) 2002-10-04 2006-05-16 International Rectifier Corporation Semiconductor device package
EP1556895A4 (en) 2002-10-08 2009-12-30 Chippac Inc SEMICONDUCTOR STACKED MULTIPLE CAPSULATION MODULE WITH INVERTED SECOND CAPACITY
US6989122B1 (en) 2002-10-17 2006-01-24 National Semiconductor Corporation Techniques for manufacturing flash-free contacts on a semiconductor package
TW567601B (en) 2002-10-18 2003-12-21 Siliconware Precision Industries Co Ltd Module device of stacked semiconductor package and method for fabricating the same
TWI221664B (en) 2002-11-07 2004-10-01 Via Tech Inc Structure of chip package and process thereof
JP2004172157A (ja) 2002-11-15 2004-06-17 Shinko Electric Ind Co Ltd 半導体パッケージおよびパッケージスタック半導体装置
JP2004172477A (ja) 2002-11-21 2004-06-17 Kaijo Corp ワイヤループ形状、そのワイヤループ形状を備えた半導体装置、ワイヤボンディング方法及び半導体製造装置
JP4464041B2 (ja) 2002-12-13 2010-05-19 キヤノン株式会社 柱状構造体、柱状構造体を有する電極、及びこれらの作製方法
KR100621991B1 (ko) 2003-01-03 2006-09-13 삼성전자주식회사 칩 스케일 적층 패키지
JP2004221257A (ja) 2003-01-14 2004-08-05 Seiko Epson Corp ワイヤボンディング方法及びワイヤボンディング装置
WO2004077525A2 (en) 2003-02-25 2004-09-10 Tessera, Inc. Ball grid array with bumps
TW583757B (en) 2003-02-26 2004-04-11 Advanced Semiconductor Eng A structure of a flip-chip package and a process thereof
US20040217471A1 (en) 2003-02-27 2004-11-04 Tessera, Inc. Component and assemblies with ends offset downwardly
JP3885747B2 (ja) 2003-03-13 2007-02-28 株式会社デンソー ワイヤボンディング方法
JP2004343030A (ja) 2003-03-31 2004-12-02 North:Kk 配線回路基板とその製造方法とその配線回路基板を備えた回路モジュール
JP2004319892A (ja) 2003-04-18 2004-11-11 Renesas Technology Corp 半導体装置の製造方法
JP4199588B2 (ja) 2003-04-25 2008-12-17 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路基板の製造方法、及び、この配線回路基板を用いた半導体集積回路装置の製造方法
DE10320646A1 (de) 2003-05-07 2004-09-16 Infineon Technologies Ag Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben
JP4145730B2 (ja) 2003-06-17 2008-09-03 松下電器産業株式会社 半導体内蔵モジュール
KR100604821B1 (ko) 2003-06-30 2006-07-26 삼성전자주식회사 적층형 볼 그리드 어레이 패키지 및 그 제조방법
US20040262728A1 (en) 2003-06-30 2004-12-30 Sterrett Terry L. Modular device assemblies
JP2005033141A (ja) 2003-07-11 2005-02-03 Sony Corp 半導体装置及びその製造方法、疑似ウェーハ及びその製造方法、並びに半導体装置の実装構造
US7227095B2 (en) 2003-08-06 2007-06-05 Micron Technology, Inc. Wire bonders and methods of wire-bonding
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
KR100546374B1 (ko) 2003-08-28 2006-01-26 삼성전자주식회사 센터 패드를 갖는 적층형 반도체 패키지 및 그 제조방법
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
US7061096B2 (en) 2003-09-24 2006-06-13 Silicon Pipe, Inc. Multi-surface IC packaging structures and methods for their manufacture
US20050082654A1 (en) 2003-09-26 2005-04-21 Tessera, Inc. Structure and self-locating method of making capped chips
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
JP4272968B2 (ja) 2003-10-16 2009-06-03 エルピーダメモリ株式会社 半導体装置および半導体チップ制御方法
JP4167965B2 (ja) 2003-11-07 2008-10-22 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路用部材の製造方法
KR100564585B1 (ko) 2003-11-13 2006-03-28 삼성전자주식회사 이중 스택된 ｂｇａ 패키지 및 다중 스택된 ｂｇａ 패키지
TWI227555B (en) 2003-11-17 2005-02-01 Advanced Semiconductor Eng Structure of chip package and the process thereof
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP2005183923A (ja) 2003-11-28 2005-07-07 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US7345361B2 (en) 2003-12-04 2008-03-18 Intel Corporation Stackable integrated circuit packaging
JP2005175019A (ja) 2003-12-08 2005-06-30 Sharp Corp 半導体装置及び積層型半導体装置
WO2005059967A2 (en) 2003-12-17 2005-06-30 Chippac, Inc. Multiple chip package module having inverted package stacked over die
DE10360708B4 (de) 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
JP4334996B2 (ja) 2003-12-24 2009-09-30 株式会社フジクラ 多層配線板用基材、両面配線板およびそれらの製造方法
US7495644B2 (en) 2003-12-26 2009-02-24 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing display device
US6900530B1 (en) 2003-12-29 2005-05-31 Ramtek Technology, Inc. Stacked IC
US6917098B1 (en) 2003-12-29 2005-07-12 Texas Instruments Incorporated Three-level leadframe for no-lead packages
US7176043B2 (en) 2003-12-30 2007-02-13 Tessera, Inc. Microelectronic packages and methods therefor
US7709968B2 (en) 2003-12-30 2010-05-04 Tessera, Inc. Micro pin grid array with pin motion isolation
US8207604B2 (en) 2003-12-30 2012-06-26 Tessera, Inc. Microelectronic package comprising offset conductive posts on compliant layer
JP2005203497A (ja) 2004-01-14 2005-07-28 Toshiba Corp 半導体装置およびその製造方法
US20050173807A1 (en) 2004-02-05 2005-08-11 Jianbai Zhu High density vertically stacked semiconductor device
US8399972B2 (en) 2004-03-04 2013-03-19 Skyworks Solutions, Inc. Overmolded semiconductor package with a wirebond cage for EMI shielding
US7095105B2 (en) 2004-03-23 2006-08-22 Texas Instruments Incorporated Vertically stacked semiconductor device
JP4484035B2 (ja) 2004-04-06 2010-06-16 セイコーエプソン株式会社 半導体装置の製造方法
US8092734B2 (en) 2004-05-13 2012-01-10 Aptina Imaging Corporation Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers
US7629695B2 (en) 2004-05-20 2009-12-08 Kabushiki Kaisha Toshiba Stacked electronic component and manufacturing method thereof
US6962864B1 (en) 2004-05-26 2005-11-08 National Chung Cheng University Wire-bonding method for chips with copper interconnects by introducing a thin layer
US7233057B2 (en) 2004-05-28 2007-06-19 Nokia Corporation Integrated circuit package with optimized mold shape
TWI255022B (en) 2004-05-31 2006-05-11 Via Tech Inc Circuit carrier and manufacturing process thereof
US7453157B2 (en) 2004-06-25 2008-11-18 Tessera, Inc. Microelectronic packages and methods therefor
TWI250596B (en) 2004-07-23 2006-03-01 Ind Tech Res Inst Wafer-level chip scale packaging method
JP4385329B2 (ja) 2004-10-08 2009-12-16 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
US8646675B2 (en) 2004-11-02 2014-02-11 Hid Global Gmbh Laying apparatus, contact-making apparatus, movement system, laying and contact-making unit, production system, method for production and a transponder unit
US8525314B2 (en) 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements
US7268421B1 (en) 2004-11-10 2007-09-11 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond
US7750483B1 (en) 2004-11-10 2010-07-06 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal
KR100674926B1 (ko) 2004-12-08 2007-01-26 삼성전자주식회사 메모리 카드 및 그 제조 방법
JP4504798B2 (ja) 2004-12-16 2010-07-14 パナソニック株式会社 多段構成半導体モジュール
JP2006186086A (ja) 2004-12-27 2006-07-13 Itoo:Kk プリント基板のはんだ付け方法およびブリッジ防止用ガイド板
DE102005006333B4 (de) 2005-02-10 2007-10-18 Infineon Technologies Ag Halbleiterbauteil mit mehreren Bondanschlüssen und gebondeten Kontaktelementen unterschiedlicher Metallzusammensetzung und Verfahren zur Herstellung desselben
DE102005006995B4 (de) 2005-02-15 2008-01-24 Infineon Technologies Ag Halbleiterbauteil mit Kunstoffgehäuse und Außenanschlüssen sowie Verfahren zur Herstellung desselben
KR100630741B1 (ko) 2005-03-04 2006-10-02 삼성전자주식회사 다중 몰딩에 의한 적층형 반도체 패키지 및 그 제조방법
US7939934B2 (en) 2005-03-16 2011-05-10 Tessera, Inc. Microelectronic packages and methods therefor
US7371676B2 (en) 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
TWI284394B (en) 2005-05-12 2007-07-21 Advanced Semiconductor Eng Lid used in package structure and the package structure of having the same
JP2006324553A (ja) 2005-05-20 2006-11-30 Renesas Technology Corp 半導体装置及びその製造方法
US7216794B2 (en) 2005-06-09 2007-05-15 Texas Instruments Incorporated Bond capillary design for ribbon wire bonding
JP4322844B2 (ja) 2005-06-10 2009-09-02 シャープ株式会社 半導体装置および積層型半導体装置
US20100078795A1 (en) 2005-07-01 2010-04-01 Koninklijke Philips Electronics, N.V. Electronic device
US7476608B2 (en) 2005-07-14 2009-01-13 Hewlett-Packard Development Company, L.P. Electrically connecting substrate with electrical device
TWI263313B (en) 2005-08-15 2006-10-01 Phoenix Prec Technology Corp Stack structure of semiconductor component embedded in supporting board
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
SG130066A1 (en) 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
JP5522561B2 (ja) 2005-08-31 2014-06-18 マイクロン テクノロジー， インク． マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法
US7675152B2 (en) 2005-09-01 2010-03-09 Texas Instruments Incorporated Package-on-package semiconductor assembly
US7504716B2 (en) 2005-10-26 2009-03-17 Texas Instruments Incorporated Structure and method of molded QFN device suitable for miniaturization, multiple rows and stacking
JP2007123595A (ja) 2005-10-28 2007-05-17 Nec Corp 半導体装置及びその実装構造
CN101356633B (zh) 2005-11-01 2011-03-23 Nxp股份有限公司 半导体裸片的封装方法以及通过该方法形成的裸片封装
JP4530975B2 (ja) 2005-11-14 2010-08-25 株式会社新川 ワイヤボンディング方法
JP2007142042A (ja) 2005-11-16 2007-06-07 Sharp Corp 半導体パッケージとその製造方法，半導体モジュール，および電子機器
US7344917B2 (en) 2005-11-30 2008-03-18 Freescale Semiconductor, Inc. Method for packaging a semiconductor device
US7307348B2 (en) 2005-12-07 2007-12-11 Micron Technology, Inc. Semiconductor components having through wire interconnects (TWI)
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
JP4530984B2 (ja) * 2005-12-28 2010-08-25 株式会社新川 ワイヤボンディング装置、ボンディング制御プログラム及びボンディング方法
US20070190747A1 (en) 2006-01-23 2007-08-16 Tessera Technologies Hungary Kft. Wafer level packaging to lidded chips
JP2007208159A (ja) 2006-02-06 2007-08-16 Hitachi Ltd 半導体装置
SG135074A1 (en) 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
JP2007234845A (ja) 2006-03-01 2007-09-13 Nec Corp 半導体装置
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
US7759782B2 (en) 2006-04-07 2010-07-20 Tessera, Inc. Substrate for a microelectronic package and method of fabricating thereof
JP5598787B2 (ja) 2006-04-17 2014-10-01 マイクロンメモリジャパン株式会社 積層型半導体装置の製造方法
US7242081B1 (en) 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
US7659612B2 (en) 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
US7780064B2 (en) 2006-06-02 2010-08-24 Asm Technology Singapore Pte Ltd Wire bonding method for forming low-loop profiles
JP4961848B2 (ja) 2006-06-12 2012-06-27 日本電気株式会社 金属ポストを有する配線基板、半導体装置及び半導体装置モジュールの製造方法
US7967062B2 (en) 2006-06-16 2011-06-28 International Business Machines Corporation Thermally conductive composite interface, cooled electronic assemblies employing the same, and methods of fabrication thereof
US20070290325A1 (en) 2006-06-16 2007-12-20 Lite-On Semiconductor Corporation Surface mounting structure and packaging method thereof
US8084867B2 (en) 2006-06-29 2011-12-27 Intel Corporation Apparatus, system, and method for wireless connection in integrated circuit packages
KR100792352B1 (ko) 2006-07-06 2008-01-08 삼성전기주식회사 패키지 온 패키지의 바텀기판 및 그 제조방법
KR100800478B1 (ko) 2006-07-18 2008-02-04 삼성전자주식회사 적층형 반도체 패키지 및 그의 제조방법
US20080023805A1 (en) 2006-07-26 2008-01-31 Texas Instruments Incorporated Array-Processed Stacked Semiconductor Packages
US8048479B2 (en) 2006-08-01 2011-11-01 Qimonda Ag Method for placing material onto a target board by means of a transfer board
JP2008039502A (ja) 2006-08-03 2008-02-21 Alps Electric Co Ltd 接触子およびその製造方法
US7486525B2 (en) 2006-08-04 2009-02-03 International Business Machines Corporation Temporary chip attach carrier
US7425758B2 (en) 2006-08-28 2008-09-16 Micron Technology, Inc. Metal core foldover package structures
KR20080020069A (ko) 2006-08-30 2008-03-05 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR100891516B1 (ko) 2006-08-31 2009-04-06 주식회사 하이닉스반도체 적층 가능한 에프비지에이 타입 반도체 패키지와 이를이용한 적층 패키지
KR100770934B1 (ko) 2006-09-26 2007-10-26 삼성전자주식회사 반도체 패키지와 그를 이용한 반도체 시스템 패키지
TWI336502B (en) 2006-09-27 2011-01-21 Advanced Semiconductor Eng Semiconductor package and semiconductor device and the method of making the same
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
TWI312561B (en) 2006-10-27 2009-07-21 Advanced Semiconductor Eng Structure of package on package and method for fabricating the same
KR100817073B1 (ko) 2006-11-03 2008-03-26 삼성전자주식회사 휨방지용 보강부재가 기판에 연결된 반도체 칩 스택 패키지
US8193034B2 (en) 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
WO2008065896A1 (fr) 2006-11-28 2008-06-05 Kyushu Institute Of Technology Procédé de fabrication d'un dispositif semi-conducteur ayant une structure d'électrode à double face et dispositif semi-conducteur fabriqué par le procédé
US8598717B2 (en) 2006-12-27 2013-12-03 Spansion Llc Semiconductor device and method for manufacturing the same
JP2008166439A (ja) 2006-12-27 2008-07-17 Spansion Llc 半導体装置およびその製造方法
KR100757345B1 (ko) 2006-12-29 2007-09-10 삼성전자주식회사 플립 칩 패키지 및 그의 제조 방법
US20080156518A1 (en) 2007-01-03 2008-07-03 Tessera, Inc. Alignment and cutting of microelectronic substrates
TWI332702B (en) 2007-01-09 2010-11-01 Advanced Semiconductor Eng Stackable semiconductor package and the method for making the same
JP5347222B2 (ja) 2007-01-10 2013-11-20 富士通株式会社 半導体装置の製造方法
US7719122B2 (en) 2007-01-11 2010-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. System-in-package packaging for minimizing bond wire contamination and yield loss
KR100827667B1 (ko) 2007-01-16 2008-05-07 삼성전자주식회사 기판 내에 반도체 칩을 갖는 반도체 패키지 및 이를제조하는 방법
JP4823089B2 (ja) 2007-01-31 2011-11-24 株式会社東芝 積層型半導体装置の製造方法
WO2008093414A1 (ja) 2007-01-31 2008-08-07 Fujitsu Microelectronics Limited 半導体装置及びその製造方法
US8685792B2 (en) 2007-03-03 2014-04-01 Stats Chippac Ltd. Integrated circuit package system with interposer
JP5584474B2 (ja) 2007-03-05 2014-09-03 インヴェンサス・コーポレイション 貫通ビアによって前面接点に接続された後面接点を有するチップ
US7517733B2 (en) 2007-03-22 2009-04-14 Stats Chippac, Ltd. Leadframe design for QFN package with top terminal leads
JPWO2008117488A1 (ja) 2007-03-23 2010-07-08 三洋電機株式会社 半導体装置およびその製造方法
TWI335070B (en) 2007-03-23 2010-12-21 Advanced Semiconductor Eng Semiconductor package and the method of making the same
WO2008120755A1 (ja) 2007-03-30 2008-10-09 Nec Corporation 機能素子内蔵回路基板及びその製造方法、並びに電子機器
JP4926787B2 (ja) 2007-03-30 2012-05-09 アオイ電子株式会社 半導体装置の製造方法
US7589394B2 (en) 2007-04-10 2009-09-15 Ibiden Co., Ltd. Interposer
JP5003260B2 (ja) 2007-04-13 2012-08-15 日本電気株式会社 半導体装置およびその製造方法
US7994622B2 (en) 2007-04-16 2011-08-09 Tessera, Inc. Microelectronic packages having cavities for receiving microelectric elements
KR20080094251A (ko) 2007-04-19 2008-10-23 삼성전자주식회사 웨이퍼 레벨 패키지 및 그 제조방법
JP5601751B2 (ja) 2007-04-26 2014-10-08 スパンション エルエルシー 半導体装置
US20080284045A1 (en) 2007-05-18 2008-11-20 Texas Instruments Incorporated Method for Fabricating Array-Molded Package-On-Package
JP2008306128A (ja) 2007-06-11 2008-12-18 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
KR100865125B1 (ko) 2007-06-12 2008-10-24 삼성전기주식회사 반도체 패키지 및 그 제조방법
TW200908819A (en) 2007-06-15 2009-02-16 Ngk Spark Plug Co Wiring substrate with reinforcing member
JP5179787B2 (ja) 2007-06-22 2013-04-10 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
US7944034B2 (en) 2007-06-22 2011-05-17 Texas Instruments Incorporated Array molded package-on-package having redistribution lines
US7911805B2 (en) 2007-06-29 2011-03-22 Tessera, Inc. Multilayer wiring element having pin interface
SG148901A1 (en) 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
KR20090007120A (ko) 2007-07-13 2009-01-16 삼성전자주식회사 봉지부를 통하여 재배선을 달성하는 웨이퍼 레벨 적층형패키지 및 그 제조방법
US7781877B2 (en) 2007-08-07 2010-08-24 Micron Technology, Inc. Packaged integrated circuit devices with through-body conductive vias, and methods of making same
JP2009044110A (ja) 2007-08-13 2009-02-26 Elpida Memory Inc 半導体装置及びその製造方法
SG150396A1 (en) 2007-08-16 2009-03-30 Micron Technology Inc Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
US8039960B2 (en) 2007-09-21 2011-10-18 Stats Chippac, Ltd. Solder bump with inner core pillar in semiconductor package
KR101388538B1 (ko) 2007-09-28 2014-04-23 테세라, 인코포레이티드 이중 포스트를 사용하여 플립칩 상호연결한 마이크로전자 어셈블리
JP2009088254A (ja) 2007-09-28 2009-04-23 Toshiba Corp 電子部品パッケージ及び電子部品パッケージの製造方法
KR20090033605A (ko) 2007-10-01 2009-04-06 삼성전자주식회사 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US20090091009A1 (en) 2007-10-03 2009-04-09 Corisis David J Stackable integrated circuit package
US8008183B2 (en) 2007-10-04 2011-08-30 Texas Instruments Incorporated Dual capillary IC wirebonding
US7834464B2 (en) 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
TWI389220B (zh) 2007-10-22 2013-03-11 矽品精密工業股份有限公司 半導體封裝件及其製法
JP2009123863A (ja) 2007-11-14 2009-06-04 Tessera Interconnect Materials Inc バンプ構造形成方法及びバンプ構造
US20090127686A1 (en) 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
KR100886100B1 (ko) 2007-11-29 2009-02-27 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
JP2009135398A (ja) 2007-11-29 2009-06-18 Ibiden Co Ltd 組合せ基板
US7902644B2 (en) 2007-12-07 2011-03-08 Stats Chippac Ltd. Integrated circuit package system for electromagnetic isolation
US7964956B1 (en) 2007-12-10 2011-06-21 Oracle America, Inc. Circuit packaging and connectivity
US8390117B2 (en) 2007-12-11 2013-03-05 Panasonic Corporation Semiconductor device and method of manufacturing the same
JP2009158593A (ja) 2007-12-25 2009-07-16 Tessera Interconnect Materials Inc バンプ構造およびその製造方法
US20090170241A1 (en) 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
CN101971313B (zh) 2008-01-30 2013-07-24 库力索法工业公司 导线环以及形成导线环的方法
US8120186B2 (en) 2008-02-15 2012-02-21 Qimonda Ag Integrated circuit and method
US8258015B2 (en) 2008-02-22 2012-09-04 Stats Chippac Ltd. Integrated circuit package system with penetrable film adhesive
US7956456B2 (en) 2008-02-27 2011-06-07 Texas Instruments Incorporated Thermal interface material design for enhanced thermal performance and improved package structural integrity
KR101501739B1 (ko) 2008-03-21 2015-03-11 삼성전자주식회사 반도체 패키지 제조 방법
US7919871B2 (en) 2008-03-21 2011-04-05 Stats Chippac Ltd. Integrated circuit package system for stackable devices
US8072079B2 (en) 2008-03-27 2011-12-06 Stats Chippac, Ltd. Through hole vias at saw streets including protrusions or recesses for interconnection
JP5043743B2 (ja) 2008-04-18 2012-10-10 ラピスセミコンダクタ株式会社 半導体装置の製造方法
KR20090123680A (ko) 2008-05-28 2009-12-02 주식회사 하이닉스반도체 적층 반도체 패키지
US8021907B2 (en) 2008-06-09 2011-09-20 Stats Chippac, Ltd. Method and apparatus for thermally enhanced semiconductor package
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
US7932170B1 (en) 2008-06-23 2011-04-26 Amkor Technology, Inc. Flip chip bump structure and fabrication method
TWI473553B (zh) 2008-07-03 2015-02-11 Advanced Semiconductor Eng 晶片封裝結構
US7859033B2 (en) 2008-07-09 2010-12-28 Eastman Kodak Company Wafer level processing for backside illuminated sensors
JP5339800B2 (ja) 2008-07-10 2013-11-13 三菱電機株式会社 半導体装置の製造方法
TWI372453B (en) 2008-09-01 2012-09-11 Advanced Semiconductor Eng Copper bonding wire, wire bonding structure and method for processing and bonding a wire
SG177945A1 (en) 2008-07-18 2012-02-28 United Test & Assembly Ct Lt Packaging structural member
US8004093B2 (en) 2008-08-01 2011-08-23 Stats Chippac Ltd. Integrated circuit package stacking system
US20100044860A1 (en) 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
KR100997793B1 (ko) 2008-09-01 2010-12-02 주식회사 하이닉스반도체 반도체 패키지 및 이의 제조 방법
KR20100033012A (ko) 2008-09-19 2010-03-29 주식회사 하이닉스반도체 반도체 패키지 및 이를 갖는 적층 반도체 패키지
US7842541B1 (en) 2008-09-24 2010-11-30 Amkor Technology, Inc. Ultra thin package and fabrication method
US8063475B2 (en) 2008-09-26 2011-11-22 Stats Chippac Ltd. Semiconductor package system with through silicon via interposer
JPWO2010041630A1 (ja) 2008-10-10 2012-03-08 日本電気株式会社 半導体装置及びその製造方法
JP5185062B2 (ja) 2008-10-21 2013-04-17 パナソニック株式会社 積層型半導体装置及び電子機器
MY149251A (en) 2008-10-23 2013-07-31 Carsem M Sdn Bhd Wafer-level package using stud bump coated with solder
KR101461630B1 (ko) 2008-11-06 2014-11-20 삼성전자주식회사 실장 높이는 축소되나, 솔더 접합 신뢰도는 개선되는 웨이퍼 레벨 칩 온 칩 패키지와, 패키지 온 패키지 및 그 제조방법
TW201023308A (en) 2008-12-01 2010-06-16 Advanced Semiconductor Eng Package-on-package device, semiconductor package and method for manufacturing the same
KR101011863B1 (ko) 2008-12-02 2011-01-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US7642128B1 (en) 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US7898083B2 (en) 2008-12-17 2011-03-01 Texas Instruments Incorporated Method for low stress flip-chip assembly of fine-pitch semiconductor devices
US8012797B2 (en) 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
JP2010199528A (ja) 2009-01-27 2010-09-09 Tatsuta System Electronics Kk ボンディングワイヤ
JP2010177597A (ja) 2009-01-30 2010-08-12 Sanyo Electric Co Ltd 半導体モジュールおよび携帯機器
US20100200981A1 (en) 2009-02-09 2010-08-12 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
US9142586B2 (en) 2009-02-24 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for backside illuminated image sensor
JP2010206007A (ja) 2009-03-04 2010-09-16 Nec Corp 半導体装置及びその製造方法
WO2010101163A1 (ja) 2009-03-04 2010-09-10 日本電気株式会社 機能素子内蔵基板及びそれを用いた電子デバイス
US8106498B2 (en) 2009-03-05 2012-01-31 Stats Chippac Ltd. Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof
US8258010B2 (en) 2009-03-17 2012-09-04 Stats Chippac, Ltd. Making a semiconductor device having conductive through organic vias
US20100244276A1 (en) 2009-03-25 2010-09-30 Lsi Corporation Three-dimensional electronics package
US8194411B2 (en) 2009-03-31 2012-06-05 Hong Kong Applied Science and Technology Research Institute Co. Ltd Electronic package with stacked modules with channels passing through metal layers of the modules
US20100289142A1 (en) 2009-05-15 2010-11-18 Il Kwon Shim Integrated circuit packaging system with coin bonded interconnects and method of manufacture thereof
US8020290B2 (en) 2009-06-14 2011-09-20 Jayna Sheats Processes for IC fabrication
TWI379367B (en) 2009-06-15 2012-12-11 Kun Yuan Technology Co Ltd Chip packaging method and structure thereof
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
JP5214554B2 (ja) 2009-07-30 2013-06-19 ラピスセミコンダクタ株式会社 半導体チップ内蔵パッケージ及びその製造方法、並びに、パッケージ・オン・パッケージ型半導体装置及びその製造方法
US7923304B2 (en) 2009-09-10 2011-04-12 Stats Chippac Ltd. Integrated circuit packaging system with conductive pillars and method of manufacture thereof
US8264091B2 (en) 2009-09-21 2012-09-11 Stats Chippac Ltd. Integrated circuit packaging system with encapsulated via and method of manufacture thereof
US8390108B2 (en) 2009-12-16 2013-03-05 Stats Chippac Ltd. Integrated circuit packaging system with stacking interconnect and method of manufacture thereof
US8169065B2 (en) 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
TWI392066B (zh) 2009-12-28 2013-04-01 矽品精密工業股份有限公司 封裝結構及其製法
US9496152B2 (en) 2010-03-12 2016-11-15 STATS ChipPAC Pte. Ltd. Carrier system with multi-tier conductive posts and method of manufacture thereof
US7928552B1 (en) 2010-03-12 2011-04-19 Stats Chippac Ltd. Integrated circuit packaging system with multi-tier conductive interconnects and method of manufacture thereof
KR101667656B1 (ko) 2010-03-24 2016-10-20 삼성전자주식회사 패키지-온-패키지 형성방법
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8564141B2 (en) 2010-05-06 2013-10-22 SK Hynix Inc. Chip unit and stack package having the same
US8217502B2 (en) 2010-06-08 2012-07-10 Stats Chippac Ltd. Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
KR20120007839A (ko) 2010-07-15 2012-01-25 삼성전자주식회사 적층형 반도체 패키지의 제조방법
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
KR101683814B1 (ko) 2010-07-26 2016-12-08 삼성전자주식회사 관통 전극을 구비하는 반도체 장치
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8304900B2 (en) 2010-08-11 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with stacked lead and method of manufacture thereof
US8518746B2 (en) 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
US20120063090A1 (en) 2010-09-09 2012-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling mechanism for stacked die package and method of manufacturing the same
US8409922B2 (en) 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
US20120080787A1 (en) 2010-10-05 2012-04-05 Qualcomm Incorporated Electronic Package and Method of Making an Electronic Package
US8618646B2 (en) 2010-10-12 2013-12-31 Headway Technologies, Inc. Layered chip package and method of manufacturing same
JP2012104790A (ja) 2010-10-12 2012-05-31 Elpida Memory Inc 半導体装置
US8263435B2 (en) 2010-10-28 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias
US8697492B2 (en) 2010-11-02 2014-04-15 Tessera, Inc. No flow underfill
US8525318B1 (en) 2010-11-10 2013-09-03 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
US8502387B2 (en) 2010-12-09 2013-08-06 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
KR101215271B1 (ko) 2010-12-29 2012-12-26 앰코 테크놀로지 코리아 주식회사 반도체 패키지 구조물 및 반도체 패키지 구조물의 제조 방법
US20120184116A1 (en) 2011-01-18 2012-07-19 Tyco Electronics Corporation Interposer
US8476115B2 (en) 2011-05-03 2013-07-02 Stats Chippac, Ltd. Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9006031B2 (en) 2011-06-23 2015-04-14 Stats Chippac, Ltd. Semiconductor device and method of forming EWLB package with standoff conductive layer over encapsulant bumps
US8487421B2 (en) 2011-08-01 2013-07-16 Tessera, Inc. Microelectronic package with stacked microelectronic elements and method for manufacture thereof
US8937309B2 (en) 2011-08-08 2015-01-20 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US20130037929A1 (en) 2011-08-09 2013-02-14 Kay S. Essig Stackable wafer level packages and related methods
KR101800440B1 (ko) 2011-08-31 2017-11-23 삼성전자주식회사 다수의 반도체 칩들을 가진 반도체 패키지 및 그 형성 방법
US20130049218A1 (en) 2011-08-31 2013-02-28 Zhiwei Gong Semiconductor device packaging having pre-encapsulation through via formation
US9177832B2 (en) 2011-09-16 2015-11-03 Stats Chippac, Ltd. Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect
KR101906408B1 (ko) 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US9105552B2 (en) 2011-10-31 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
KR101297015B1 (ko) 2011-11-03 2013-08-14 주식회사 네패스 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법, 이에 의한 반도체 패키지 및 패키지 온 패키지
US8912651B2 (en) 2011-11-30 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure including stud bulbs and method
US8680684B2 (en) 2012-01-09 2014-03-25 Invensas Corporation Stackable microelectronic package structures
US9258922B2 (en) 2012-01-18 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. PoP structures including through-assembly via modules
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US20130234317A1 (en) 2012-03-09 2013-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Packaged Semiconductor Devices
US9082763B2 (en) 2012-03-15 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Joint structure for substrates and methods of forming
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9171790B2 (en) 2012-05-30 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8828860B2 (en) 2012-08-30 2014-09-09 International Business Machines Corporation Double solder bumps on substrates for low temperature flip chip bonding
KR101419597B1 (ko) 2012-11-06 2014-07-14 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US8940630B2 (en) 2013-02-01 2015-01-27 Invensas Corporation Method of making wire bond vias and microelectronic package having wire bond vias
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9299670B2 (en) 2013-03-14 2016-03-29 Freescale Semiconductor, Inc. Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3430835A (en) * 1966-06-07 1969-03-04 Westinghouse Electric Corp Wire bonding apparatus for microelectronic components
US4213556A (en) * 1978-10-02 1980-07-22 General Motors Corporation Method and apparatus to detect automatic wire bonder failure
US4327860A (en) * 1980-01-03 1982-05-04 Kulicke And Soffa Ind. Inc. Method of making slack free wire interconnections

Also Published As

Publication number Publication date
WO2015021277A3 (en) 2015-04-02
TW201511197A (zh) 2015-03-16
US9685365B2 (en) 2017-06-20
US20150044823A1 (en) 2015-02-12
WO2015021277A2 (en) 2015-02-12

Similar Documents

Publication Publication Date Title
TWI588949B (zh) 具有整合式承載表面的微電子封裝
US10008477B2 (en) Microelectronic element with bond elements to encapsulation surface
US10833044B2 (en) Package-on-package assembly with wire bonds to encapsulation surface
US10510659B2 (en) Substrate-less stackable package with wire-bond interconnect
US10297582B2 (en) BVA interposer
US8618659B2 (en) Package-on-package assembly with wire bonds to encapsulation surface
KR101522770B1 (ko) 패키지 정렬 구조물 및 패키지 정렬 구조물의 형성 방법
JP2016505222A (ja) ワイヤボンドビアを有するマイクロ電子パッケージ、その製造方法、およびそのための補強層
US11830845B2 (en) Package-on-package assembly with wire bonds to encapsulation surface

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees