JP5453678B2 - 半導体パッケージおよびその製造方法 - Google Patents
半導体パッケージおよびその製造方法 Download PDFInfo
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- JP5453678B2 JP5453678B2 JP2010147196A JP2010147196A JP5453678B2 JP 5453678 B2 JP5453678 B2 JP 5453678B2 JP 2010147196 A JP2010147196 A JP 2010147196A JP 2010147196 A JP2010147196 A JP 2010147196A JP 5453678 B2 JP5453678 B2 JP 5453678B2
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- semiconductor chip
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- 239000004065 semiconductor Substances 0.000 title claims description 200
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 54
- 229920005989 resin Polymers 0.000 claims description 48
- 239000011347 resin Substances 0.000 claims description 48
- 229920001187 thermosetting polymer Polymers 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 28
- 239000010931 gold Substances 0.000 description 10
- 229910000679 solder Inorganic materials 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 238000010030 laminating Methods 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
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- 230000000694 effects Effects 0.000 description 3
- 238000003892 spreading Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
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- 238000005422 blasting Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
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- 238000001746 injection moulding Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
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- 238000007789 sealing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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Classifications
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Description
先ず、半導体パッケージ200の製造方法の概略を説明すると、第1の半導体チップ210の電極部に金(Au)バンプ211を形成し、第1の半導体チップ210が接続される配線基板230の電極部232にははんだコート237を形成する。次いで、NCF(Non−Conductive Film)に例示されるフィルム状の熱硬化性樹脂(以下、「熱硬化性樹脂フィルム」という)203を配線基板230に貼り付ける。次いで、第1の半導体チップ210の金(Au)バンプ211と、熱硬化性樹脂フィルム203を貼り付けた配線基板230のはんだコート部237とを加熱圧着によって接続を行う。その際に熱硬化性樹脂フィルム203が同時に硬化される。次いで、熱硬化性樹脂フィルム203を所定の温度、時間により完全に硬化させる。次いで、第1の半導体チップ210の上に、第2の半導体チップ220をダイボンディングにより接合するというものである。
ここで課題となったのが、第1の半導体チップ210上に搭載する第2の半導体チップ220が、当該第1の半導体チップ210からオーバーハングする設計(L:オーバーハング量)の場合、すなわち、第2の半導体チップ220の外形が、第1の半導体チップ210の外形よりも大きい場合には、製造工程中において図8の写真(図7のコーナー部Bを拡大した写真である)および図9の概略図(図7に示す平面に対して垂直方向の断面を模式的に表した図である)に示すように、第2の半導体チップ220の外縁部220a(特にコーナー部)の下に空隙(符号Cで表示)が生じ易いことであった。すなわち、当該空隙が生じると、第2の半導体チップ220上面の外縁部220aに設けられる電極部(不図示)と配線基板230上の電極部233とをワイヤボンディングによって接続する工程において、第2の半導体チップ220が撓む原因となり、接続が不安定となる。また、全体をモールドする工程において、第1の半導体チップ210と第2の半導体チップ220との境界面に隙間が生じてモールドボイドの危険が高まる。これらの課題は、第2の半導体チップ220のオーバーハング量Lが大きい場合程、顕著に生じ得る。
その結果、第2の半導体チップ上面の外縁部に設けられた電極部と配線基板上の電極部とをワイヤボンディングによって接続する際に、第2の半導体チップの外縁部の撓みが防止でき、接続の安定化を図ることができる。また、モールドを行う際に、モールドボイド発生の抑制を図ることができる。
図1は、半導体パッケージ1の例を示す概略図(断面図)である。なお、図中において、説明の便宜上、実際の寸法・縮尺とは異なって図示されている部分がある。
また、第1の半導体チップ10には配線基板30に対向する面10aに、電極部32と接続される接続バンプ11が設けられる。一例として、接続バンプ11は金(Au)を用いて形成される。
一方、第2の半導体チップ20の上面20eにおける外縁部20a領域には電極部(不図示)が設けられており、配線基板30上において第1の半導体チップ10の搭載位置よりも外方に設けられた電極部33との間でワイヤボンディング接続が行われる。
一例として、半導体パッケージ1は、図1に示すように、モールド樹脂6によってモールドされて形成されるが、モールドされない状態での流通形態も考えられる。
台座36の形成例については前述の通りである(図2参照)。本実施形態においては、配線基板30の上面30a上であって、後工程で配設される第2の半導体チップ20のコーナー部20bが配置される予定位置に対応する位置に、コーナー部台座36aを形成する。また、配線基板30の上面30a上であって、後工程で配設される第2の半導体チップ20の隣接するコーナー部20b、20b間の辺部20cが配置される予定位置に対応する位置に、コーナー部台座36aと連続でもしくは不連続で(本実施形態では不連続としている)辺部台座36bを形成する。なお、配線基板30上面の電極部33(33a)の配置あるいは第1の半導体チップ10の形状等に応じて、コーナー部台座36aのみを設ける構成としてもよい。
なお、熱硬化性樹脂フィルム3には、一例として、エポキシ系熱硬化性樹脂が用いられる。また、熱硬化性樹脂フィルム3を配線基板30の上に貼り付ける方法には、一例として、真空ラミネート法が用いられる。
これによって、第1の半導体チップ10と配線基板30との間に挟まれた熱硬化性樹脂フィルム3は押し広げられるようにして、第1の半導体チップ10と配線基板30との間の空間部を充填すると共に、台座36の上面を越え、第1の半導体チップ10と配線基板30との間から当該第1の半導体チップ10の外方へ(外周部から外側に向けて)流出する。また、第1の半導体チップ10の接続バンプ11と配線基板30の電極部32a上のはんだコート37とが接触する。さらに、当該第1の半導体チップ10を介して配線基板30のはんだコート37が加熱されて溶融し、接触状態にあった接続バンプ11とはんだコート37すなわち電極部32aとが接合されると共に、第1の半導体チップ10と配線基板30との間の空間部内に充填された熱硬化性樹脂フィルム3も加熱されて硬化する。
ここで、台座36が設けられていることの効果として、台座36形成位置においては、当該台座36の上面とボンディングツール2の押圧面との間の隙間が狭いため(すなわち、容積が小さいため)、熱硬化性樹脂フィルム3が、より一層、第1の半導体チップ10の外方まで(外周部から外側に向けて)流出する効果が得られる。
特に、台座36として、コーナー部台座36aを設けることによって、当該コーナー部台座36a形成位置において、熱硬化性樹脂フィルム3をより一層外方まで広げることができるため、円形状に広がる性質を有する熱硬化性樹脂フィルム3をいわば矩形状に近づけて形成することができる。すなわち、第1の半導体チップ10よりも第2の半導体チップ20の方が外形が大きい場合に、第2の半導体チップ20の外縁部20a(特にコーナー部20b)の最外周位置の直下まで、熱硬化性樹脂フィルム3を充填させることができ、図9で説明したような空隙の発生を防止することができる。
なお、配線基板30の下面に設けられた外部接続用の電極部33(33b)は、当該パッドにはんだボールやリードピンを接続して外部接続端子としても良く、あるいは、当該電極部自体を外部接続端子としても良い。
2 ボンディングツール
3 熱硬化性樹脂フィルム
5 ワイヤ
6 モールド樹脂
10 第1の半導体チップ
11 接続バンプ
20 第2の半導体チップ
30 配線基板
32、33 電極部
36 台座
Claims (5)
- 配線基板の上に、熱硬化性樹脂フィルムを介して第1の半導体チップがフリップチップ実装方式により加熱圧着され、前記第1の半導体チップの上に、第2の半導体チップが搭載されて形成される半導体パッケージにおいて、
前記第2の半導体チップは、前記第1の半導体チップより外形が大きく、
前記配線基板上には、前記第1の半導体チップの外周よりも外方の位置で、且つ前記第2の半導体チップの外縁部の直下の位置に、該第2の半導体チップの下面に接触しない高さの突起状の台座が設けられ、
前記熱硬化性樹脂フィルムは、前記台座を包み込む形状を有し、前記第1の半導体チップの外周よりも外方の位置における上面が該第1の半導体チップの上面と同一の平坦面に形成され、且つ、前記第2の半導体チップの外周よりも外方に配設される外縁部がフィレット形状に形成されており、
前記台座として、前記第2の半導体チップのコーナー部に対応する位置に、コーナー部台座が設けられると共に、前記第2の半導体チップの隣接するコーナー部間の辺部に対応する位置に、前記コーナー部台座と連続でもしくは不連続で辺部台座が設けられること
を特徴とする半導体パッケージ。 - 前記コーナー部台座は、略L字状もしくは円弧状に形成されていること
を特徴とする請求項1記載の半導体パッケージ。 - 配線基板の上に、第1の半導体チップが搭載され、該第1の半導体チップの上に、該第1の半導体チップよりも外形の大きい第2の半導体チップが搭載されて形成される半導体パッケージの製造方法であって、
前記配線基板上において、後工程で搭載される前記第2の半導体チップの外縁部が配置される予定位置の直下の位置に、該第2の半導体チップの下面に接触しない高さの突起状の台座を形成する工程と、
前記配線基板上に、所定形状の熱硬化性樹脂フィルムを介してフリップチップ実装方式により第1の半導体チップを加熱圧着し、前記熱硬化性樹脂フィルムは、前記台座を包み込み、前記第1の半導体チップの外周よりも外方の位置における上面が該第1の半導体チップの上面と同一の平坦面に形成され、且つ、前記第2の半導体チップの外周よりも外方に配設される外縁部がフィレット形状に形成される工程と、
前記第1の半導体チップ上に、前記第2の半導体チップを搭載する工程と、を備え、
前記台座を形成する工程は、前記第2の半導体チップのコーナー部が配置される予定位置に対応する位置に、コーナー部台座を形成する工程と、前記第2の半導体チップの隣接するコーナー部間の辺部が配置される予定位置に対応する位置に、前記コーナー部台座と連続でもしくは不連続で辺部台座を形成する工程と、を有すること
を特徴とする半導体パッケージの製造方法。 - 前記コーナー部台座を、略L字状もしくは円弧状に形成すること
を特徴とする請求項3記載の半導体パッケージの製造方法。 - 前記第2の半導体チップを搭載する工程は、
前記第1の半導体チップ上に、前記第2の半導体チップをダイボンディングによって接合する工程と、
前記第2の半導体チップの上面に設けられた電極部と、前記配線基板上において前記前記第1の半導体チップの搭載位置よりも外方に設けられた電極部とをワイヤボンディングによって接続する工程と、を備えること
を特徴とする請求項3または請求項4記載の半導体パッケージの製造方法。
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