JP4620553B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4620553B2 JP4620553B2 JP2005249029A JP2005249029A JP4620553B2 JP 4620553 B2 JP4620553 B2 JP 4620553B2 JP 2005249029 A JP2005249029 A JP 2005249029A JP 2005249029 A JP2005249029 A JP 2005249029A JP 4620553 B2 JP4620553 B2 JP 4620553B2
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- JP
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- Prior art keywords
- chip
- resin
- filler
- underfill resin
- mold resin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
これを防ぐために、配線基板とチップとの隙間より小さいフィラー、例えば直径が5μm以下のフィラーのみを含有するモールド樹脂を用いる手段が考えられる。しかし、直径の小さいフィラーのみを含有するモールド樹脂を用いると、フィラーの表面積が大きくなって粘度が上がるため、金線の変形や未充填の発生などによって成形が困難になるという問題があった。そして、粘度を下げるためにフィラーの含有量を減らすと、モールド樹脂の熱膨張係数が大きくなり、パッケージの反りが発生するという問題があった。
2 Auめっきランド
3,8 チップ
4 Auスタッドバンプ
5 アンダーフィル樹脂
6 ステージ
7 治具
9 ワイヤ
10 モールド樹脂
Claims (4)
- (a)配線基板上に、複数のバンプを介して、チップをフリップチップ接続し、前記配線基板と前記チップの隙間を前記チップの角部を残してアンダーフィル樹脂で充填する工程と、
(b)前記工程(a)の後、前記チップと、前記アンダーフィル樹脂から露出する前記チップの角部における前記隙間を、前記アンダーフィル樹脂と異なるモールド樹脂で封止する工程とを有し、
前記モールド樹脂は、前記隙間以上の直径のフィラーを含有し、
前記モールド樹脂中の前記隙間以上の直径のフィラーの割合は、2wt%以下であることを特徴とする半導体装置の製造方法。 - 前記アンダーフィル樹脂は、フィラーを含有し、
前記モールド樹脂における全体のフィラーの含有率は、前記アンダーフィル樹脂における全体のフィラーの含有率より高いことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記モールド樹脂のフィラー及び前記アンダーフィル樹脂のフィラーは、シリカであることを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記アンダーフィル樹脂のフィラーの直径は、前記隙間よりも小さいことを特徴とする請求項3に記載の半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005249029A JP4620553B2 (ja) | 2005-08-30 | 2005-08-30 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005249029A JP4620553B2 (ja) | 2005-08-30 | 2005-08-30 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007067047A JP2007067047A (ja) | 2007-03-15 |
JP4620553B2 true JP4620553B2 (ja) | 2011-01-26 |
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Application Number | Title | Priority Date | Filing Date |
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JP2005249029A Expired - Fee Related JP4620553B2 (ja) | 2005-08-30 | 2005-08-30 | 半導体装置の製造方法 |
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JP (1) | JP4620553B2 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009188392A (ja) * | 2008-01-08 | 2009-08-20 | Toppan Printing Co Ltd | 半導体装置及び半導体装置の製造方法 |
JP5250524B2 (ja) * | 2009-10-14 | 2013-07-31 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP2011210759A (ja) * | 2010-03-29 | 2011-10-20 | Casio Computer Co Ltd | 半導体装置及び半導体装置の製造方法 |
US8742603B2 (en) * | 2010-05-20 | 2014-06-03 | Qualcomm Incorporated | Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC) |
JP5453678B2 (ja) * | 2010-06-29 | 2014-03-26 | 新光電気工業株式会社 | 半導体パッケージおよびその製造方法 |
JP2012109437A (ja) | 2010-11-18 | 2012-06-07 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP6094592B2 (ja) | 2012-10-01 | 2017-03-15 | 富士電機株式会社 | 半導体装置とその製造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0745754A (ja) * | 1993-07-30 | 1995-02-14 | Kyocera Corp | Ic封止樹脂 |
JP2003124402A (ja) * | 2001-10-17 | 2003-04-25 | New Japan Radio Co Ltd | 半導体パッケージおよびその製造方法 |
-
2005
- 2005-08-30 JP JP2005249029A patent/JP4620553B2/ja not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0745754A (ja) * | 1993-07-30 | 1995-02-14 | Kyocera Corp | Ic封止樹脂 |
JP2003124402A (ja) * | 2001-10-17 | 2003-04-25 | New Japan Radio Co Ltd | 半導体パッケージおよびその製造方法 |
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JP2007067047A (ja) | 2007-03-15 |
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