TW201826477A - 半導體晶片封裝和疊層封裝 - Google Patents

半導體晶片封裝和疊層封裝 Download PDF

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Publication number
TW201826477A
TW201826477A TW106143338A TW106143338A TW201826477A TW 201826477 A TW201826477 A TW 201826477A TW 106143338 A TW106143338 A TW 106143338A TW 106143338 A TW106143338 A TW 106143338A TW 201826477 A TW201826477 A TW 201826477A
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Taiwan
Prior art keywords
bonding pad
semiconductor die
conductive paste
bonding
substrate
Prior art date
Application number
TW106143338A
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English (en)
Inventor
蔡憲聰
王學德
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聯發科技股份有限公司
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Publication date
Priority claimed from US15/701,456 external-priority patent/US10685943B2/en
Application filed by 聯發科技股份有限公司 filed Critical 聯發科技股份有限公司
Publication of TW201826477A publication Critical patent/TW201826477A/zh

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

本發明提供一種半導體晶片封裝和疊層封裝，半導體晶片封裝包括：基板；安裝在該基板上的半導體裸片，其中該半導體裸片包括設置在該半導體裸片的主動表面上的接合焊盤以及覆蓋該接合焊盤周邊的鈍化層，其中該鈍化層中的接合焊盤開口暴露於該接合焊盤的中心區域；導電漿料柱，印刷在該接合焊盤暴露的中心區域上；以及接合線，固定在該導電漿料柱的上表面。從而避免相鄰接合焊盤之間的短路，並可採用更小的接合焊盤開口和接合焊盤間距。同時施加在頂部裸片的突出側邊緣上的應力可減少或避免，引線接合製程的生產量也得到提高。

Description

半導體晶片封裝和疊層封裝
本發明涉及半導體技術領域，更具體地，涉及一種半導體裝置和疊層封裝。
本發明涉及積體電路和半導體晶片封裝的相互連接。
積體電路（IC）裸片（die）係形成在例如矽晶圓的半導體晶圓（semiconductor wafer）上的小元件。這種裸片通常係從晶圓上切割下來後連接到基板以形成相互連接的重新分佈。之後裸片上的焊盤通過引線接合法與基板上的引線電連接。然後將裸片和接合線用塑封材料（molding compound）包封以形成半導體封裝。
通常，包封在半導體封裝中的引線在載體內的導體網路中重新分佈，並且在半導體封裝外部的端子陣列中終止。製造商已經在單個包裝中堆疊了兩個或更多個裸片。這種裝置有時被稱為多晶片堆疊封裝（stacked multichip package）。
第1圖中示出了通常地一個的多晶片堆疊封裝。在該結構中，第一裸片11安裝在基板10上。然後可以將第二裸片12黏合地固定到第一裸片11的上表面，從而形成裸片堆疊結構。當從上方觀察時，第二裸片12與第一裸片11部分重疊。然後使用常規的焊線機，通過接合線16和18將第一裸片11和第二裸片12與基板10上各自的接合指（bond finger）電連接。密封劑材料20在基板10上模制，以提供密封蓋板。
已知，間接式針腳接合製程（stand-off stitch bonding process）通常包括將平頂凸塊放置在諸如鋁焊盤的主動積體電路（IC）焊盤上，然後從基板或封裝反向接合到平頂球凸塊。然而，這樣難以在與突出側邊緣12a相鄰的第二裸片12的接合焊盤上形成接合線18。引線接合器引起的應力可能導致第一裸片11和第二裸片12之間的剝離，並降低了生產率。
有鑑於此，本發明提供一種半導體裝置和疊層封裝，使得施加在頂部裸片的突出側邊緣上的應力可以減少或避免，引線接合製程的生產量也得到提高。
根據本發明的第一方面，公開一種半導體晶片封裝，包括：基板；安裝在該基板上的半導體裸片，其中該半導體裸片包括設置在該半導體裸片的主動表面上的接合焊盤以及覆蓋該接合焊盤周邊的鈍化層，其中該鈍化層中的接合焊盤開口暴露於該接合焊盤的中心區域；導電漿料柱，印刷在該接合焊盤暴露的中心區域上；以及接合線，固定在該導電漿料柱的上表面。
根據本發明的第二方面，公開一種半導體晶片封裝，包括：基板；安裝在該基板上的半導體裸片，其中該半導體裸片包括設置在該半導體裸片的主動表面上的接合焊盤以及覆蓋該接合焊盤周邊的鈍化層，其中該鈍化層中的接合焊盤開口暴露於該接合焊盤的中心區域；導電漿料柱，印刷在該接合焊盤暴露的中心區域上；導電跡線，印刷在該鈍化層上並與該導電漿料柱電連接；再分佈接合焊盤，印刷在該鈍化層上，其中再分佈接合焊盤通過該導電跡線與該導電漿料柱電連接；以及接合線，固定在該再分佈接合焊盤的上表面。
根據本發明的協力廠商面，公開一種疊層封裝，包括：底部封裝，安裝在基板上的第一半導體裸片和安裝在基板的下表面上的複數個焊球，其中該第一半導體裸片由第一塑封材料包封；導電跡線，印刷在該第一塑封材料上的；以及第二半導體裸片，安裝在該第一塑封材料上。
本發明提供的半導體晶片封裝由於半導體裸片包括設置在主動表面上的接合焊盤以及覆蓋接合焊盤周邊的鈍化層，鈍化層中的接合焊盤開口暴露於接合焊盤的中心區域，以及印刷在該接合焊盤暴露的中心區域上的導電漿料柱，固定在導電漿料柱的上表面的接合線。由於導電漿料柱的彈性特性，在導電漿料柱上形成接合線後，導電漿料柱會迅速恢復它的形狀，可以避免相鄰接合焊盤之間的短路，並且可以採用更小的接合焊盤開口和接合焊盤間距。同時施加在頂部裸片的突出側邊緣上的應力可以減少或避免，引線接合製程的生產量也得到提高。
以下描述為本發明實施的較佳實施例。以下實施例僅用來例舉闡釋本發明的技術特徵，並非用來限制本發明的範疇。在通篇說明書及申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域技術人員應可理解，製造商可能會用不同的名詞來稱呼同樣的元件。本說明書及申請專利範圍並不以名稱的差異來作為區別元件的方式，而係以元件在功能上的差異來作為區別的基準。本發明的範圍應當參考後附的申請專利範圍來確定。本發明中使用的術語“元件”、“系統”和“裝置”可以係與電腦相關的實體，其中，該電腦可以係硬體、軟體、或硬體和軟體的結合。在以下描述和申請專利範圍當中所提及的術語“包含”和“包括”為開放式用語，故應解釋成“包含，但不限定於…”的意思。此外，術語“耦接”意指間接或直接的電氣連接。因此，若文中描述一個裝置耦接至另一裝置，則代表該裝置可直接電氣連接於該另一裝置，或者透過其它裝置或連接手段間接地電氣連接至該另一裝置。
對這些實施例進行了詳細的描述係為了使本領域的技術人員能夠實施這些實施例，並且應當理解，在不脫離本發明的精神和範圍情況下，可以利用其他實施例進行機械、化學、電氣和程式上的改變。因此，以下詳細描述並非係限制性的，並且本發明的實施例的範圍僅由所附申請專利範圍第限定。
請參考第2圖至第4圖。第2圖至第4圖係示出根據本發明的一個實施例的用於間接式針腳接合製程的接合焊盤上的導電漿料柱的橫截面示意圖。如第2圖和第3圖所示，提供一種半導體裸片120，半導體裸片120上具有接合焊盤122。儘管在該圖中僅示出了一個接合焊盤122，但係應當理解的係半導體裸片120可以包括分佈在半導體裸片120的主動表面上的複數個接合焊盤。例如，接合焊盤122可以係鋁焊盤。
根據本發明的一個實施例，鈍化層124例如聚醯亞胺層可以形成在半導體裸片120上，並覆蓋接合焊盤122的周邊。根據本發明的一個實施例，接合焊盤開口124a暴露出接合焊盤122的中心區域。
根據本發明的一個實施例，導電漿料柱130印刷在接合焊盤122的暴露的中心區域上。例如，導電漿料柱130可以包括銅漿，銅材質導電性能優良，可以保證信號傳輸的穩定，但不限於此。根據本發明的一個實施例，導電漿料柱130可以通過使用絲網印刷製程形成。根據本發明的一個實施例，導電漿料柱130可以通過使用3D印刷製程形成。導電漿料柱用作緩衝劑以防止鋁擠出。
與傳統的間接式針腳焊接製程中形成的常規平頂球凸塊相比，導電漿料柱130具有更平坦的上表面130a。導電漿料柱130較平坦的上表面130a為半導體封裝提供了更高的可靠性和更好的性能。
根據本發明的一個實施例，例如，銅漿可以包括環氧樹脂，例如熱固性環氧樹脂，並且銅粉或銀包銅球作為填料，但不限於此。銅在氧化後會影響信號傳輸，使用銀包銅球可以有效防止銅的氧化，從而保證信號傳輸的穩定。在導電漿料柱130印刷在接合焊盤122上之後，可以對導電漿料柱130進行固化處理。根據本發明的一個實施例，導電漿料柱130可以通過熱處理或紫外（UV）光固化。
可選地，可以對導電漿料柱130的上表面130a進行蝕刻製程以暴露出更多的金屬填料，從而降低接觸電阻。根據本發明的另一個實施例，可以將具有低電阻的導電層131（例如Pt或Au）塗覆在導電漿料柱130的上表面130a上。
如第2圖所示，導電漿料柱130可以完全填滿接合焊盤開口124a。第2圖中，導電漿料柱130的周邊側壁與鈍化層124直接接觸。或者，如第3圖所示，導電漿料柱130不完全填滿接合焊盤開口124a。在第3圖中，導電漿料柱130的周邊側壁不與鈍化層124直接接觸。在導電漿料柱130的周邊側壁和鈍化層124之間可以形成間隙132。當如第2圖所示導電漿料柱130的周邊側壁與鈍化層124直接接觸時，更加方便生產加工，加工時可將鈍化層124直接覆蓋在半導體裸片120上及導電漿料柱130的周邊，從而加工效率更高。如第3圖所示，在將接合線等焊接在導電漿料柱130上時，導電漿料柱130受到壓力作用，可能會產生形變，從而使導電漿料柱130的側壁擴大，因此當導電漿料柱130的周邊側壁不與鈍化層124直接接觸時，可預留出供側壁擴大的餘量，從而避免因側壁的擠壓而造成鈍化層124變形等意外影響，保證結構的穩定性和提高生產良率。
第4圖示出了在將接合線接合在其上之後的導電漿料柱130。如第4圖所示，可以執行例如間接式針腳接合製程的引線接合製程，以將接合線180固定在導電漿料柱130的上表面130a上。根據本發明的一個實施例，導電漿料柱130代替在常規的間接式針腳接合製程中形成的常規平頂球凸塊。此外，在引線接合製程之前，可以將導電漿料柱130印刷在半導體裸片120上。因此，第1圖中顯示的施加在頂部裸片的突出側邊緣上的應力可以減少或避免。引線接合製程的生產量（UPH或unit per hour）也得到提高。
由於導電漿料柱130的彈性特性，導電漿料柱130能夠在形成接合線180後迅速恢復它的形狀。可以避免相鄰接合焊盤之間的短路。因此，可以採用更小的接合焊盤開口和接合焊盤間距。
第5圖示出了結合如第4圖所示的導電漿料柱的示例性半導體晶片封裝1，其中相同的數字表示相同的元件、區域或層。如第5圖所示，半導體晶片封裝1包括安裝在第一裸片110上的第二裸片120。第二裸片120黏合地固定到第一裸片110的上表面，從而產生堆疊的裸片結構。當從上方觀察時，第二裸片120與第一裸片110部分重疊。在基板100上模制密封劑材料200，例如環氧模塑膠，以提供密封劑蓋板。
使用焊線機，形成接合線160和180，以將第一裸片110和第二裸片120電連接到基板100上相應的接合指104和106。基板100可以係封裝基板，但不限於此。接合線180可以固定到基板100上的接合指104，然後反向接合到第二裸片120上的導電漿料柱130。
第6圖示出了結合如第4圖所示的導電漿料柱的示例性半導體晶片封裝2。其中相同的符號表示相同的元件、區域或層。如第6圖所示，半導體晶片封裝2包括安裝在基板100上的單個裸片120。使用焊線機，形成接合線180以將裸片120電連接到基板100上各自的接合指104。基板100可以係封裝基板，但不限於此。接合線180可以固定到基板100上的接合104，然後反向接合到裸片120上的導電漿料柱130。
應當理解，第2圖和第6圖所示的封裝結構只係為了說明的目的。在不脫離本發明的精神或範圍的情況下，可以採用其他包裝結構。
請參考第7圖至第10圖。第7圖至第10圖係示出根據本發明的複數種實施例的橫截面示意圖，其中相同的數字表示相同的元件、區域或層。第7圖至第10圖所示的再分佈層（RDL）結構可以適用於第5圖和第6圖所示的半導體晶片封裝。
如第7圖所示，同樣地，提供了一種在其上形成具有接合焊盤122的半導體裸片120。儘管在該圖中僅示出了一個接合焊盤122，但係應當理解，半導體裸片120可以包括分佈在半導體裸片120的主動表面上的複數個接合焊盤。例如，接合焊盤122可以係鋁焊盤。
根據本發明的一個實施例，鈍化層124例如聚醯亞胺層可以形成在半導體裸片120上並覆蓋接合焊盤122的周邊。根據本發明的一個實施例，接合焊盤開口124a暴露出接合焊盤122的中心區域。
根據本發明的一個實施例，導電漿料柱130印刷在接合焊盤122的暴露的中心區域上。例如，導電漿料柱130可以包括銅漿，但不限於此。根據本發明的一個實施例，導電漿料柱130可以通過使用絲網印刷製程形成。根據本發明的另一個實施例，導電漿料柱130可以通過使用3D印刷製程形成。
根據本發明的一個實施例，導電跡線136印刷在鈍化層124上。導電跡線136與導電漿料柱130電連接。導電跡線136可以包括銅漿，但不限於此。根據本發明的一個實施例，可以通過使用相同的印刷製程來印刷導電漿料柱130和導電跡線136。
根據本發明的一個實施例，再分佈接合焊盤138也印刷在鈍化層124上。再分佈接合焊盤138通過導電跡線136電連接到導電漿料柱130。再分佈接合焊盤138比導電跡線136厚。
根據本發明的一個實施例，可以通過使用相同的印刷製程來印刷導電漿料柱130、導電跡線136和再分佈接合焊盤138，並且可以進行固化處理。導電漿料柱130在結構上與導電跡線136和再分佈接合焊盤138成一體，例如圖7中以一體的方式展現，當然不限於此，導電漿料柱130、導電跡線136和再分佈接合焊盤138也可以分開成型。導電漿料柱130、導電跡線136和再分佈接合焊盤138構成再分佈層結構300。
如第8圖所示，提供一種在其上形成具有接合焊盤122的半導體裸片120。儘管在該圖中僅示出了一個接合焊盤122，但係應當理解，半導體裸片120可以包括分佈在半導體裸片120的主動表面上的複數個接合焊盤。例如，接合焊盤122可以係鋁焊盤。
根據本發明的一個實施例，鈍化層124例如聚醯亞胺層可以形成在半導體裸片120上，並覆蓋接合焊盤122的周邊。根據本發明的一個實施例，接合焊盤開口124a暴露出接合焊盤122的中心區域。
類似地，如第7圖所示，導電漿料柱130、導電跡線136和再分佈接合焊盤138都印刷到半導體裸片120上。絕緣層140可以形成在半導體裸片120上。根據本發明的一個實施例，絕緣層140可以包括塑封材料，但不限於此。絕緣層140覆蓋導電漿料柱130、導電跡線136和再分佈接合焊盤138。開口140a可以形成在絕緣層140中以部分地暴露出再分佈接合焊盤138。接合線180可以固定在暴露出的再分佈接合焊盤138。
如第9圖所示，提供一種在其上形成具有接合焊盤122的半導體裸片120。儘管在該圖中僅示出了一個接合焊盤122，但係應當理解，半導體裸片120可以包括分佈在半導體裸片120的主動表面上的複數個接合焊盤。例如，接合焊盤122可以係鋁焊盤。
根據本發明的一個實施例，鈍化層124例如聚醯亞胺層可以形成在半導體裸片120上，並覆蓋接合焊盤122的周邊。根據本發明的一個實施例，接合焊盤開口124a暴露出接合焊盤122的中心區域。
如第7圖所示，將導電漿料柱130、導電跡線136和再分佈接合焊盤138都印刷到半導體裸片120上。絕緣層140可以形成在半導體裸片120上。根據本發明的一個實施例，絕緣層140可以包括塑封材料，但不限於此。絕緣層140覆蓋導電漿料柱130、導電跡線136和再分佈接合焊盤138。絕緣層140經過拋光處理以暴露再分佈接合焊盤138。接合線180可固定到暴露的再分佈接合焊盤138。
如第10圖所示，第10圖中的結構和第2圖中的結構之間的不同係圖10中的結構還包括在鈍化層124上印刷的被動元件150。根據本發明的一個實施例，被動元件150可以包括用於作為形成導電漿料柱130、導電跡線136和再分佈接合焊盤138的組合物的銅漿，被動元件150與導電漿料柱130、導電跡線136或再分佈接合焊盤138連接後信號的傳輸更加順暢，干擾更小。根據本發明的一個實施例，被動元件150可以係電阻器、電容器或電感器，但不限於此。此外，再分佈接合焊盤138的側壁與絕緣層140之間可以如第8圖、第9圖和第10圖中所示直接接觸、沒有間隙；再分佈接合焊盤138的側壁與絕緣層140之間也可以未直接接觸、設有間隙，從而在再分佈接合焊盤138因焊接等受到壓力作用，為再分佈接合焊盤138可能產生的形變留出預留空間，避免破壞絕緣層140，保證結構的穩定性和提高生產良率。
參照第11圖至第14圖。第11圖至第14圖係示出根據本發明的一個實施例的用於形成基板400的方法的橫截面示意圖。基板400可以係中介層基板、封裝基板或電路板。
如第11圖所示，在載體410上塗覆一層阻焊層420。隨後，可以通過使用微影製程對阻焊層420進行圖案化，從而形成複數個開口420a。根據本發明的一個實施例，載體410可以係塑膠基板或柔性基板，但不限於此。
如第12圖所示，執行印刷製程以將例如銅漿的導電漿料印刷到開口420a中，從而形成第一電路層430。根據本發明的一個實施例，例如，第一電路層430可以包括球柵陣列（BGA）球焊盤和互連跡線。根據本發明的一個實施例，印刷製程可以包括絲網印刷製程，但不限於此。可以對第一電路層430進行固化處理。
如第13圖所示，之後介電層440塗覆在第一電路層430上。根據本發明的一個實施例，介電層440可以包括聚醯亞胺、ABF（Ajinomoto Buildup Film）等，但不限於此。可以執行微影製程以對介電層440進行圖案化，從而在介電層中形成通孔開口440a。通孔開口440a分別部分地暴露出第一電路層430。
如第14圖所示，執行印刷製程以將例如銅漿的導電漿料印刷到通孔開口440a和介電層440上，從而形成第二電路層450。第二電路層450包括通孔元件450a，通孔元件450a位於通孔開口440a中。第二電路層450還包括位於介電層440上的部分，通孔元件450a用於將第二電路層450的位於介電層440上的部分與第一電路層430電連接。應當理解，參照第11圖至第14圖可以重複的以在中介層基板中形成期望數量的互連層。
請參考第15圖。第15圖係示出根據本發明的一個實施例的用於製造半導體晶片封裝的帶式自動接合（TAB）方法的示意圖。第16圖係示出第15圖中製造的半導體晶片封裝的結構的示意圖。
如第15圖所示，基板400例如中介層基板或封裝基板可以例如通過第11圖至第14圖所示的製程在TAB帶510上預製，TAB帶510可以由聚醯亞胺組成，但不限於此。在第一工位處，倒裝晶片520例如焊料凸塊晶片或裸片可以接合在基板400上。
在晶片放置和接合之後，然後晶片元件在第二工位元進行固化和回流焊製程，以固化基板400的銅漿並回流倒裝晶片520與基板400之間的焊接點。例如，在固化處理中可以使用紅外（IR）回流裝置530，但不限於此。
此後，在第三工位執行模制處理。採用塑封材料540。塑封材料540覆蓋附接的倒裝晶片520和基板400的上表面。塑封材料540可以進行固化處理。塑封材料540可以包括環氧樹脂和二氧化矽填料的混合物，但不限於此。在模制處理之後，將半導體晶片封裝5從TAB帶510上拆下。
如第16圖所示，在從TAB帶510分離半導體晶片封裝5之後，第一電路層430的暴露出的下表面（球形墊）可以由表面處理層（例如Ni/Au層或ASOP層）460覆蓋。隨後，可以在球形墊上形成連接元件例如球柵陣列（BGA）球（未示出）。
第17圖至第20圖係示出根據本發明複數種實施例的用於形成疊層封裝（PoP，package-on-package）的方法的示意圖，其中相同的數字表示相同的元件、區域或層。
如第17圖所示，提供一種底部封裝600。底部封裝600包括安裝在基板610上的第一半導體裸片620。複數個焊球611可以安裝在基板610的下表面上。第一半導體裸片620可被第一塑封材料630包封。貫穿模通孔640可以設置在第一塑封材料630中。
儘管第一半導體裸片620通過圖中的接合線電連接到基板610，但係應當理解，在其他實施例中半導體裸片620可以係倒裝晶片。
隨後，可以執行例如絲網印刷製程或3D印刷製程的印刷製程，以在第一塑封材料630上印刷導電跡線644，例如接合指。此外，導電跡線644也可以印刷到貫穿模通孔640中，印刷在第一塑封材料630的導電跡線644可以電連接到印刷到貫穿模通孔640的導電跡線644，從而連接到基板610上。在印刷製程之後，可以對印刷的導電跡線644進行固化處理。可選地，可以在印刷導電跡線644上設置例如Pt、Ag等的導電層。
然後將第二半導體裸片650安裝在第一塑封材料630上。形成接合線652以將第二半導體裸片650電連接到導電跡線644。隨後，第二半導體裸片650可以被第二塑封材料660包封，從而形成疊層封裝6。
如第18圖所示，同樣地，提供一種底部封裝600。底部封裝600包括安裝在基板610上的第一半導體裸片620。複數個焊球611可以安裝在基板610的下表面上。第一半導體裸片620可由第一塑封材料630包封。貫穿模通孔640可以設置在第一塑封材料630中。
儘管在該圖中通過接合線將第一半導體裸片620電連接到基板610，但係應當理解，在其他實施例中，第一半導體裸片620可以係倒裝晶片。
隨後，可以執行例如絲網印刷製程或3D印刷製程的印刷製程，以在第一塑封材料630上印刷包括接合焊盤644a的導電跡線644。印刷的導電跡線644分別電連接至貫穿模通孔640。在印刷製程之後，可以對印刷的導電跡線644進行固化處理。可選地，可以在印刷導電跡線644上設置例如Pt，Ag等的導電層。
然後以倒裝晶片配置將第二半導體裸片650接合在接合焊盤644a上。隨後，第二半導體裸片650可以由第二塑封材料660包封，由此形成疊層封裝6a。
如第19圖所示，提供一種底部封裝700。底部封裝700包括安裝在基板710上的第一半導體裸片720。複數個焊球711可以安裝在基板710的下表面上。第一半導體裸片720可以由第一塑封材料730包封。
儘管在該圖中通過接合線將第一半導體裸片720電連接到基板710，但係應當理解，在其他實施例中，第一半導體裸片720可以係倒裝晶片。
隨後，可以執行例如絲網印刷製程或3D印刷製程的印刷製程，以在第一塑封材料730的上表面上印刷導電跡線740，例如接合指。導電跡線740可延伸至第一塑封材料730的傾斜側壁。印刷的導電跡線740可以電連接到基板710上或基板710中的導電跡線。在印刷製程之後，可以對印刷的導電跡線740進行固化處理。可選地，可以在印刷導電跡線740上提供例如Pt，Ag等的導電層。
然後將第二半導體裸片750安裝在第一塑封材料730上。形成接合線752以將半導體裸片750電連接到導電跡線740。隨後，第二半導體裸片750可通過第二塑封材料760包封，由此形成疊層封裝7。
如第20圖所示，同樣地，提供一種底部封裝700。底部封裝700包括安裝在基板710上的第一半導體裸片720。複數個焊球711可以安裝在基板710的下表面上。第一半導體裸片720可以由第一塑封材料730包封。
儘管在該圖中通過接合線將第一半導體裸片720電連接到基板710，但係應當理解，在其他實施例中，第一半導體裸片720可以係倒裝晶片。
隨後，可以執行例如絲網印刷製程或3D印刷製程的印刷製程，以在第一塑封材料730的上表面上印刷包括接合焊盤740a的導電跡線740。導電跡線740可延伸至第一塑封材料730的傾斜側壁。印刷的導電跡線740可以電連接到基板710上的導電跡線。在印刷製程之後，印刷的導電跡線740可以進行固化處理。可選地，可以在印刷導電跡線740上提供例如Pt，Ag等的導電層。
然後以倒裝晶片配置將第二半導體裸片750接合在接合焊盤740a上。隨後，第二半導體裸片750可以由第二塑封材料760包封，由此形成疊層封裝7a。
請參見第21圖。第21圖係表示本發明的另一實施例的半導體晶片封裝的示意圖。如第21圖所示，半導體晶片封裝8包括安裝在例如封裝基板的基板810上的半導體裸片820。複數個焊球811可以安裝在基板810的下表面上。半導體裸片820可以由塑封材料830包封。
儘管半導體裸片820通過該圖中的接合線電連接到基板810，但係應當理解，在其他實施例中半導體裸片820可以係倒裝晶片。
複數個散熱部件840嵌入在塑封材料830的上表面中。為了形成散熱部件840，首先，通過雷射器在塑封材料830的上表面中加工形成溝槽，然後將例如銅漿的導電漿料印刷到塑封材料830的上表面上並填充溝槽。在塑封材料830的上表面中形成的溝槽係雷射加工溝槽，並且可以包括各種圖案、字母或數位元，以便顯示如商標或型號某些資訊。
第22圖係表示本發明的另一實施例的基板佈局的局部俯視圖。基板可以係封裝基板、印刷電路板或印刷線路板。
如第22圖所示，在基板90的上表面90a上形成複數個導電跡線。為了簡單起見，該圖中僅示出了兩條導電跡線911和912。導電跡線911和912被阻焊層覆蓋。例如，導電跡線911將通孔921與佈置在阻焊層910外部的接合指931相互連接。導電跡線912可將通孔922與通孔924相互連接。該實施例中，導電跡線912、通孔922和通孔924被阻焊層910覆蓋。阻焊層開口910a形成在阻焊層910中以暴露出通孔923。
導電跡線913設置在阻焊層910上方以將接合指932電連接到通孔923。導電跡線913可以通過使用絲網印刷方法或3D印刷方法印刷在阻焊層910上。導電跡線913可以包括例如銅漿的導電漿料，並且可以進行固化處理。通過提供這種阻焊層上跡線（trace-over-solder mask）的配置，阻焊層910下方的區域950可以省去，以便增加基板90佈線的靈活性。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1、2、5‧‧‧半導體晶片封裝；
10、100、400、610、710、810、90‧‧‧基板；
11、110‧‧‧第一裸片；
12、120‧‧‧第二裸片；
12a‧‧‧突出側邊緣；
16、18、160、180、652、752‧‧‧接合線；
20、200‧‧‧密封劑材料；
104、106、931、932‧‧‧接合指；
120、820‧‧‧半導體裸片；
122、644a、740a‧‧‧接合焊盤；
124‧‧‧鈍化層；
124a‧‧‧接合焊盤開口；
130‧‧‧導電漿料柱；
130a、90a‧‧‧上表面；
131‧‧‧導電層；
132‧‧‧間隙；
136、740、911、912、913‧‧‧導電跡線；
138‧‧‧再分佈接合焊盤；
140‧‧‧絕緣層；
140a、420a‧‧‧開口；
150‧‧‧被動元件；
410‧‧‧載體；
420、910‧‧‧阻焊層；
430‧‧‧第一電路層；
440‧‧‧介電層；
440a‧‧‧通孔開口；
450‧‧‧第二電路層；
450a‧‧‧通孔元件；
460‧‧‧表面處理層；
510‧‧‧TAB帶；
520‧‧‧倒裝晶片；
530‧‧‧紅外回流裝置；
540、830‧‧‧塑封材料；
6、7、7a、8‧‧‧疊層封裝；
600、700‧‧‧底部封裝；
611、711、811‧‧‧焊球；
620、720‧‧‧第一半導體裸片；
630、730‧‧‧第一封塑封材料；
640‧‧‧貫穿模通孔；
650、750‧‧‧第二半導體裸片；
660、760‧‧‧第二封塑封材料；
840‧‧‧散熱部件；
910a‧‧‧阻焊層開口；
921、922、923、924‧‧‧通孔；
950‧‧‧區域。
通過閱讀後續的詳細描述和實施例可以更全面地理解本發明，該實施例參照附圖給出，其中： 第1圖係表示現有的疊層多晶片封裝的截面示意圖； 第2圖至第4圖係示出根據本發明的一個實施例的用於間接式針腳接合製程的接合焊盤上的導電漿料柱的橫截面示意圖； 第5圖和第6圖示出了結合如第1圖所示的導電漿料柱的示例性半導體晶片封裝； 第7圖至第10圖係示出根據本發明的複數種實施例的橫截面示意圖； 第11圖至第14圖係示出根據本發明的一個實施例的用於形成基板的方法的截面示意圖； 第15圖係示出根據本發明的一個實施例的用於製造半導體晶片封裝的帶式自動接合（TAB）方法的示意圖； 第16圖係示出第15圖中製造的半導體晶片封裝的結構的示意圖。 第17圖至第20圖係示出根據本發明的複數種實施例的用於形成疊層封裝（PoP，package-on-package）的方法的示意圖； 第21圖係表示本發明的另一實施例的半導體晶片封裝的示意圖； 第22圖係表示本發明的另一實施例的基板佈局的局部俯視圖。

Claims (20)

  1. 一種半導體晶片封裝，包括： 基板； 安裝在該基板上的半導體裸片，其中該半導體裸片包括設置在該半導體裸片的主動表面上的接合焊盤以及覆蓋該接合焊盤周邊的鈍化層，其中該鈍化層中的接合焊盤開口暴露於該接合焊盤的中心區域； 導電漿料柱，印刷在該接合焊盤暴露的中心區域上；以及 接合線，固定在該導電漿料柱的上表面。
  2. 如申請專利範圍第1項所述之半導體晶片封裝，其中該導電漿料柱完全填滿該接合焊盤開口，其中該導電漿料柱的週邊側壁與該鈍化層直接接觸。
  3. 如申請專利範圍第1項所述之半導體晶片封裝，其中該導電漿料柱不完全填滿該接合焊盤開口，其中該導電漿料柱的週邊側壁不與該鈍化層直接接觸。
  4. 如申請專利範圍第1項所述之半導體晶片封裝，其中還包括塗覆在該導電漿料柱的上表面上的導電層。
  5. 如申請專利範圍第1項所述之半導體晶片封裝，其中還包括在該基板上模制的密封劑材料。
  6. 如申請專利範圍第1項所述之半導體晶片封裝，其中該接合焊盤係鋁接合焊盤。
  7. 一種半導體晶片封裝，包括： 基板； 安裝在該基板上的半導體裸片，其中該半導體裸片包括設置在該半導體裸片的主動表面上的接合焊盤以及覆蓋該接合焊盤周邊的鈍化層，其中該鈍化層中的接合焊盤開口暴露於該接合焊盤的中心區域； 導電漿料柱，印刷在該接合焊盤暴露的中心區域上； 導電跡線，印刷在該鈍化層上並與該導電漿料柱電連接； 再分佈接合焊盤，印刷在該鈍化層上，其中再分佈接合焊盤通過該導電跡線與該導電漿料柱電連接；以及 接合線，固定在該再分佈接合焊盤的上表面。
  8. 如申請專利範圍第7項所述之半導體晶片封裝，其中該導電漿料柱在結構上與該導電跡線和該再分佈接合焊盤成一體。
  9. 如申請專利範圍第7項所述之半導體晶片封裝，其中還包括在該鈍化層上的絕緣層，並且其中該絕緣層覆蓋該導電漿料柱、該導電跡線和該再分佈接合焊盤，並且其中該絕緣層包括開口露出該再分佈接合焊盤。
  10. 如申請專利範圍第9項所述之半導體晶片封裝，其中該絕緣層包括塑封材料。
  11. 如申請專利範圍第7項所述之半導體晶片封裝，其中還包括印刷在該鈍化層上的被動元件。
  12. 一種疊層封裝，包括： 底部封裝，安裝在基板上的第一半導體裸片和安裝在基板的下表面上的複數個焊球，其中該第一半導體裸片由第一塑封材料包封； 導電跡線，印刷在該第一塑封材料上的；以及 第二半導體裸片，安裝在該第一塑封材料上。
  13. 如申請專利範圍第12項所述之疊層封裝，其中該第一半導體裸片通過接合線與該基板電連接。
  14. 如申請專利範圍第12項所述之疊層封裝，其中該第一半導體裸片係倒裝晶片。
  15. 如申請專利範圍第12項所述之疊層封裝，其中該導電跡線包括接合指。
  16. 如申請專利範圍第15項所述之疊層封裝，其中還包括將該第二半導體裸片電連接到該接合指的接合線。
  17. 如申請專利範圍第12項所述之疊層封裝，其中還包括包封該第二半導體裸片的第二塑封材料。
  18. 如申請專利範圍第12項所述之疊層封裝，其中該導電跡線包括在該第一塑封材料上的接合焊盤。
  19. 如申請專利範圍第12項所述之疊層封裝，其中還包括在該第一塑封材料中的貫穿模通孔。
  20. 如申請專利範圍第19項所述之疊層封裝，其中該導電跡線分別與該貫穿模通孔電連接。
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