CN108281408A - 半导体芯片封装和叠层封装 - Google Patents

半导体芯片封装和叠层封装 Download PDF

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Publication number
CN108281408A
CN108281408A CN201711303574.6A CN201711303574A CN108281408A CN 108281408 A CN108281408 A CN 108281408A CN 201711303574 A CN201711303574 A CN 201711303574A CN 108281408 A CN108281408 A CN 108281408A
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China
Prior art keywords
conductive paste
landing pad
semiconductor
stock column
substrate
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CN201711303574.6A
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English (en)
Inventor
蔡宪聪
王学德
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MediaTek Inc
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MediaTek Inc
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Priority claimed from US15/701,456 external-priority patent/US10685943B2/en
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of CN108281408A publication Critical patent/CN108281408A/zh
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Abstract

本发明公开一种半导体芯片封装和叠层封装，半导体芯片封装包括：基板；安装在所述基板上的半导体裸片，其中所述半导体裸片包括设置在所述半导体裸片的有源表面上的接合焊盘以及覆盖所述接合焊盘周边的钝化层，其中所述钝化层中的接合焊盘开口暴露于所述接合焊盘的中心区域；导电浆料柱，印刷在所述接合焊盘暴露的中心区域上；以及接合线，固定在所述导电浆料柱的上表面。由于导电浆料柱的弹性特性，在导电浆料柱上形成接合线后，导电浆料柱会迅速恢复它的形状，可以避免相邻接合焊盘之间的短路，并且可以采用更小的接合焊盘开口和接合焊盘间距。同时施加在顶部裸片的突出侧边缘上的应力可以减少或避免，引线接合工艺的生产量也得到提高。

Description

半导体芯片封装和叠层封装
技术领域
本发明涉及半导体技术领域，更具体地，涉及一种半导体装置和叠层封装。
背景技术
本发明涉及集成电路和半导体芯片封装的相互连接。
集成电路(IC)裸片(die)是形成在例如硅晶片的半导体晶片(semiconductorwafer)上的小器件。这种裸片通常是从晶片上切割下来后连接到基板以形成相互连接的重新分布。之后裸片上的焊盘通过引线接合法与基板上的引线电连接。然后将裸片和接合线用塑封材料(molding compound)包封以形成半导体封装。
通常，包封在半导体封装中的引线在载体内的导体网络中重新分布，并且在半导体封装外部的端子阵列中终止。制造商已经在单个包装中堆叠了两个或更多个裸片。这种器件有时被称为多芯片堆叠封装(stacked multichip package)。
图1中示出了通常地一个的多芯片堆叠封装。在该结构中，第一裸片11安装在基板10上。然后可以将第二裸片12粘合地固定到第一裸片11的上表面，从而形成裸片堆叠结构。当从上方观察时，第二裸片12与第一裸片11部分重叠。然后使用常规的焊线机，通过接合线16和18将第一裸片11和第二裸片12与基板10上各自的接合指(bond finger)电连接。密封剂材料20在基板10上模制，以提供密封盖板。
如本领域已知的那样，间接式针脚接合工艺(stand-off stitch bondingprocess)通常包括将平顶凸块放置在诸如铝焊盘的有源集成电路(IC)焊盘上，然后从基板或封装反向接合到平顶球凸块。然而，这样难以在与突出侧边缘12a相邻的第二裸片12的接合焊盘上形成引线接合18。焊线机引起的应力可能导致第一裸片11和第二裸片12之间的剥离，并降低了生产率。
发明内容
有鉴于此，本发明提供一种半导体装置和叠层封装，使得施加在顶部裸片的突出侧边缘上的应力可以减少或避免，引线接合工艺的生产量也得到提高。
根据本发明的第一方面，公开一种半导体芯片封装，包括：基板；安装在所述基板上的半导体裸片，其中所述半导体裸片包括设置在所述半导体裸片的有源表面上的接合焊盘以及覆盖所述接合焊盘周边的钝化层，其中所述钝化层中的接合焊盘开口暴露于所述接合焊盘的中心区域；导电浆料柱，印刷在所述接合焊盘暴露的中心区域上；以及接合线，固定在所述导电浆料柱的上表面。
根据本发明的第二方面，公开一种半导体芯片封装，包括：基板；安装在所述基板上的半导体裸片，其中所述半导体裸片包括设置在所述半导体裸片的有源表面上的接合焊盘以及覆盖所述接合焊盘周边的钝化层，其中所述钝化层中的接合焊盘开口暴露于所述接合焊盘的中心区域；导电浆料柱，印刷在所述接合焊盘暴露的中心区域上；导电迹线，印刷在所述钝化层上并与所述导电浆料柱电连接；再分布接合焊盘，印刷在所述钝化层上，其中再分布接合焊盘通过所述导电迹线与所述导电浆料柱电连接；以及接合线，固定在所述再分布接合焊盘的上表面。
根据本发明的第三方面，公开一种叠层封装，包括：底部封装，安装在基板上的第一半导体裸片和安装在基板的下表面上的多个焊球，其中所述第一半导体裸片由第一塑封材料包封；导电迹线，印刷在所述第一塑封材料上的；以及第二半导体裸片，安装在所述第一塑封材料上。
本发明提供的半导体芯片封装由于半导体裸片包括设置在有源表面上的接合焊盘以及覆盖接合焊盘周边的钝化层，钝化层中的接合焊盘开口暴露于接合焊盘的中心区域，以及印刷在所述接合焊盘暴露的中心区域上的导电浆料柱，固定在导电浆料柱的上表面的接合线。由于导电浆料柱的弹性特性，在导电浆料柱上形成接合线后，导电浆料柱会迅速恢复它的形状，可以避免相邻接合焊盘之间的短路，并且可以采用更小的接合焊盘开口和接合焊盘间距。同时施加在顶部裸片的突出侧边缘上的应力可以减少或避免，引线接合工艺的生产量也得到提高。
在阅读了随后以不同附图展示的优选实施例的详细说明之后，本发明的这些和其它目标对本领域普通技术人员来说无疑将变得明显。
附图说明
附图以提供对本发明的进一步理解，并且并入并构成本说明书的一部分。附图示出了本发明的实施例，并与说明书一起用于解释本发明的原理。在图中：
图1是表示现有的叠层多芯片封装的截面示意图；
图2至图4是示出根据本发明的一个实施例的用于间接式针脚接合工艺的接合焊盘上的导电浆料柱的横截面示意图；
图5和图6示出了结合如图1所示的导电浆料柱的示例性半导体芯片封装；
图7至图10是示出根据本发明的多种实施例的横截面示意图；
图11至图14是示出根据本发明的一个实施例的用于形成基板的方法的截面示意图；
图15是示出根据本发明的一个实施例的用于制造半导体芯片封装的带式自动接合(TAB)方法的示意图；
图16是示出图15中制造的半导体芯片封装的结构的示意图。
图17至图20是示出根据本发明的多种实施例的用于形成叠层封装(PoP，package-on-package)的方法的示意图；
图21是表示本发明的另一实施例的半导体芯片封装的示意图；
图22是表示本发明的另一实施例的基板布局的局部俯视图。
具体实施方式
在说明书和随后的权利要求书中始终使用特定术语来指代特定组件。正如本领域技术人员所认识到的，制造商可以用不同的名称指代组件。本文件无意于区分那些名称不同但功能相同的组件。在以下的说明书和权利要求中，术语“包含”和“包括”被用于开放式类型，因此应当被解释为意味着“包含，但不限于...”。此外，术语“耦合”旨在表示间接或直接的电连接。因此，如果一个设备耦合到另一设备，则该连接可以是直接电连接，或者经由其它设备和连接的间接电连接。
对这些实施例进行了详细的描述是为了使本领域的技术人员能够实施这些实施例，并且应当理解，在不脱离本发明的精神和范围情况下，可以利用其他实施例进行机械、化学、电气和程序上的改变。因此，以下详细描述并非是限制性的，并且本发明的实施例的范围仅由所附权利要求限定。
请参考图2至图4。图2至图4是示出根据本发明的一个实施例的用于间接式针脚接合工艺的接合焊盘上的导电浆料柱的横截面示意图。如图2和如图3所示，提供一种半导体裸片120，半导体裸片120上具有接合焊盘122。尽管在该图中仅示出了一个焊盘122，但是应当理解的是半导体裸片120可以包括分布在半导体裸片120的有源表面上的多个接合焊盘。例如，接合焊盘122可以是铝焊盘。
根据本发明的一个实施例，钝化层124例如聚酰亚胺层可以形成在半导体裸片120上，并覆盖接合焊盘122的周边。根据本发明的一个实施例，焊盘开口124a暴露出接合焊盘122的中心区域。
根据本发明的一个实施例，导电浆料柱130印刷在接合焊盘122的暴露的中心区域上。例如，导电浆料柱130可以包括铜浆，铜材质导电性能优良，可以保证信号传输的稳定，但不限于此。根据本发明的一个实施例，导电浆料柱130可以通过使用丝网印刷工艺形成。根据本发明的一个实施例，导电浆料柱130可以通过使用3D印刷工艺形成。导电浆料柱用作缓冲剂以防止铝挤出。
与传统的间接式针脚焊接工艺中形成的常规平顶球凸块相比，导电浆料柱130具有更平坦的上表面130a。导电浆料柱130较平坦的上表面130a为半导体封装提供了更高的可靠性和更好的性能。
根据本发明的一个实施例，例如，铜浆可以包括环氧树脂，例如热固性环氧树脂，并且铜粉或银包铜球作为填料，但不限于此。铜在氧化后会影响信号传输，使用银包铜球可以有效防止铜的氧化，从而保证信号传输的稳定。在导电浆料柱130印刷在接合焊盘122上之后，可以对导电浆料柱130进行固化处理。根据本发明的一个实施例，导电浆料柱130可以通过热处理或紫外(UV)光固化。
可选地，可以对导电浆料柱130的上表面130a进行蚀刻工艺以暴露出更多的金属填料，从而降低接触电阻。根据本发明的另一个实施例，可以将具有低电阻的导电层131(例如Pt或Au)涂覆在导电浆料柱130的上表面130a上。
如图2所示，导电浆料柱130可以完全填满接合焊盘开口124a。图2中，导电浆料柱130的周边侧壁与钝化层124直接接触。或者，如图3所示，导电浆料柱130不完全填满接合焊盘开口124a。在图3中，导电浆料柱130的周边侧壁不与钝化层124直接接触。在导电浆料柱130的周边侧壁和钝化层124之间可以形成间隙132。当如图2所示导电浆料柱130的周边侧壁与钝化层124直接接触时，更加方便生产加工，加工时可将钝化层124直接覆盖在基板120上及导电浆料柱130的周边，从而加工效率更高。如图3所示，在将接合线等焊接在导电浆料柱130上时，导电浆料柱130受到压力作用，可能会产生形变，从而使导电浆料柱130的侧壁扩大，因此当导电浆料柱130的周边侧壁不与钝化层124直接接触时，可预留出供侧壁扩大的余量，从而避免因侧壁的挤压而造成钝化层124变形等意外影响，保证结构的稳定性和提高生产良率。
图4示出了在将接合线接合在其上之后的导电浆料柱130。如图4所示，可以执行例如间接式针脚接合工艺的引线接合工艺，以将接合线180固定在导电浆料柱130的上表面130a上。根据本发明的一个实施例，导电浆料柱130代替在常规的间接式针脚接合工艺中形成的常规平顶球凸块。此外，在引线接合工艺之前，可以将导电浆料柱130印刷在半导体裸片120上。因此，图1中显示的施加在顶部裸片的突出侧边缘上的应力可以减少或避免。引线接合工艺的生产量(UPH或unit per hour)也得到提高。
由于导电浆料柱130的弹性特性，导电浆料柱130能够在形成接合线180后迅速恢复它的形状。可以避免相邻接合焊盘之间的短路。因此，可以采用更小的接合焊盘开口和接合焊盘间距。
图5示出了结合如图4所示的导电浆料柱的示例性半导体芯片封装1，其中相同的数字表示相同的元件、区域或层。如图5所示，半导体芯片封装1包括安装在第一裸片110上的第二裸片120。第二裸片120粘合地固定到第一裸片110的上表面，从而产生堆叠的裸片结构。当从上方观察时，第二裸片120与第一裸片110部分重叠。在基板100上模制密封剂材料200，例如环氧模塑料，以提供密封剂盖板。
使用焊线机，形成接合线160和180，以将第一裸片110和第二裸片120电连接到基板100上相应的接合指104和106。基板100可以是封装基板，但不限于此。接合线180可以固定到基板100上的接合指104，然后反向接合到第二裸片120上的导电浆料柱130。
图6示出了结合如图4所示的导电浆料柱的示例性半导体芯片封装2。其中相同的数字表示相同的元件、区域或层。如图6所示，半导体芯片封装2包括安装在基板100上的单个裸片120。使用焊线机，形成接合线180以将裸片120电连接到基板100上各自的接合指104。基板100可以是封装基板，但不限于此。接合线180可以固定到基板100上的接合104，然后反向接合到裸片120上的导电浆料柱130。
应当理解，图2和图6所示的封装结构只是为了说明的目的。在不脱离本发明的精神或范围的情况下，可以采用其他包装结构。
请参考图7至图10。图7至图10是示出根据本发明的多种实施例的横截面示意图，其中相同的数字表示相同的元件、区域或层。图7至图10所示的再分布层(RDL)结构可以适用于图5和图6所示的半导体芯片封装。
如图7所示，同样地，提供了一种在其上形成具有接合焊盘122的半导体裸片120。尽管在该图中仅示出了一个焊盘122，但是应当理解，半导体裸片120可以包括分布在半导体裸片120的有源表面上的多个接合焊盘。例如，接合焊盘122可以是铝焊盘。
根据本发明的一个实施例，钝化层124例如聚酰亚胺层可以形成在半导体裸片120上并覆盖接合焊盘122的周边。根据本发明的一个实施例，接合焊盘开口124a暴露出接合焊盘122的中心区域。
根据本发明的一个实施例，导电浆料柱130印刷在接合焊盘122的暴露的中心区域上。例如，导电浆料柱130可以包括铜浆，但不限于此。根据本发明的一个实施例，导电浆料柱130可以通过使用丝网印刷工艺形成。根据本发明的另一个实施例，导电浆料柱130可以通过使用3D印刷工艺形成。
根据本发明的一个实施例，导电迹线136印刷在钝化层124上。导电迹线136与导电浆料柱130电连接。导电迹线136可以包括铜浆，但不限于此。根据本发明的一个实施例，可以通过使用相同的印刷工艺来印刷导电浆料柱130和导电迹线136。
根据本发明的一个实施例，再分布接合焊盘138也印刷在钝化层124上。再分布接合焊盘138通过导电迹线136电连接到导电浆料柱130。再分布的接合焊盘138比导电迹线136厚。
根据本发明的一个实施例，可以通过使用相同的印刷工艺来印刷导电浆料柱130、导电迹线136和再分布接合焊盘138，并且可以进行固化处理。导电浆料柱130在结构上与导电迹线136和再分布接合焊盘138成一体，例如图7中以一体的方式展现，当然不限于此，导电浆料柱130、导电迹线136和再分布接合焊盘138也可以分开成型。导电浆料柱130、导电迹线136和再分布接合焊盘138构成再分布层结构300。
如图8所示，提供一种在其上形成具有接合焊盘122的半导体裸片120。尽管在该图中仅示出了一个焊盘122，但是应当理解，半导体裸片120可以包括分布在半导体裸片120的有源表面上的多个接合焊盘。例如，接合焊盘122可以是铝焊盘。
根据本发明的一个实施例，钝化层124例如聚酰亚胺层可以形成在半导体裸片120上，并覆盖接合焊盘122的周边。根据本发明的一个实施例，焊盘开口124a暴露出接合焊盘122的中心区域。
类似地，如图7所示，导电浆料柱130、导电迹线136和再分布接合焊盘138都印刷到半导体裸片120上。绝缘层140可以形成在半导体裸片120上。根据本发明的一个实施例，绝缘层140可以包括塑封材料，但不限于此。绝缘层140覆盖导电浆料柱130、导电迹线136和再分布接合焊盘138。开口140a可以形成在绝缘层140中以部分地暴露出再分布接合焊盘138。接合线180可以固定在暴露出的再分布接合焊盘138。
如图9所示，提供一种在其上形成具有接合焊盘122的半导体裸片120。尽管在该图中仅示出了一个焊盘122，但是应当理解，半导体裸片120可以包括分布在半导体裸片120的有源表面上的多个接合焊盘。例如，接合焊盘122可以是铝焊盘。
根据本发明的一个实施例，钝化层124例如聚酰亚胺层可以形成在半导体裸片120上，并覆盖接合焊盘122的周边。根据本发明的一个实施例，焊盘开口124a暴露出接合焊盘122的中心区域。
如图7所示，将导电浆料柱130、导电迹线136和再分布接合焊盘138都印刷到半导体裸片120上。绝缘层140可以形成在半导体裸片120上。根据本发明的一个实施例，绝缘层140可以包括塑封材料，但不限于此。绝缘层140覆盖导电浆料柱130、导电迹线136和再分布接合焊盘138。绝缘层140经过抛光处理以暴露再分布接合焊盘138。接合线180可固定到暴露的再分布接合焊盘138。
如图10所示，图10中的结构和图2中的结构之间的不同是图10中的结构还包括在钝化层124上印刷的无源元件150。根据本发明的一个实施例，无源元件150可以包括用于作为形成导电浆料柱130、导电迹线136和再分布接合焊盘138的组合物的铜浆，无源元件150与导电浆料柱130、导电迹线136或再分布接合焊盘138连接后信号的传输更加顺畅，干扰更小。根据本发明的一个实施例，无源元件150可以是电阻器、电容器或电感器，但不限于此。此外，再分布接合焊盘138的侧壁与绝缘层140之间可以如图8、图9和图10中所示直接接触、没有间隙；再分布接合焊盘138的侧壁与绝缘层140之间也可以未直接接触、设有间隙，从而在再分布接合焊盘138因焊接等受到压力作用，为再分布接合焊盘138可能产生的形变留出预留空间，避免破坏绝缘层140，保证结构的稳定性和提高生产良率。
参照图11至图14。图11至图14是示出根据本发明的一个实施例的用于形成基板400的方法的横截面示意图。基板400可以是中介层基板、封装基板或电路板。
如图11所示，在载体410上涂覆一层阻焊层420。随后，可以通过使用光刻工艺对阻焊层420进行图案化，从而形成多个开口420a。根据本发明的一个实施例，载体410可以是塑料基板或柔性基板，但不限于此。
如图12所示，执行印刷工艺以将例如铜浆的导电浆料印刷到开口420a中，从而形成第一电路层430。根据本发明的一个实施例，例如，第一电路层430可以包括球栅阵列(BGA)球焊盘和互连迹线。根据本发明的一个实施例，印刷工艺可以包括丝网印刷工艺，但不限于此。可以对第一电路层430进行固化处理。
如图13所示，之后介电层440涂覆在第一电路层430上。根据本发明的一个实施例，介电层440可以包括聚酰亚胺，ABF(Ajinomoto Buildup Film)等，但不限于此。可以执行光刻工艺以对介电层440进行图案化，从而在介电层中形成通孔开口440a。通孔开口440a分别部分地暴露出第一电路层430。
如图14所示，执行印刷工艺以将例如铜浆的导电浆料印刷到通孔开口440a和介电层440上，从而形成第二电路层450。第二电路层450包括通孔元件450a，通孔元件450a位于通孔开口440a中。第二电路层450还包括位于介电层440上的部分，通孔元件450a用于将第二电路层450的位于介电层440上的部分与第一电路层430电连接。应当理解，参照图11至图14可以重复的以在中介层基板中形成期望数量的互连层。
请参考图15。图15是示出根据本发明的一个实施例的用于制造半导体芯片封装的带式自动接合(TAB)方法的示意图。图16是示出图15中制造的半导体芯片封装的结构的示意图。
如图15所示，基板400例如中介层基板或封装基板可以例如通过图11至图14所示的工艺在TAB带510上预制，TAB带510可以由聚酰亚胺组成，但不限于此。在第一工位处，倒装芯片520例如焊料凸块芯片或裸片可以接合在基板400上。
在芯片放置和接合之后，然后芯片组件在第二工位进行固化和回流焊工艺，以固化基板400的铜浆并回流倒装芯片520与基板400之间的焊接点。例如，在固化处理中可以使用红外(IR)回流装置530，但不限于此。
此后，在第三工位执行模制处理。采用塑封材料540。塑封材料540覆盖附接的倒装芯片520和基板400的上表面。塑封材料540可以进行固化处理。塑封材料540可以包括环氧树脂和二氧化硅填料的混合物，但不限于此。在模制处理之后，将半导体芯片封装5从TAB带510上拆下。
如图16所示，在从TAB带510分离半导体芯片封装5之后，第一电路层430的暴露出的下表面(球形垫)可以由表面处理层(例如Ni/Au层或ASOP层)460覆盖。随后，可以在球形垫上形成连接元件例如球栅阵列(BGA)球(未示出)。
图17至图20是示出根据本发明多种实施例的用于形成叠层封装(PoP，package-on-package)的方法的示意图，其中相同的数字表示相同的元件、区域或层。
如图17所示，提供一种底部封装600。底部封装600包括安装在基板610上的第一半导体裸片620。多个焊球611可以安装在基板610的下表面上。第一半导体裸片620可被第一塑封材料630包封。贯穿模通孔640可以设置在第一塑封材料630中。
尽管第一半导体裸片620通过图中的接合线电连接到基板610，但是应当理解，在其他实施例中半导体裸片620可以是倒装芯片。
随后，可以执行例如丝网印刷工艺或3D印刷工艺的印刷工艺，以在第一塑封材料630上印刷导电迹线644，例如接合指。此外，导电迹线644也可以印刷到贯穿模通孔640中，印刷在第一塑封材料630的导电迹线644可以电连接到印刷到贯穿模通孔640的导电迹线644，从而连接到基板610上。在印刷工艺之后，可以对印刷的导电迹线644进行固化处理。可选地，可以在印刷导电迹线644上设置例如Pt，Ag等的导电层。
然后将第二半导体裸片650安装在第一塑封材料630上。形成接合线652以将第二半导体裸片650电连接到导电迹线644。随后，第二半导体裸片650可以被第二塑封材料660包封，从而形成叠层封装6。
如图18所示，同样地，提供一种底部封装600。底部封装600包括安装在基板610上的第一半导体裸片620。多个焊球611可以安装在基板610的下表面上。第一半导体裸片620可由第一塑封材料630包封。贯穿模通孔640可以设置在第一塑封材料630中。
尽管在该图中通过接合线将第一半导体裸片620电连接到基板610，但是应当理解，在其他实施例中，第一半导体裸片620可以是倒装芯片。
随后，可以执行例如丝网印刷工艺或3D印刷工艺的印刷工艺，以在第一塑封材料630上印刷包括接合焊盘644a的导电迹线644。印刷的导电迹线644分别电连接至贯穿模通孔640。在印刷工艺之后，可以对印刷的导电迹线644进行固化处理。可选地，可以在印刷导电迹线644上设置例如Pt，Ag等的导电层。
然后以倒装芯片配置将第二半导体裸片650接合在接合焊盘644a上。随后，第二半导体裸片650可以由第二塑封材料660包封，由此形成叠层封装6a。
如图19所示，提供一种底部封装700。底部封装700包括安装在基板710上的第一半导体裸片720。多个焊球711可以安装在基板710的下表面上。第一半导体裸片720可以由第一塑封材料730包封。
尽管在该图中通过接合线将第一半导体裸片720电连接到基板710，但是应当理解，在其他实施例中，第一半导体裸片720可以是倒装芯片。
随后，可以执行例如丝网印刷工艺或3D印刷工艺的印刷工艺，以在第一塑封材料730的上表面上印刷导电迹线740，例如接合指。导电迹线740可延伸至第一塑封材料730的倾斜侧壁。印刷的导电迹线740可以电连接到基板710上或基板710中的导电迹线。在印刷工艺之后，可以对印刷的导电迹线740进行固化处理。可选地，可以在印刷导电迹线740上提供例如Pt，Ag等的导电层。
然后将第二半导体裸片750安装在第一塑封材料730上。形成接合线752以将半导体裸片750电连接到导电迹线740。随后，第二半导体裸片750可通过第二塑封材料760包封，由此形成叠层封装7。
如图20所示，同样地，提供一种底部封装700。底部封装700包括安装在基板710上的第一半导体裸片720。多个焊球711可以安装在基板710的下表面上。第一半导体裸片720可以由第一塑封材料730包封。
尽管在该图中通过接合线将第一半导体裸片720电连接到基板710，但是应当理解，在其他实施例中，第一半导体裸片720可以是倒装芯片。
随后，可以执行例如丝网印刷工艺或3D印刷工艺的印刷工艺，以在第一塑封材料730的上表面上印刷包括接合焊盘740a的导电迹线740。导电迹线740可延伸至第一塑封材料730的倾斜侧壁。印刷的导电迹线740可以电连接到基板710上的导电迹线。在印刷工艺之后，印刷的导电迹线740可以进行固化处理。可选地，可以在印刷导电迹线740上提供例如Pt，Ag等的导电层。
然后以倒装芯片配置将第二半导体裸片750接合在接合焊盘740a上。随后，第二半导体裸片750可以由第二塑封材料760包封，由此形成叠层封装7a。
请参见图21。图21是表示本发明的另一实施例的半导体芯片封装的示意图。如图21所示，半导体芯片封装8包括安装在例如封装基板的基板810上的半导体裸片820。多个焊球811可以安装在基板810的下表面上。半导体裸片820可以由塑封材料830包封。
尽管半导体裸片820通过该图中的接合线电连接到基板810，但是应当理解，在其他实施例中半导体裸片820可以是倒装芯片。
多个散热部件840嵌入在塑封材料830的上表面中。为了形成散热部件840，首先，通过激光器在塑封材料830的上表面中加工形成沟槽，然后将例如铜浆的导电浆料印刷到塑封材料830的上表面上并填充沟槽。在塑封材料830的上表面中形成的沟槽是激光加工沟槽，并且可以包括各种图案、字母或数字，以便显示如商标或型号某些信息。
图22是表示本发明的另一实施例的基板布局的局部俯视图。基板可以是封装基板、印刷电路板或印刷线路板。
如图22所示，在基板90的上表面90a上形成多个导电迹线。为了简单起见，该图中仅示出了两条导电迹线911和912。导电迹线911和912被阻焊层覆盖。例如，导电迹线911将通孔921与布置在焊料掩模910外部的接合指931相互连接。导电迹线912可将通孔922与通孔924相互连接。该实施例中，导电迹线912、通孔922和通孔924被阻焊层910覆盖。阻焊层开口910a形成在阻焊层910中以暴露出通孔923。
导电迹线913设置在阻焊层910上方以将接合指932电连接到通孔923。导电迹线913可以通过使用丝网印刷方法或3D印刷方法印刷在阻焊层910上。导电迹线913可以包括例如铜浆的导电浆料，并且可以进行固化处理。通过提供这种阻焊层上迹线(trace-over-solder mask)的配置，阻焊层910下方的区域950可以省去，以便增加基板90布线的灵活性。
本领域的技术人员将容易地观察到，在保持本发明教导的同时，可以做出许多该装置和方法的修改和改变。因此，上述公开内容应被解释为仅由所附权利要求书的界限和范围所限制。

Claims (20)

1.一种半导体芯片封装，其特征在于，包括：
基板；
安装在所述基板上的半导体裸片，其中所述半导体裸片包括设置在所述半导体裸片的有源表面上的接合焊盘以及覆盖所述接合焊盘周边的钝化层，其中所述钝化层中的接合焊盘开口暴露于所述接合焊盘的中心区域；
导电浆料柱，印刷在所述接合焊盘暴露的中心区域上；以及
接合线，固定在所述导电浆料柱的上表面。
2.根据权利要求1所述的半导体芯片封装，其特征在于，所述导电浆料柱完全填满所述接合焊盘开口，其中所述导电浆料柱的外围侧壁与所述钝化层直接接触。
3.根据权利要求1所述的半导体芯片封装，其特征在于，所述导电浆料柱不完全填满所述接合焊盘开口，其中所述导电浆料柱的外围侧壁不与所述钝化层直接接触。
4.根据权利要求1所述的半导体芯片封装，其特征在于，还包括涂覆在所述导电浆料柱的上表面上的导电层。
5.根据权利要求1所述的半导体芯片封装，其特征在于，还包括在所述基板上模制的密封剂材料。
6.根据权利要求1所述的半导体芯片封装，其特征在于，所述接合焊盘是铝接合焊盘。
7.一种半导体芯片封装，其特征在于，包括：
基板；
安装在所述基板上的半导体裸片，其中所述半导体裸片包括设置在所述半导体裸片的有源表面上的接合焊盘以及覆盖所述接合焊盘周边的钝化层，其中所述钝化层中的接合焊盘开口暴露于所述接合焊盘的中心区域；
导电浆料柱，印刷在所述接合焊盘暴露的中心区域上；
导电迹线，印刷在所述钝化层上并与所述导电浆料柱电连接；
再分布接合焊盘，印刷在所述钝化层上，其中再分布接合焊盘通过所述导电迹线与所述导电浆料柱电连接；以及
接合线，固定在所述再分布接合焊盘的上表面。
8.根据权利要求7所述的半导体芯片封装，其特征在于，所述导电浆料柱在结构上与所述导电迹线和所述再分布接合焊盘成一体。
9.根据权利要求7所述的半导体芯片封装，其特征在于，还包括在所述钝化层上的绝缘层，并且其中所述绝缘层覆盖所述导电浆料柱、所述导电迹线和所述再分布接合焊盘，并且其中所述绝缘层包括开口露出所述再分布接合焊盘。
10.根据权利要求9所述的半导体芯片封装，其特征在于，所述绝缘层包括塑封材料。
11.根据权利要求7所述的半导体芯片封装，其特征在于，还包括印刷在所述钝化层上的无源元件。
12.一种叠层封装，其特征在于，包括：
底部封装，安装在基板上的第一半导体裸片和安装在基板的下表面上的多个焊球，其中所述第一半导体裸片由第一塑封材料包封；
导电迹线，印刷在所述第一塑封材料上的；以及
第二半导体裸片，安装在所述第一塑封材料上。
13.根据权利要求12所述的叠层封装，其特征在于，所述第一半导体裸片通过接合线与所述基板电连接。
14.根据权利要求12所述的叠层封装，其特征在于，所述第一半导体裸片是倒装芯片。
15.根据权利要求12所述的叠层封装，其特征在于，所述导电迹线包括接合指。
16.根据权利要求15所述的叠层封装，其特征在于，还包括将所述第二半导体裸片电连接到所述接合指的接合线。
17.根据权利要求12所述的叠层封装，其特征在于，还包括包封所述第二半导体裸片的第二塑封材料。
18.根据权利要求12所述的叠层封装，其特征在于，所述导电迹线包括在所述第一塑封材料上的接合焊盘。
19.根据权利要求12所述的叠层封装，其特征在于，还包括在所述第一塑封材料中的贯穿模通孔。
20.根据权利要求19所述的叠层封装，其特征在于，所述导电迹线分别与所述贯穿模通孔电连接。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109872982A (zh) * 2019-03-08 2019-06-11 东莞记忆存储科技有限公司 半导体多层晶粒堆叠模块及其焊接方法
CN112420656A (zh) * 2019-08-20 2021-02-26 爱思开海力士有限公司 包括层叠的半导体芯片的半导体封装件及其制造方法
CN113471176A (zh) * 2020-06-15 2021-10-01 台湾积体电路制造股份有限公司 封装结构及其形成方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10685943B2 (en) 2015-05-14 2020-06-16 Mediatek Inc. Semiconductor chip package with resilient conductive paste post and fabrication method thereof
US10978419B1 (en) * 2019-10-14 2021-04-13 Nanya Technology Corporation Semiconductor package and manufacturing method thereof
US11444019B2 (en) 2020-04-06 2022-09-13 Qualcomm Incorporated Package comprising a substrate with interconnect routing over solder resist layer and an integrated device coupled to the substrate and method for manufacturing the package
TWI822016B (zh) * 2022-04-28 2023-11-11 元太科技工業股份有限公司 顯示裝置
TW202407913A (zh) * 2022-08-08 2024-02-16 海華科技股份有限公司 晶片封裝結構及其封裝模組

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08107123A (ja) * 1994-10-04 1996-04-23 Hitachi Ltd 半導体集積回路装置の製造方法、その製造装置および半導体集積回路装置
US7633765B1 (en) * 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
CN103178054A (zh) * 2011-12-22 2013-06-26 三星电子株式会社 包括堆叠半导体芯片和再分布层的半导体封装件
US8643185B2 (en) * 2007-10-10 2014-02-04 Renesas Electronics Corporation Semiconductor apparatus, manufacturing method of semiconductor apparatus, and joint material
US20160064344A1 (en) * 2014-08-28 2016-03-03 Renesas Electronics Corporation Semiconductor device and its manufacturing method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0252443A (ja) * 1988-08-17 1990-02-22 Mitsubishi Electric Corp ワイヤボンディング方法
US7176580B1 (en) * 2003-10-24 2007-02-13 Joseph Fjelstad Structures and methods for wire bonding over active, brittle and low K dielectric areas of an IC chip
KR20100124161A (ko) * 2009-05-18 2010-11-26 주식회사 하이닉스반도체 반도체 패키지의 제조방법
US20120228768A1 (en) * 2011-03-07 2012-09-13 Reza Argenty Pagaila Integrated circuit packaging system using b-stage polymer and method of manufacture thereof
KR20140064053A (ko) * 2012-11-19 2014-05-28 삼성전자주식회사 재배선 층을 갖는 반도체 패키지

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08107123A (ja) * 1994-10-04 1996-04-23 Hitachi Ltd 半導体集積回路装置の製造方法、その製造装置および半導体集積回路装置
US7633765B1 (en) * 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US8643185B2 (en) * 2007-10-10 2014-02-04 Renesas Electronics Corporation Semiconductor apparatus, manufacturing method of semiconductor apparatus, and joint material
CN103178054A (zh) * 2011-12-22 2013-06-26 三星电子株式会社 包括堆叠半导体芯片和再分布层的半导体封装件
US20160064344A1 (en) * 2014-08-28 2016-03-03 Renesas Electronics Corporation Semiconductor device and its manufacturing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109872982A (zh) * 2019-03-08 2019-06-11 东莞记忆存储科技有限公司 半导体多层晶粒堆叠模块及其焊接方法
CN112420656A (zh) * 2019-08-20 2021-02-26 爱思开海力士有限公司 包括层叠的半导体芯片的半导体封装件及其制造方法
CN113471176A (zh) * 2020-06-15 2021-10-01 台湾积体电路制造股份有限公司 封装结构及其形成方法
CN113471176B (zh) * 2020-06-15 2024-02-23 台湾积体电路制造股份有限公司 封装结构及其形成方法

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