JP5529494B2 - リードフレーム - Google Patents
リードフレーム Download PDFInfo
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- JP5529494B2 JP5529494B2 JP2009245603A JP2009245603A JP5529494B2 JP 5529494 B2 JP5529494 B2 JP 5529494B2 JP 2009245603 A JP2009245603 A JP 2009245603A JP 2009245603 A JP2009245603 A JP 2009245603A JP 5529494 B2 JP5529494 B2 JP 5529494B2
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- lead frame
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- 239000004065 semiconductor Substances 0.000 claims description 59
- 239000000463 material Substances 0.000 claims description 28
- 239000011347 resin Substances 0.000 claims description 24
- 229920005989 resin Polymers 0.000 claims description 24
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000007747 plating Methods 0.000 description 31
- 239000013067 intermediate product Substances 0.000 description 17
- 238000000034 method Methods 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
- H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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Description
特許文献1の半導体装置の製造方法では、まず、リードフレーム材の上面側のワイヤボンディング部、外枠の一部又は全部、及び下面側の外部接続端子部に貴金属めっき層を形成し、リードフレーム材の上面側のハーフエッチング加工を行っている。そして、半導体素子を搭載した後、ワイヤボンディングを行い、上面側を樹脂封止し、次に、下面側のエッチング加工を行って、外部接続端子部を突出及び独立させ、半導体装置を製造している。
本発明は、かかる事情に鑑みてなされるもので、外枠の樹脂からの剥離を防止するリードフレームを提供することを目的とする。
前記外枠の内側は平面視して凹凸形状となり、しかも、該外枠に形成された凹凸形状は、前記回路パターン群に向かって延設されたT字形状の内側突出部と、外側に向かって形成されたT字形状の窪み部を備え、
かつ、前記外枠の一部を上面側から前記樹脂で封止する領域は、前記外側に向かって形成されたT字形状の窪み部の更に外側まであり、前記樹脂と前記外枠との接合を強化する。
図1、図2、図6に示すように、本発明の一実施の形態に係るリードフレーム10は、銅又は銅合金からなるリードフレーム材11に第1回目のエッチングにより、半導体素子搭載領域12の周囲に複数の上側端子部13を有する単位リードフレーム14を多列に備えた回路パターン群15と、回路パターン群15を隙間を有して囲む外枠16とを形成した後、単位リードフレーム14毎に半導体素子17を搭載し必要な配線を行い、更に半導体素子17が搭載された回路パターン群15の全体と、外枠16の一部とを上面側から樹脂18で封止し、更に下面側から第2回目のエッチングをして回路パターン群15の上側端子部13に連接する下側端子部19を形成して半導体装置20を製造するために用いられる。
そして、横並びに配置された複数(本実施の形態では4つ)のリードフレーム10を有して、リードフレーム集合体21が形成されている。
更に、外枠16の内側直線部(隣り合う内隅領域22〜25の間の領域)には、それぞれ回路パターン群15に向かって延設された複数(例えば3〜15個の範囲で、本実施の形態では6個)のT字状の内側突出部26と、外側に向かって形成された複数(例えば3〜15個の範囲で、本実施の形態では7個)のT字形状の窪み部27が設けられている。
このように、内隅領域22〜25、内側突出部26及び窪み部27を設けることにより、外枠16の内側は凹凸形状となり、リードフレ−ム材11の露出した部分の表面積が広くなるので、樹脂18とリードフレーム材11は、接触面積が増え、密着性が向上する。
内側突出部26と窪み部27は、交互に形成され、外枠16の内側は、内側突出部26、窪み部27、及び階段状の内隅領域22〜25によって、凹凸形状となっている。
めっき層28は、リードフレーム材11の上側の表面に下地めっきの一例であるNiめっきをなし、その上に貴金属めっきとしてPdめっき、更に、その上にAuめっきをなして形成することや、下地Niめっきの上にAuめっきをなした2層構造で形成することができる。
また、めっき層29は、リードフレーム材11の下側の表面に下地めっきの一例であるNiめっきをなし、その下にPdめっき、更に、その下にAuめっきをなして形成することや、Niめっき又はSnめっきの1層構造により形成することや、あるいは下地Niめっきの下にAuめっきをなして2層構造により形成することができる。
単位リードフレーム14には、中央に半導体素子17を搭載する半導体素子搭載領域12が設けられ、半導体素子搭載領域12の周囲に、半導体素子17と電気的に接続される複数の上側端子部13が配置されている。
上側端子部13は、上向きに突出するリードフレーム材11によって形成されている。
また、リードフレーム材11の上側端子部13が形成された領域の上面及び下面には、めっき層28、29がそれぞれ設けられている(図5(G)参照)。
ここで、めっきは、一般的に、樹脂との接着(密着)強度が弱いが、階段状の内隅領域22〜25、内側突出部26、及び窪み部27を設けて、外枠16の内側を凹凸形状にすることで、外枠16の内側側面に露出したリードフレーム材11の表面積が広くなり、樹脂18とリードフレーム材11との接触面積を増加させ、樹脂18と外枠16の密着性を強化して、外枠16の樹脂18からの剥離を抑制できることが実験によって確認された。
また、半導体装置の中間製品35を複数(本実施の形態では4つ)連結して、半導体装置の中間製品集合体37が形成されている。
図5(A)〜(C)に示すように、板状のリードフレーム材11の上面及び下面にレジスト膜41、42をそれぞれ形成し、露光及び現像を行って、レジスト膜41、42にそれぞれ複数の開口部43、44を設けると共に、外枠形成領域45の上面及び下面に配置されたレジスト膜41、42の一部を取除く。
なお、開口部43は、上側端子部13の形成領域に、開口部44は、下側端子部19(上側端子部13の下側)及び半導体素子搭載領域12の形成領域にそれぞれ設けられる。
なお、エッチングされるリードフレーム材11の略半分の厚みとは、例えば30〜55%の範囲であり、この範囲は、リードフレーム材11の板厚の変化や、アスペクト比等の影響により生じるエッチングの誤差等からもたらされる。
そして、図5(G)に示すように、リードフレーム材11からレジスト膜46を取除いて、単位リードフレーム14の形成と共に、16個の単位リードフレーム14からなる回路パターン群15と、外枠16とを設けたリードフレーム10が形成される。
これにより、外枠16には、リードフレーム材11が露出した側面を有する内隅領域22〜25、内側突出部26、及び窪み部27が形成される。
このとき、外枠16には、内側側面にリードフレーム材11が露出した内隅領域22〜25、内側突出部26、及び窪み部27が設けられているので、樹脂18とリードフレーム10の密着性は強固になっている。
更に、刃物の一例であるダイサーによって隣り合った各単位リードフレーム14の間及び外枠16と各単位リードフレーム14の間を切断分離して個々の半導体装置20が製造される。なお、1つの単位リードフレーム14につき、1つの半導体装置20が製造される。
例えば、外枠は、内側突出部と窪み部を交互に設けて形成されることに限定されず、内側突出部、あるいは、窪み部を連続して設けてもよく、図7(A)に示すように、内側突出部38のみを設けた外枠40aにすることや、図7(B)に示すように、窪み部39のみを設けた外枠40bにすることができる。
また、外枠の内側4隅に、階段状の内隅領域を設ける代わりに、内側突出部を設けることや、図7(B)に示すように窪み部39を設けてもよい。
そして、内側突出部及び窪み部は、平面視してT字形状でなく、他の形状例えば、矢印形状に形成することもできる。
更に、回路パターン群には、単位リードフレームを一列だけ配置することができる。
そして、めっきの原料については、Ni、Pd、Au、Snを例として挙げたが、その他の耐エッチング性を備えた原料を用いることができる。
Claims (3)
- リードフレーム材に、半導体素子搭載領域の周囲に複数の上側端子部を有する単位リードフレームを一列又は多列に備えた回路パターン群と、該回路パターン群を隙間を有して囲む外枠とを形成した後、前記単位リードフレーム毎に半導体素子を搭載し必要な配線を行い、前記半導体素子が搭載された前記回路パターン群の全体と、前記外枠の一部とを上面側から樹脂で封止し、更に下面側からエッチングをして前記回路パターン群の前記上側端子部に連接する下側端子部を突出及び独立させて半導体装置を製造するために用いるリードフレームであって、
前記外枠の内側は平面視して凹凸形状となり、しかも、該外枠に形成された凹凸形状は、前記回路パターン群に向かって延設されたT字形状の内側突出部と、外側に向かって形成されたT字形状の窪み部を備え、
かつ、前記外枠の一部を上面側から前記樹脂で封止する領域は、前記外側に向かって形成されたT字形状の窪み部の更に外側まであることを特徴とするリードフレーム。 - 請求項1記載のリードフレームにおいて、前記外枠の内側角部にも、平面視して凹凸形状を有することを特徴とするリードフレーム。
- 請求項2記載のリードフレームにおいて、前記内側角部に形成されている凹凸形状は、平面視して階段状となっていることを特徴とするリードフレーム。
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