CN101996958A - 芯片封装体及其制造方法 - Google Patents

芯片封装体及其制造方法 Download PDF

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CN101996958A
CN101996958A CN2010101143150A CN201010114315A CN101996958A CN 101996958 A CN101996958 A CN 101996958A CN 2010101143150 A CN2010101143150 A CN 2010101143150A CN 201010114315 A CN201010114315 A CN 201010114315A CN 101996958 A CN101996958 A CN 101996958A
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layers
rerouting office
semiconductor chip
chip
openings
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CN101996958B (zh
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张恕铭
周正德
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XinTec Inc
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XinTec Inc
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

本发明公开一种芯片封装体及其制造方法。该芯片封装体包括：一承载基板以及设置于一承载基板上的至少一半导体芯片。半导体芯片具有多个导电垫，而多个第一重布局层位于半导体芯片上且电连接于导电垫。一单层绝缘结构覆盖承载基板及半导体芯片，且具有多个开口以露出第一重布局层。多个第二重布局层设置于单层绝缘结构上，并电连接至第一重布局层。一保护层设置于单层绝缘结构上并覆盖第二重布局层，具有多个开口以暴露出第二重布局层。多个导电凸块对应设置于保护层的开口内而电连接至第二重布局层。另一实施例则揭示上述芯片封装体的制造方法。

Description

芯片封装体及其制造方法
技术领域
本发明涉及一种芯片封装，特别是涉及一种扇出式(fan-out)芯片封装体及其制造方法。
背景技术
随着电子或光电产品诸如数字相机、具有影像拍摄功能的手机、条码扫瞄器(bar code reader)以及监视器需求的增加，半导体技术发展的相当快速，且半导体芯片的尺寸有微缩化(miniaturization)的趋势，而其功能也变得更为复杂。
大多数的半导体芯片通常为了效能上的需求而置放于一密封的封装体，其有助于操作上的稳定性。然而，由于先进的半导体芯片必须在更小的面积内提供更多的输入/输出(I/O)导电垫，因而增加半导体封装的困难度，使其良率降低。尤其是在晶片级封装(wafer level chip scale package，WLCSP)的应用上，当半导体芯片尺寸越来越小时，封装体的凸块球距(pitch)以及尺寸会限制位于半导体芯片表面的I/O导电垫数量而妨碍半导体芯片效能的提升。
因此，有必要寻求一种新的封装体结构，其能够解决上述的问题。
发明内容
有鉴于此，本发明一实施例提供一种芯片封装体，包括：一承载基板以及设置于一承载基板上的至少一半导体芯片。半导体芯片具有多个导电垫，而多个第一重布局层位于半导体芯片上且电连接于导电垫。一单层绝缘结构覆盖承载基板及半导体芯片，且具有多个开口以露出第一重布局层。多个第二重布局层设置于单层绝缘结构上，并电连接至第一重布局层。一保护层设置于单层绝缘结构上并覆盖第二重布局层，具有多个开口以暴露出第二重布局层。多个导电凸块对应设置于保护层的开口内而电连接至第二重布局层。
本发明另一实施例提供一种芯片封装体的制造方法，包括：提供至少一半导体芯片在一承载基板上，其中半导体芯片具有多个导电垫；在半导体芯片上形成与导电垫电连接的多个第一重布局层；在承载基板上形成一单层绝缘结构，并覆盖半导体芯片，且跨于第一重布局层上；定义单层绝缘结构以形成多个第一开口，暴露出第一重布局层；在单层绝缘结构上形成多个第二重布局层，使第二重布局层经由第一开口而电连接至第一重布局层；在单层绝缘结构上形成一第一保护层，并覆盖第二重布局层；定义第一保护层以形成多个第二开口，暴露出第二重布局层；以及在第二开口内对应形成多个导电凸块，使导电凸块经由第二开口而电连接至第二重布局层。
附图说明
图1A至图1G为根据本发明实施例的芯片封装体的制造方法剖面示意图；及
图2A至图2C为根据本发明不同实施例的防滑结构。
主要元件符号说明
10～芯片封装体；        100～半导体芯片；
100a～导电垫；          102、212～保护层；
102a、208a、212a～开口；200～承载基底；
202～防滑结构；         204～粘着层；
206、210～重布局层；    208～单层绝缘结构；
214～导电凸块。
具体实施方式
以下说明本发明实施例的制作与使用。然而，可轻易了解本发明所提供的实施例仅用于说明以特定方法制作及使用本发明，并非用以局限本发明的范围。在附图或描述中，相似或相同部分的元件使用相同或相似的符号表示。再者，附图中元件的形状或厚度可扩大，以简化或是方便标示。此外，未绘示或描述的元件，可以是具有各种熟习该项技艺者所知的形式。
请参照图1G，其为根据本发明实施例的芯片封装体10剖面示意图。在本发明的封装体实施例中，其可应用于各种包含主动元件或被动元件(active or passive elements)、数字电路或模拟电路等集成电路的电子元件(electronic components)，例如是有关于光电元件(opto electronic devices)、微机电系统(Micro Electro Mechanical Systems，MEMS)、微流体系统(microfluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(physical sensor)。特别是可选择使用晶片级封装制作工艺对影像感测器、发光二极管、太阳能电池、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件、压力感测器(pressure sensors)、或喷墨头(ink printer heads)等半导体芯片进行封装。
上述晶片级封装制作工艺主要指在晶片阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体芯片重新分布在一承载晶片上，再进行封装制作工艺，也可称之为晶片级封装制作工艺。上述晶片级封装制作工艺也适用于通过堆叠(stack)方式安排具有集成电路的多片晶片，以形成多层集成电路(multi-layer integrated circuitdevices)的封装体。
在本实施例中，芯片封装体10包括：一承载基板200以及至少一半导体芯片100，芯片100可经由一粘着层204而设置于承载基板200上。承载基板200，例如由一空白的硅晶片(raw silicon wafer)或其他不含电路的半导体基板切割而成。此处，为简化附图及说明，仅以单一半导体芯片100表示之。在本实施例中，邻近半导体芯片100的承载基板200上可具有一防滑结构202，用以作为芯片固定装置(shifting stopper)。再者，半导体芯片100具有一芯片保护层(passivation)(未绘示)，其包括多个开口以露出多个导电垫100a，用以将半导体芯片100内的电路(未绘示)电连接至外部电路(未绘示)。此处，为简化附图及说明，仅以两个不相邻的导电垫100a表示之。在一实施例中，两相邻的导电垫之间的间隔(space)在15至25微米(μm)的范围。
此外，在一选择性的步骤中，可考虑额外形成一保护层102于半导体芯片100的芯片保护层上，以重新形成露出多个导电垫100a的多个开口102a，由此可调整芯片保护层的开口形状和尺寸，以符合本实施例的晶片级封装所需的规格。例如由氧化硅、氮化硅、或其组合所构成，或是选择高分子材料，例如，聚醯亚胺树脂(polyimide)或是苯环丁烯(butylcyclobutene：BCB，道氏化学公司)，上述重新形成的开口102a可以局部露出下方对应的导电垫100a，但尺寸已较芯片保护层的开口为小。以下实施例以开口102a为例，但并不以此为限。
多个扇入式(fan-in)重布局层206设置于半导体芯片上，其经由保护层102内的开口102a而与对应的导电垫100a电连接。
一单层绝缘结构208设置于承载基板200上，并覆盖半导体芯片100、防滑结构202且跨于重布局层206上，其中单层绝缘结构208具有多个开口208a以局部露出下方对应的重布局层206。多个重布局层210设置于单层绝缘结构208上，并经由单层绝缘结构208内的开口208a而与对应的重布局层206电连接。不同于扇入式重布局层206，重布局层210进一步向外延伸至半导体芯片100外侧的单层绝缘结构208上而构成扇出式(fan-out)重布局层210结构。
一保护层212，例如一防焊层(solder mask)，设置于单层绝缘结构208上并覆盖重布局层210，其中保护层212具有多个开口212a以局部露出下方对应的重布局层210。多个导电凸块214对应设置于开口212a内，并经由开口212a而电连接至对应的重布局层210。
以下配合图1A至图1G说明根据本发明实施例的芯片封装体10的制造方法。请参照图1A，提供一承载基板200，例如一空白的硅晶片(raw siliconwafer)或其他不含电路的半导体基板，其上具有多个芯片承载区(未绘示)，用以对应放置多个半导体芯片。多个防滑结构对应设置于邻近芯片承载区的承载基板200上。此处，为简化附图及说明，仅以一芯片承载区及与其相邻的一防滑结构202表示之。防滑结构202可包括金属材料或绝缘材料。前者可通过电镀制作工艺而形成，而后者则可通过微影制作工艺或其他现有沉积制作工艺而形成。
图2A至图2C为根据本发明不同实施例的防滑结构，其中相同于图1A的部件使用相同的标号并省略其说明。在一实施例中，如图2A所示，防滑结构202可为一环形物且环绕芯片承载区(如虚线区所示)，用以在后续接合芯片时，作为芯片对准标记及/或芯片固定装置。在另一实施例中，防滑结构202可为多个岛状物且环绕芯片承载区，防滑结构202包括至少两个岛状物，分别邻近于芯片承载区的两个对边或两个邻边。举例而言，如图2B所示，防滑结构202的岛状物具有矩形的上视轮廓且邻近于芯片承载区的所有边缘。在另一实施例中，防滑结构202包括至少两个岛状物，且分别邻近于芯片承载区的两个对角。举例而言，如图2C所示，防滑结构202的岛状物具有L形的上视轮廓且邻近于芯片承载区的四个角落。
接下来，提供多个半导体芯片，用以在后续步骤中设置于承载基板200上对应的芯片承载区。此处，为简化附图及说明，仅以一半导体芯片100表示之，如图1B所示。半导体芯片100本身覆盖有一芯片保护层(未绘示)，其具有多个开口以暴露出多个导电垫100a，用以将半导体芯片100内的集成电路(未绘示)电连接至外部电路(未绘示)。此处，为简化附图及说明，仅以两个不相邻的导电垫100a表示之。需注意的是相邻的导电垫之间的间隔在15至25微米(μm)的范围。
在一实施例中，可以额外增加一道重新定义开口的步骤，例如在芯片上方再另外覆盖一层保护层102，例如由氧化硅、氮化硅、或其组合所构成，或是由高分子材料构成，接着定义出多个开口102a以局部露出下方对应的导电垫100a。在本实施例中，开口102a的尺寸及形状可以配合晶片级封装所需规格，例如通过调整开口102a的尺寸来缩小芯片保护层开口的尺寸，扩大两开口的间距。
请参照图1C，半导体芯片100通过防滑结构202作为对准标记，并通过一粘着层204设置于承载基板200上对应的芯片承载区(如图2A、图2B或图2C的虚线区所示)，其中由于粘着层在硬化之前可能使芯片发生偏移，进而使后续制作工艺发生对位偏差，因此通过围绕芯片的防滑结构202，例如形成邻近于或稍微接触半导体芯片100的防滑结构202，其中，由于粘着材料受到芯片与防滑结构202两者的紧迫，而使粘着材料的流动受到局限，因此芯片的位移量控制在可容许误差之内。在另一实施例中，也可通过防滑结构202作为对准标记，以使芯片精准地设置于承载基板200上。在本实施例中，粘着层204可包括：导电银胶、芯片贴膜(DAF：Die attach film)、或是环氧树脂层。接着，多个重布局层206形成于保护层102上，其中重布局层206经由保护层102的开口102a而电连接至对应的导电垫100a。重布局层206可包括铝、铜、或其他现有导线材料并通过现有沉积技术所形成，例如电镀、无电镀、或物理气相沉积。在本实施例中，重布局层206在半导体芯片100放置于承载基板200之后，形成于该半导体芯片上。在另一实施例中，重布局层206也可在半导体芯片100放置于承载基板200之前，先形成于半导体芯片100上。在一实施例中，重布局层206并不会延伸超出至芯片外。
请参照图1D，在承载基板200上形成一单层绝缘结构208，并覆盖半导体芯片100。单层绝缘结构208可包括环氧树脂材料、聚醯亚胺树脂(polyimide)或是苯环丁烯(butylcyclobutene：BCB，道氏化学公司)，并通过现有技术所形成，例如贴合或涂布。接着，通过现有微影及蚀刻技术在单层绝缘结构208内形成多个开口208a，以局部露出下方对应的重布局层206。
请参照图1E，在单层绝缘结构208上形成多个扇出(fan-out)重布局层210，其中重布局层210经由单层绝缘结构208的开口208a而电连接至对应的重布局层206。同样地，重布局层210可包括铝、铜、或其他现有导线材料并通过现有沉积技术所形成，例如电镀、无电镀或物理气相沉积。再者，重布局层210可向外延伸至半导体芯片100外侧的单层绝缘结构208上。
请参照图1F，在单层绝缘结构208上形成一保护层212，例如一防焊层，并覆盖重布局层210。接着，通过现有微影及蚀刻制作工艺，在保护层212内形成多个开口212a以局部露出下方对应的重布局层210。
请参照图1G，在保护层212的开口212a内对应形成多个导电凸块214，使导电凸块214经由开口212a而电连接至对应的重布局层210。之后，切割由硅晶片构成的承载基底200及其上方的单层绝缘结构208，以形成独立的芯片封装体10。
根据上述的一实施例中，由于半导体芯片100设置于承载基底200上，因此导电凸块214除了可设置于半导体芯片100正上方之外，也可通过扇出式重布局层210形成于半导体芯片100外侧的承载基底200上方。亦即，芯片封装体10的终端接触区(即，导电凸块214所设置之处)无须局限于半导体芯片100正上方，因而可增加终端接触区的数量，以因应高效能的芯片封装需求。再另一实施例中，承载基底200上围绕芯片的防滑结构202，可使半导体芯片100在固定在承载基底200上时可能发生的偏移受到有效控制，以维持或改善芯片封装体的良率。此外，在另一实施例中，采用单层绝缘结构208可同时作为两半导体芯片100之间的填充物以及覆盖重布局层206的保护层，可简化制作工艺步骤并降低制造成本。
虽然已结合以上较佳实施例揭露了本发明，然而其并非用以限定本发明，任何所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作更动与润饰，因此本发明的保护范围应以附上的权利要求所界定的为准。

Claims (19)

1.一种芯片封装体，包括：
承载基板；
至少一半导体芯片，设置于该承载基板上，其中该半导体芯片具有多个导电垫；
多个第一重布局层，对应设置于该半导体芯片上并与该多个导电垫电连接；
单层绝缘结构，设置于该承载基板上，并覆盖该半导体芯片，且跨于该多个第一重布局层上，其中该单层绝缘结构具有多个第一开口以暴露出该多个第一重布局层；
多个第二重布局层，设置于该单层绝缘结构上，并经由该多个第一开口而电连接至该多个第一重布局层；
第一保护层，设置于该单层绝缘结构上并覆盖该多个第二重布局层，其中该第一保护层具有多个第二开口以暴露出该多个第二重布局层；以及
多个导电凸块，对应设置于该多个第二开口内，并经由该多个第二开口而电连接至该多个第二重布局层。
2.如权利要求1所述的芯片封装体，还包括一防滑结构，设置于该承载基板上且围绕该半导体芯片。
3.如权利要求2所述的芯片封装体，其中该防滑结构包括至少两个岛状物，分别邻近于或接触该半导体芯片的两个对角、两个对边或两个邻边。
4.如权利要求3所述的芯片封装体，其中该防滑结构的岛状物具有L型的上视轮廓且邻近于该半导体芯片的角落。
5.如权利要求2至4任一项所述的芯片封装体，其中该防滑结构包括金属材料或绝缘材料。
6.如权利要求5所述的芯片封装体，其中该多个第一重布局层为扇入型重布局层，且该多个第二重布局层为扇出型重布局层。
7.如权利要求6所述的芯片封装体，还包括一第二保护层，设置于该半导体芯片与该多个第一重布局层之间，其中该第二保护层具有多个第三开口，暴露出该多个导电垫，且该多个第一重布局层经由该多个第三开口而电连接至该多个导电垫。
8.如权利要求1所述的芯片封装体，其中该承载基板为一空白硅基底。
9.如权利要求1所述的芯片封装体，其中该单层绝缘结构包括环氧树脂材料、聚醯亚胺树脂或苯环丁烯。
10.一种芯片封装体的制造方法，包括：
提供至少一半导体芯片在一承载基板上，其中该半导体芯片具有多个导电垫；
在该半导体芯片上形成与该多个导电垫电连接的多个第一重布局层；
在该承载基板上形成一单层绝缘结构，并覆盖该半导体芯片，且跨于该多个第一重布局层上；
定义该单层绝缘结构以形成多个第一开口，暴露出该多个第一重布局层；
在该单层绝缘结构上形成多个第二重布局层，使该多个第二重布局层经由该多个第一开口而电连接至该多个第一重布局层；
在该单层绝缘结构上形成一第一保护层，并覆盖该多个第二重布局层；
定义该第一保护层以形成多个第二开口，暴露出该多个第二重布局层；以及
在该多个第二开口内对应形成多个导电凸块，使该多个导电凸块经由该多个第二开口而电连接至该多个第二重布局层。
11.如权利要求10所述的芯片封装体的制造方法，还包括在该承载基板上形成一防滑结构，且该防滑结构围绕该半导体芯片。
12.如权利要求11所述的芯片封装体的制造方法，其中该防滑结构包括至少两个岛状物，分别邻近于或接触该半导体芯片的两个对角、两个对边或两个邻边。
13.如权利要求12所述的芯片封装体的制造方法，其中该防滑结构的岛状物具有L型的上视轮廓且邻近于该半导体芯片的角落。
14.如权利要求11至13任一项所述的芯片封装体的制造方法，其中该防滑结构包括金属材料或绝缘材料。
15.如权利要求14所述的芯片封装体的制造方法，其中该多个第一重布局层为扇入型重布局层，且该多个第二重布局层为扇出型重布局层。
16.如权利要求15所述的芯片封装体的制造方法，还包括：
在该半导体芯片与该多个第一重布局层之间形成一第二保护层；
定义该第二保护层以形成多个第三开口，以暴露出该多个导电垫，且该多个第一重布局层经由该多个第三开口而电连接至该多个导电垫。
17.如权利要求10所述的芯片封装体的制造方法，其中该承载基板为一空白晶片。
18.如权利要求10所述的芯片封装体的制造方法，其中该单层绝缘结构包括环氧树脂材料、聚醯亚胺树脂或苯环丁烯。
19.如权利要求16所述的芯片封装体的制造方法，其中该第一重布局层在该半导体芯片提供于该承载基板上之前，形成于该半导体芯片上。
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