CN102082131B - 晶片封装体及其制造方法 - Google Patents
晶片封装体及其制造方法 Download PDFInfo
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Abstract
本发明提供一种晶片封装体及其制造方法,该晶片封装体包括一含有晶片的半导体基底,具有元件区和周边接垫区,多个导电垫设置于周边接垫区上,晶片保护层覆盖于半导体基底上,暴露出所述导电垫,绝缘保护层形成于元件区的晶片保护层上,以及封装层设置于绝缘保护层之上,暴露出所述导电垫及位于周边接垫区的晶片保护层。该晶片封装体的制造方法包括在切割制程中形成绝缘保护层覆盖导电垫以及利用封装层的开口除去导电垫上方的绝缘保护层。本发明所述的晶片封装体及其制造方法可避免导电垫在切割制程中被切割残余物损害及刮伤。
Description
技术领域
本发明有关于一种晶片封装体,特别有关于一种可以在切割制程中保护导电垫的晶片封装体及其制造方法。
背景技术
目前业界针对晶片的封装已发展出一种晶圆级封装技术,于晶圆级封装体完成之后,需在各晶片之间进行切割步骤,以分离各晶片。
然而由于在使用切割刀形成开口时会产生许多碎屑,这些碎屑有可能使得接合垫在切割制程中受到损害及刮伤,因此在后续制程中会产生打线接合的信赖性问题,导致现有的晶片封装体电性不良。
因此,业界亟需一种晶片封装体,其可以克服上述问题,避免导电垫在切割制程中受到损害。
发明内容
本发明提供一种晶片封装体,包括:一含有晶片的半导体基底,具有元件区和周边接垫区,周边接垫区围绕元件区;多个导电垫设置于周边接垫区上,晶片保护层覆盖于半导体基底上,暴露出所述导电垫,绝缘保护层形成于元件区上,以及封装层设置于绝缘保护层之上,暴露出所述导电垫。
本发明所述的晶片封装体,该绝缘保护层覆盖该元件区而不覆盖该周边接垫区,且该封装层暴露出所述导电垫及位于该周边接垫区的晶片保护层。
本发明所述的晶片封装体,还包括一间隔层设置于该封装层与该绝缘保护层之间。
本发明所述的晶片封装体,还包括一间隙形成于该封装层与该绝缘保护层之间,且其中该间隙被该间隔层所围绕。
本发明所述的晶片封装体,该绝缘保护层与该晶片保护层的材料不同。
本发明所述的晶片封装体,该晶片保护层的材料包括氮化硅,该绝缘保护层的材料包括氧化硅。
本发明所述的晶片封装体,该绝缘保护层的材料包括光致抗蚀剂绝缘材料。
本发明所述的晶片封装体,该绝缘保护层在该间隔层下方区域的硬度大于其他区域。
本发明所述的晶片封装体,该封装层包括一透明基底或一半导体基底。
此外,本发明还提供一种晶片封装体的制造方法,包括:提供一半导体晶圆,包括多个元件区,任两个相邻的元件区之间包括一周边接垫区,且该周边接垫区包括多个导电垫,以及一晶片保护层,覆盖该半导体晶圆,且暴露出所述导电垫;形成一绝缘保护层于该晶片保护层上,且覆盖所述导电垫;提供一封装层;接合该半导体晶圆与该封装层;定义该封装层,以形成多个开口,所述开口暴露出该周边接垫区内的绝缘保护层;以及以该封装层为硬罩幕,除去该周边接垫区内的绝缘保护层,暴露出所述导电垫。
本发明所述的晶片封装体的制造方法,定义该封装层的步骤包括一切割制程,且于该切割制程中,所述导电垫被该绝缘保护层所覆盖。
本发明所述的晶片封装体的制造方法,除去该周边接垫区内的绝缘保护层的步骤包括蚀刻制程。
本发明所述的晶片封装体的制造方法,该绝缘保护层与该晶片保护层的材料不同。
本发明所述的晶片封装体的制造方法,该晶片保护层的材料包括氮化硅,该绝缘保护层的材料包括氧化硅。
本发明所述的晶片封装体的制造方法,该绝缘保护层的材料包括光致抗蚀剂绝缘材料。
本发明所述的晶片封装体的制造方法,还包括形成一间隔层于该封装层与该绝缘保护层之间,及形成一间隙于该封装层与该绝缘保护层之间,其中该间隙被该间隔层所围绕。
本发明所述的晶片封装体的制造方法,还包括:形成一间隔层于该封装层与该绝缘保护层之间及形成一间隙于该封装层与该绝缘保护层之间,其中该间隙被该间隔层所围绕;对该光致抗蚀剂绝缘材料进行曝光,且该光致抗蚀剂绝缘材料于该间隔层下方区域的曝光程度小于其他区域。
本发明所述的晶片封装体的制造方法,该光致抗蚀剂绝缘材料于该间隔层下方区域的硬度大于其他区域。
本发明所述的晶片封装体的制造方法,该封装层为一透明基底或一半导体基底。
本发明所述的晶片封装体及其制造方法可避免导电垫在切割制程中被切割残余物损害及刮伤。
附图说明
图1A至图1F显示依据本发明的一实施例,形成晶片封装体的制造方法的剖面示意图。
具体实施方式
为了让本发明的上述目的、特征及优点能更明显易懂,以下配合所附图式,作详细说明如下。
以下以实施例并配合图式详细说明本发明,在图式或说明书描述中,相似或相同的部分使用相同的图号。且在图式中,实施例的形状或是厚度可扩大,以简化或是方便标示。再者,图式中各元件的部分将以描述说明之,值得注意的是,图中未绘示或描述的元件,为本领域技术人员所知的形式。另外,特定的实施例仅为揭示本发明使用的特定方式,其并非用以限定本发明。
本发明以一制作影像感测元件封装体(image sensorpackage)的实施例作为说明。然而,可以了解的是,在本发明的晶片封装体的实施例中,其可应用于各种包括有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digitalor analog circuits)等集成电路的电子元件(electroniccomponents),例如是有关于光电元件(opto electronic devices)、微机电系统(Micro Electro Mechanical System;MEMS)、微流体系统(micro fluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package;WSP)制程对影像感测元件、发光二极管(light-emitting diodes;LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件(surfaceacoustic wave devices)、压力感测器(process sensors)或喷墨头(ink printer heads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要指在晶圆阶段完成封装步骤后,再予以切割成独立的封装体。然而,在一特定实施例中,例如将已分离的半导体晶片重新分布在一承载晶圆上,再进行封装制程,亦可称之为晶圆级封装制程。另外,上述晶圆级封装制程亦适用于借堆叠(stack)方式安排具有集成电路的多片晶圆,以形成多层集成电路(multi-layer integrated circuit devices)的晶片封装体。
本发明的实施例提供一种晶片封装体及其制造方法,在上述元件的晶圆级封装体完成之后,以切割制程分割各元件时,晶片封装体的导电垫可受到保护,避免被切割制程产生的残余物损害或刮伤。
接着,请参阅图1A至图1F,其显示依据本发明的一实施例,形成晶片封装体的制造方法的剖面示意图。如图1A所示,首先提供一包括多个晶片的半导体晶圆100,其具有元件区100A,任两个相邻的元件区100A之间为周边接垫区100B,以及多个导电垫104位于周边接垫区100B上。此外,半导体晶圆100在晶圆厂产出时一般覆盖有一晶片保护层106(passivation layer),例如为氮化硅层,同时为将晶片内的元件电性连接至外部电路,晶圆厂会事先定义晶片保护层106以形成多个暴露出导电垫104的开口。
接着,如图1B所示,在半导体晶圆100的表面上全面性形成与晶片保护层106不同材料的绝缘保护层108,其覆盖着晶片保护层106以及导电垫104,绝缘保护层108例如为氧化硅层,可利用化学气相沉积法形成。
然后,如图1C所示,提供封装层200以与半导体晶圆100接合,封装层200例如为玻璃基板或是另一空白硅晶圆。在一实施例中,可通过间隔层110分开封装层200与半导体晶圆100,同时形成由间隔层110所围绕的间隙116。间隔层110可以为密封胶,或是感光绝缘材料,例如环氧树脂(epoxy)、阻焊材料(soldermask)等。此外间隔层110可先形成于绝缘保护层108上,之后再通过粘着层(未显示)与相对的封装层200接合,反之,亦可将间隔层110先形成于封装层200上,之后再通过粘着层(未显示)与相对的绝缘保护层108接合。
如图1D所示,使用切割刀(未绘出)在封装层200内产生开口114,其暴露出周边接垫区100B的表面,此时切割制程所产生的切割残余物118,例如玻璃或硅材料碎屑会掉落在绝缘保护层108上。而由于导电垫104受到绝缘保护层108覆盖,因此可避免导电垫104在切割制程中被切割残余物118损害或刮伤。
接着,如图1E所示,通过封装层200的开口114除去周边接垫区100B的至少部分绝缘保护层108,暴露出导电垫104以及晶片保护层106,以利后续在导电垫104上形成与外部电路的电性连接,此时剩余的绝缘保护层108a覆盖着整个由间隔层110所围绕的元件区100A。在此实施例中,由于绝缘保护层108可以为非光致抗蚀剂的绝缘材料,例如氧化硅,此时可利用具有开口114的封装层200作为硬遮罩(hard mask),通过蚀刻方式去除周边接垫区100B内的绝缘保护层108,不需要额外的光刻制程去形成光致抗蚀剂图案作为遮罩。同时,由于绝缘保护层108的材料与原有晶片保护层106的材料不同,因此晶片保护层106可作为绝缘保护层108的蚀刻停止层。在另一实施例中,亦可选择以光刻制程定义周边接垫区100B内的绝缘保护层108,形成暴露出导电垫104的开口。
此外,绝缘保护层108亦可选择光致抗蚀剂材料,此时可实施一曝光步骤,并通过封装层200的开口114,使用显影制程将周边接垫区100B内的绝缘保护层108去除。在此实施例中,间隔层110的材料为不透光材料,位于间隔层110下方的绝缘保护层108a由于不会被曝光或是曝光程度小于其他区域,可使间隔层110下方的绝缘保护层108a的硬度因此大于其他区域如间隙116内被曝光但未被显影的绝缘保护层108的硬度,使得间隔层110下方的结构强度增加。
此外,在本发明的一实施例中,由于间隔层110与氧化硅的附着力大于间隔层110与氮化硅的附着力,因此在上述例子中间隔层与原有氮化硅晶片保护层106间的界面附着力将不如间隔层与新增氧化硅绝缘保护层108a间的界面附着力,因此额外形成的氧化硅保护层108a可增加晶片封装体的信赖度。
接着,请参阅图1E及图1F,沿着周边接垫区的切割线112将半导体晶圆100分割,即可形成多个晶片封装体,如图1F所示。
请参阅图1F,其显示依据本发明一实施例的晶片封装体的剖面示意图,沿着切割线112分离晶圆成晶片封装体102。半导体基底100例如由包括晶片的半导体晶圆分割而来,半导体基底100可分为元件区100A和周边接垫区100B,围绕元件区100A的区域为周边接垫区100B。
在半导体基底100的周边接垫区100B上具有多个导电垫(conductive pad)104,例如为接合垫(bonding pad),导电垫104可通过金属连线(未显示)连接至晶片内部。在半导体基底100的表面上则覆盖有晶片保护层106,例如为氮化硅或氮氧化硅,晶片保护层106另暴露出导电垫104,其可以通过打线接合而电性连接至外部电路。位于元件区100A的晶片保护层106上还覆盖有绝缘保护层108a,例如为氧化硅材料。而在绝缘保护层108a上另设置有封装层200。
在一实施例中,晶片封装体可应用于影像感测元件,例如互补式金属氧化物半导体元件(CMOS)或电荷耦合元件(charge-couple device;CCD),此外如微机电元件等亦不在此限。
上述导电垫104较佳可以由铜(copper;Cu)、铝(aluminum;Al)或其它合适的金属材料所制成。而在封装层200与半导体基底100之间可设置间隔层(spacer)110,使半导体基底100与封装层200之间形成间隙(cavity)116,间隙116被间隔层110所围绕。
在一实施例中,封装层200可以是透明基底,例如玻璃、石英(quartz)、蛋白石(opal)、塑胶或其它任何可供光线进出的透明基板。值得一提的是,也可以选择性地形成滤光片(filter)及/或抗反射层(anti-reflective layer)于封装层200上。在非感光元件晶片的实施例中,封装层200则可以是半导体材料层,例如硅覆盖层。
在另一实施例中,绝缘保护层108a与封装层200之间也可以完全填满间隔层110,而不形成间隙。
上述间隔层110可以是环氧树脂(epoxy resin)、防焊层(solder mask)或其它适合的绝缘物质。
依据本发明的实施例,可在晶圆级封装体的切割制程中形成绝缘保护层在导电垫上,避免导电垫被切割残余物损害及刮伤,而在后续除去绝缘保护层的制程中,因切割制程产生开口的封装层又可作为硬遮罩,因此不需额外形成光致抗蚀剂图案遮罩。
以上所述仅为本发明较佳实施例,然其并非用以限定本发明的范围,任何熟悉本项技术的人员,在不脱离本发明的精神和范围内,可在此基础上做进一步的改进和变化,因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
附图中符号的简单说明如下:
100:半导体基底
100A:元件区
100B:周边接垫区
102:晶片封装体
104:导电垫
106:晶片保护层
108、108a:绝缘保护层
110:间隔层
112:切割线
114:封装层开口
116:间隙
118:切割残余物
200:封装层。
Claims (12)
1.一种晶片封装体,其特征在于,该晶片封装体包括:
一半导体基底,具有一元件区和一周边接垫区,该周边接垫区围绕该元件区;
多个导电垫,设置于该半导体基底的该周边接垫区上;
一晶片保护层,覆盖于该半导体基底上,且暴露出所述导电垫;
一绝缘保护层,覆盖该元件区,该绝缘保护层的材料包括光致抗蚀剂绝缘材料;
一封装层,设置于该绝缘保护层上,且暴露出所述导电垫,其中该绝缘保护层切齐该封装层的外缘;以及
一间隔层,设置于该封装层与该绝缘保护层之间,其中该绝缘保护层的外缘垂直对齐该间隔层的外缘,并且一间隙形成于该封装层与该绝缘保护层之间,且该绝缘保护层在该间隔层下方区域的硬度大于其他区域的硬度。
2.根据权利要求1所述的晶片封装体,其特征在于,该绝缘保护层覆盖该元件区而不覆盖该周边接垫区,且该封装层暴露出所述导电垫及位于该周边接垫区的晶片保护层。
3.根据权利要求1所述的晶片封装体,其特征在于,该间隙被该间隔层所围绕。
4.根据权利要求1至3中任一项所述的晶片封装体,其特征在于,该绝缘保护层与该晶片保护层的材料不同。
5.根据权利要求4所述的晶片封装体,其特征在于,该晶片保护层的材料包括氮化硅。
6.根据权利要求4所述的晶片封装体,其特征在于,该封装层包括一透明基底或一半导体基底。
7.一种晶片封装体的制造方法,其特征在于,该晶片封装体的制造方法包括:
提供一半导体晶圆,包括多个元件区,任两个相邻的元件区之间包括一周边接垫区,且该周边接垫区包括多个导电垫,以及一晶片保护层,覆盖该半导体晶圆,且暴露出所述导电垫;
形成一绝缘保护层于该晶片保护层上,且覆盖所述导电垫,该绝缘保护层的材料包括光致抗蚀剂绝缘材料;
提供一封装层;
形成一间隔层于该封装层与该绝缘保护层之间;
形成一间隙于该封装层与该绝缘保护层之间;
接合该半导体晶圆与该封装层;
定义该封装层,以形成多个开口,所述开口暴露出该周边接垫区内的绝缘保护层;以及
对该光致抗蚀剂绝缘材料进行曝光,并通过该封装层的所述开口,使用显影制程除去该周边接垫区内的绝缘保护层,暴露出所述导电垫,其中该绝缘保护层切齐该封装层的外缘,并且该绝缘保护层的外缘垂直对齐该间隔层的外缘,该光致抗蚀剂绝缘材料于该间隔层下方区域的曝光程度小于其他区域的曝光程度,且该光致抗蚀剂绝缘材料于该间隔层下方区域的硬度大于其他区域的硬度。
8.根据权利要求7所述的晶片封装体的制造方法,其特征在于,定义该封装层的步骤包括一切割制程,且于该切割制程中,所述导电垫被该绝缘保护层所覆盖。
9.根据权利要求7所述的晶片封装体的制造方法,其特征在于,该绝缘保护层与该晶片保护层的材料不同。
10.根据权利要求9所述的晶片封装体的制造方法,其特征在于,该晶片保护层的材料包括氮化硅。
11.根据权利要求7至10中任一项所述的晶片封装体的制造方法,其特征在于,该间隙被该间隔层所围绕。
12.根据权利要求11所述的晶片封装体的制造方法,其特征在于,该封装层为一透明基底或一半导体基底。
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CN107994039B (zh) * | 2017-10-24 | 2022-06-21 | 格科微电子(上海)有限公司 | Cmos图像传感器的晶圆级封装方法 |
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CN113131890A (zh) * | 2019-12-30 | 2021-07-16 | 中芯集成电路(宁波)有限公司 | 封装结构的制造方法 |
CN115140700A (zh) * | 2021-03-30 | 2022-10-04 | 诺思(天津)微系统有限责任公司 | 半导体组件及其切割方法、滤波器及电子设备 |
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