KR100688560B1 - 웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법 - Google Patents

웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법 Download PDF

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KR100688560B1
KR100688560B1 KR1020050066960A KR20050066960A KR100688560B1 KR 100688560 B1 KR100688560 B1 KR 100688560B1 KR 1020050066960 A KR1020050066960 A KR 1020050066960A KR 20050066960 A KR20050066960 A KR 20050066960A KR 100688560 B1 KR100688560 B1 KR 100688560B1
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South Korea
Prior art keywords
wafer
chip scale
level chip
layers
wafer level
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KR1020050066960A
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English (en)
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KR20070012111A (ko
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권용환
이충선
강운병
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삼성전자주식회사
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Priority to KR1020050066960A priority Critical patent/KR100688560B1/ko
Priority to US11/444,410 priority patent/US20070018324A1/en
Publication of KR20070012111A publication Critical patent/KR20070012111A/ko
Application granted granted Critical
Publication of KR100688560B1 publication Critical patent/KR100688560B1/ko
Priority to US12/139,771 priority patent/US7569423B2/en

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Abstract

본 발명은 웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법에 관한 것이다. 본 발명에 따른 웨이퍼 레벨 칩 스케일 패키지는 집적회로가 구성된 반도체 기판, 상기 반도체 기판의 상부에 형성되며 상기 집적회로와 전기적으로 연결된 다수개의 본딩 패드들, 상기 본딩 패드들의 가장자리를 포함한 상기 반도체 기판의 상부에 형성된 보호막, 상기 보호막 위에 형성된 제1 절연층, 상기 제1 절연층과 상기 본딩 패드들 위에 형성된 금속 기저층, 상기 금속 기저층 위에 형성된 재배선층, 상기 재배선층 위에 형성된 제2 절연층, 상기 제2 절연층의 일부가 노출되어 형성된 다수개의 볼 패드들, 상기 다수개의 볼 패드들 위에 접착된 다수개의 도전성 볼들, 및 상기 반도체 기판의 하부와 측면을 감싸며 절연 물질로 구성된 보호부를 구비한다. 따라서, 하부나 측면에 외부 충격이 가해지더라도 웨이퍼 레벨 칩 스케일 패키지는 쉽게 깨어지지 않는다.

Description

웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법{Wafer level chip scale package and manufacturing method thereof}
본 발명의 상세한 설명에서 인용되는 도면을 보다 충분히 이해하기 위하여 각 도면의 간단한 설명이 제공된다.
도 1은 종래의 웨이퍼 레벨 칩 스케일 패키지의 단면도이다.
도 2는 본 발명의 웨이퍼 레벨 칩 스케일 패키지들이 제조된 웨이퍼를 개략적으로 보여준다.
도 3은 도 2의 A 부분을 확대 도시한 도면이다.
도 4는 본 발명에 따른 웨이퍼 레벨 칩 스케일 패키지의 단면도이다.
도 5 내지 도 14는 본 발명에 따른 웨이퍼 레벨 칩 스케일 패키지의 제조 방법을 설명하기 위한 단면도들이다.
<도면의 주요 부분에 대한 부호의 설명>
201; 웨이퍼, 205; 웨이퍼 레벨 칩 스케일 패키지
211; 절단 영역, 311; 볼(들)
41l; 반도체 기판(들), 421; 본딩 패드(들)
431; 보호막(들), 441; 제1 절연층(들)
451; 금속 기저층(들), 461; 재배선층(들)
471; 볼 패드(들), 481; 보호부
711; 임시 지지판
본 발명은 웨이퍼 레벨 칩 스케일 패키지에 관한 것으로서, 특히 두께가 얇으면서도 강성을 갖는 웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법에 관한 것이다.
산업이 발달하고 사람들의 생활이 편리해지면서 전기 제품들이 많이 개발되고 있다. 이러한 전기 제품들에는 대부분 집적회로 장치들이 내장되어 있기 때문에 그 크기가 점차 소형화되고 있다. 때문에, 집적회로 장치의 소형화는 곧 전기 제품의 소형화로 이어진다.
집적회로 장치를 소형화시키기 위하여 개발된 것이 웨이퍼 레벨 칩 스케일 패키지이다. 웨이퍼 레벨 칩 스케일 패키지는 칩 단위로 반도체 패키지를 조립하는 전형적인 패키지 제조 방법과 달리 웨이퍼에 형성된 칩들을 일괄적으로 패키지로 제조하는 것이다.
도 1은 종래의 웨이퍼 레벨 칩 스케일 패키지의 단면도이다. 도 1을 참조하면, 웨이퍼 레벨 칩 스케일 패키지(101)는 반도체 기판(111) 및 솔더 볼들(131)을 포함한다.
반도체 기판(111)에는 집적회로(121)가 구성되어 있으며, 집적회로(121)는 솔더 볼들(131)과 전기적으로 연결된다.
솔더 볼들(131)은 외부 장치(미도시)와 접합되며, 이 때, 상기 외부 장치는 솔더 볼들(131)을 통해서 상기 집적회로와 전기 신호를 주고받는다.
그런데, 종래의 웨이퍼 레벨 칩 스케일 패키지(101)에 의하면, 반도체 기판(111)의 하부(111a)와 측면(111b)이 모두 외부로 노출되어 있다. 따라서, 외부 충격에 의해 반도체 기판(111)의 하부(111a)나 측면(111b) 또는 모서리(111c)가 쉽게 깨어진다. 뿐만 아니라, 웨이퍼(미도시)에 제조된 웨이퍼 레벨 칩 스케일 패키지(101)들을 개별로 분리하기 위해 상기 웨이퍼를 절단할 때 웨이퍼 레벨 칩 스케일 패키지(101)에는 미세한 크랙(crack)이 발생할 수가 있으며, 이러한 미세 크랙으로 말미암아 후 공정에서 웨이퍼 레벨 칩 스케일 패키지(101)가 파손되는 경우가 종종 발생한다.
또한, 반도체 기판(111)은 실리콘으로 구성되어 있기 때문에 웨이퍼 레벨 칩 스케일 패키지(101)가 얇아지면 잘 깨어져서 사용할 수가 없게 된다. 따라서, 웨이퍼 레벨 칩 스케일 패키지(101)의 두께를 얇게 하는 데는 한계가 있다.
본 발명의 목적은 외부 충격에 의해 하부나 측면이 잘 깨어지지 않으며, 두께가 얇은 웨이퍼 레벨 칩 스케일 패키지를 제공하는데 있다.
본 발명의 다른 목적은 외부 충격에 의해 하부나 측면이 잘 깨어지지 않으며, 두께가 얇은 웨이퍼 레벨 칩 스케일 패키지의 제조 방법을 제공하는데 있다.
상기 목적을 달성하기 위하여 본 발명은,
집적회로가 구성된 반도체 기판, 상기 반도체 기판의 상부에 형성되며 상기 집적회로와 전기적으로 연결된 다수개의 본딩 패드들, 상기 본딩 패드들의 가장자리를 포함한 상기 반도체 기판의 상부에 형성된 보호막, 상기 보호막 위에 형성된 제1 절연층, 상기 제1 절연층과 상기 본딩 패드들 위에 형성된 금속 기저층, 상기 금속 기저층 위에 형성된 재배선층, 상기 재배선층 위에 형성된 제2 절연층, 상기 제2 절연층의 일부가 노출되어 형성된 다수개의 볼 패드들, 상기 다수개의 볼 패드들 위에 접착된 다수개의 도전성 볼들, 및 상기 반도체 기판의 하부와 측면을 감싸며 절연 물질로 구성된 보호부를 구비하는 것을 특징으로 하는 웨이퍼 레벨 칩 스케일 패키지를 제공한다.
상기 다른 목적을 달성하기 위하여 본 발명은,
(a) 집적회로 및 상기 집적회로에 연결된 다수개의 볼 패드들이 형성된 칩이 다수개 제조된 웨이퍼를 준비하는 단계와, (b) 상기 웨이퍼의 하부를 얇게 그라인딩하는 단계와, (c) 상기 웨이퍼의 상부에 임시 지지판을 부착하는 단계와, (d) 상기 다수개의 칩들을 개별로 분리하기 위해 상기 웨이퍼를 1차로 절단하는 단계와, (e) 상기 웨이퍼의 하부를 절연 물질로 몰딩하는 단계와, (f) 상기 임시 지지판을 제거하는 단계와, (g) 상기 다수개의 볼 패드들에 다수개의 도전성 볼들을 접착하는 단계, 및 (h) 상기 웨이퍼를 2차로 절단하여 상기 칩들을 낱개로 분리하는 단계를 포함하는 것을 특징으로 하는 웨이퍼 레벨 칩 스케일 패키지의 제조 방법을 제공한다.
바람직하기는, 상기 (a) 단계는 (a-1) 상기 칩들은 반도체 기판들의 상부에 형성된 집적회로들을 구비하고 상기 반도체 기판들 위에 상기 집적회로들에 연결된 다수개의 본딩 패드들을 형성하는 단계와, (a-2) 상기 본딩 패드들의 가장자리들을 포함하여 상기 반도체 기판들 위에 보호막들을 형성하는 단계와, (a-3) 상기 보호막들 위에 제1 절연층들을 형성하는 단계와, (a-4) 상기 제1 절연층들과 상기 본딩 패드들 위에 금속 기저층들을 형성하는 단계와, (a-5) 상기 금속 기저층들 위에 재 배선층들을 형성하는 단계와, (a-6) 상기 재배선층들 위에 제2 절연층들을 형성하는 단계, 및 (a-7) 상기 제2 절연층들의 일부를 노출시켜서 상기 볼 패드들을 형성하는 단계를 포함한다.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 설명함으로써, 본 발명을 상세히 설명한다. 각 도면에 제시된 동일한 참조부호는 동일한 부재를 나타낸다.
도 2는 본 발명의 웨이퍼 레벨 칩 스케일 패키지들이 제조된 웨이퍼를 개략적으로 보여주며, 도 3은 도 2의 A 부분을 확대 도시한 도면이다. 도 2 및 도 3을 참조하면, 웨이퍼(201)에 집적회로가 구성된 다수개의 웨이퍼 레벨 칩 스케일 패키지들(205)이 제조되며, 다수개의 웨이퍼 레벨 칩 스케일 패키지들(205)은 절단 영역(211)에 의해 서로 구분된다. 다수개의 웨이퍼 레벨 칩 스케일 패키지들(205) 각각에 다수개의 볼들(311)이 접착되어 있으며, 다수개의 볼들(311)이 외부 장치(미도시)와 접합됨으로써 웨이퍼 레벨 칩 스케일 패키지들(205)은 상기 외부 장치와 전기 신호를 주고받는다.
웨이퍼(101)의 절단 영역(211)을 따라 절단함으로써 웨이퍼 레벨 칩 스케일 패키지들(205)은 개별로 분리된다.
도 4는 본 발명에 따른 웨이퍼 레벨 칩 스케일 패키지의 단면도이다. 도 4를 참조하면, 웨이퍼 레벨 칩 스케일 패키지(205)는 반도체 기판(411), 본딩 패드(421), 보호막(431), 제1 절연층(441), 금속 기저층(under barrier metel)(451), 재배선층(461), 제2 절연층(442), 볼 패드(471), 볼(481) 및 보호부(491)를 포함한 다.
집적회로(미도시)가 구성된 반도체 기판(411) 위에 본딩 패드(421)와 보호막(431)이 형성되어 있다. 본딩 패드(421)는 전기 신호의 입출력 단자 역할을 하는 것으로서, 알루미늄과 같은 금속으로 형성된다. 보호막(431)은 실리콘산화막 또는 실리콘질화막과 같은 절연 물질로 구성되며, 상기 집적회로를 외부 환경으로부터 보호한다. 보호막(431)은 본딩 패드(421)의 가장자리 위에도 형성된다. 도 4에는 본딩 패드(431)가 하나만 도시되어 있으나, 실제적으로 웨이퍼 레벨 칩 스케일 패키지(205)는 본딩 패드(421)를 다수개 구비한다.
보호막(431) 위에 제1 절연층(441)이 형성되어 있다. 제1 절연층(441)은 보호막(431)을 금속 기저층(451)과 절연시키며, 열응력을 완충시키는 역할을 한다. 제1 절연층(441)은 폴리이미드(polyimide), 폴리벤즈옥사졸(polybenzoxazole; PBO), 벤조사이클로부텐(benzocyclobutene; BCB), 에폭시(epoxy), 폴리머(polymer) 등으로 구성된다.
본딩 패드(421)와 제1 절연층(441) 위에 금속 기저층(451)이 형성되어 있다. 금속 기저층(451)은 재배선층(461)의 접착력을 증가시키며, 재배선층(461)을 도금할 때 도금이 용이해지도록 한다. 금속 기저층(451)은 금속들, 예컨대 구리, 니켈, 티타늄 등의 합금으로 구성된다. 금속 기저층(451)은 본딩 패드(421)와 재배선층(461)을 전기적으로 연결한다.
금속기저층(451) 위에 재배선층(461)이 형성되어 있다. 재배선층(461)은 전기 전도성이 양호한 금속, 예컨대, 크롬, 구리, 니켈, 티타늄, 텅스텐, 바나듐, 팔 라듐, 알루미늄, 금 또는 이들의 합금으로 구성된다.
재배선층(461) 위에 제2 절연층(442)이 형성되어 있다. 제2 절연층(442)은 재배선층(461)을 외부 환경으로부터 보호한다.
제2 절연층(442)의 일부가 노출된 곳에 볼 패드(471)가 형성되어 있다.
볼 패드(471)에 볼(311)이 접착된다. 볼(311)은 도전성을 갖는 물질, 예컨대 납 또는 주석-납(Sn-Pb)의 합금으로 구성된다. 볼(311)이 외부 장치(미도시)와 접합됨으로써 웨이퍼 레벨 칩 스케일 패키지(205)는 상기 외부 장치와 전기 신호를 주고받는다.
도 4에는 볼 패드(471)와 볼(311)이 하나씩만 도시되어 있으나, 실제적으로 웨이퍼 레벨 칩 스케일 패키지(205)는 볼 패드(471)와 볼(311)을 다수개 구비한다.
웨이퍼 레벨 칩 스케일 패키지(205)의 하부와 측면들은 모두 보호부(481)에 의해 감싸져 있다. 보호부(481)는 강도가 높은 에폭시 몰딩 컴파운드로 구성된다.
이와 같이, 웨이퍼 레벨 칩 스케일 패키지(205)의 하부와 측면들이 모두 보호부(481)에 의해 감싸져 있기 때문에, 웨이퍼 레벨 칩 스케일 패키지(205)의 하부나 측면에 외부로부터 충격이 가해지더라도 웨이퍼 레벨 칩 스케일 패키지(205)의 하부나 측면 또는 모서리가 쉽게 깨어지지 않는다.
또한, 웨이퍼(도 2의 201)에 제조된 다수개의 웨이퍼 레벨 칩 스케일 패키지들(205)을 개별로 분리하기 위해 웨이퍼(도 2의 201)를 절단할 때, 보호부(481)에 의해 웨이퍼 레벨 칩 스케일 패키지(205)의 하부나 측면에 미세 크랙이 발생하지 않는다. 따라서, 후 공정을 진행하는 과정에서 웨이퍼 레벨 칩 스케일 패키지(205)는 쉽게 파손되지 않는다.
도 5 내지 도 14는 본 발명에 따른 웨이퍼 레벨 칩 스케일 패키지의 제조 방법을 설명하기 위하여 제조 방법 순서대로 도시한 단면도들이다. 도 5 내지 도 14는 설명의 편의상 웨이퍼의 일부를 도시한 단면도들이다.
도 5에 도시된 바와 같이, 복수개의 반도체 기판들(411) 위에 본딩 패드들(421)과 보호막들(431)을 형성한다. 반도체 기판들(411)은 웨이퍼(201)에 구비되며, 절단 영역(211)에 의해 구분된다. 반도체 기판들(411)에는 집적회로들(미도시)이 구성된다. 상기 집적회로들을 구성하는 방법은 통상적인 기술에 해당하므로 구체적인 설명을 생략한다. 본딩 패드들(421)은 상기 집적회로들과 전기적으로 연결된다. 보호막들(431)은 본딩 패드들(421)의 가장자리들을 포함하여 반도체 기판들(411) 위에 형성되며, 상기 집적회로들을 외부 환경으로부터 보호한다. 본딩 패드들(421)과 보호막들(431)은 웨이퍼(201)에 상기 집적회로들을 구성하는 공정에서 형성된다.
도 6에 도시된 바와 같이, 반도체 기판들(411) 위에 제1 절연층들(441), 금속 기저층들(451), 재배선층들(461), 제2 절연층들(442) 및 볼 패드들(471)을 순차적으로 형성한다.
먼저, 보호막들(431) 위에 제1 절연층들(441)을 형성한다. 제1 절연층들(441)은 통상적인 스핀 코팅(spin coating) 방법과 포토(photo) 공정을 통하여 형성한다.
제1 절연층들(441)과 상기 본딩 패드들(421) 위에 금속 기저층들(451)을 형 성한다. 금속 기저층들(451)은 스퍼터링(sputtering) 또는 증착법(evaporation)을 이용하여 티타늄, 크롬, 구리, 니켈 또는 이들의 합금을 반도체 기판들(411) 위에 적층하여 형성할 수 있다. 금속 기저층들(451) 위에 제1 감광막 패턴들(미도시)을 형성하여 금속 기저층들(451)을 패터닝한다. 금속 기저층들(451)을 패터닝한 후에 상기 제1 감광막 패턴들을 제거한다.
패터닝된 금속 기저층들(451) 위에 재배선층들(461)을 형성한다. 재배선층들(461)은 볼 패드들(471)을 배치하기 위한 것이다. 금속 기저층들(451)을 도금 전극들로 이용하여 금속을 금속 기저층들(451) 위에 도금한다. 이 때, 티타늄과 구리를 사용하여 스퍼터링 방법으로 재배선층들(461)을 형성하거나, 구리와 니켈을 사용하여 도금 방법으로 재배선층들(461)을 형성하는 것이 바람직하다. 무전해 도금법을 이용하여 재배선층들(461)을 금속 기저층들(451) 위에만 형성할 수 있기 때문에, 이 경우에는 재배선층들(461)을 형성하기 위한 별도의 패터닝 공정이 필요없다.
패터닝된 재배선층들(461)을 포함하여 반도체 기판들(411) 위에 제2 절연층들(442)을 형성한다. 제2 절연층들(442)은 재배선층들(461)을 외부 환경으로부터 보호한다.
제2 절연층들(442) 위에 제2 감광막 패턴들(미도시)을 형성하여 제2 절연층들(442)의 일부를 노출시킴으로써 볼 패드들(471)을 형성한다. 볼 패드들(471)을 형성한 후에 상기 제2 감광막 패턴들을 제거한다.
상기 제1 및 제2 감광막들로써 포토레지스트를 사용한다.
도 7에 도시된 바와 같이, 웨이퍼(201) 위에 임시 지지판(711)을 부착한다. 임시 지지판(711)은 이 후에 떼어낼 것이므로 제2 절연층(442)을 손상시키지 않는 범위 내에서 적절한 접착력을 유지할 수 있어야 한다. 임시 지지판(711)으로는 연성을 갖는 부재와 경성을 갖는 부재 모두 사용 가능하지만, 웨이퍼(201)를 안전하게 취급하기 위해서는 경성을 갖는 부재를 사용하는 것이 바람직하다.
도 8에 도시된 바와 같이, 웨이퍼(201)의 후면을 1차로 그라인딩하여 웨이퍼(201)의 두께를 얇게 만든다. 이 때, 웨이퍼를 설정된 두께만큼 그라인딩한다. 웨이퍼 레벨 칩 스케일 패키지(도 4의 205)의 두께가 얇으면, 웨이퍼 레벨 칩 스케일 패키지(도 4의 205)를 채용하는 제품의 크기도 작아지게 된다. 웨이퍼(201)가 임시 지지판(711)해 고정됨으로 웨이퍼(201)를 그라인딩하는 것이 용이하여 얼마든지 얇게 그라인딩할 수 있다.
도 9에 도시된 바와 같이, 웨이퍼(201)를 1차로 절단한다. 즉, 웨이퍼(201)를 절단 영역(도 6의 211)을 따라 절단한다. 이 때, 임시 지지판(711)은 절단하지 않는다. 따라서, 절단된 반도체 기판들(411)은 임시 지지판(711)에 의해 원래대로 지지된다.
도 10에 도시된 바와 같이, 웨이퍼(201)에 보호부(481)를 형성한다. 즉, 웨이퍼(201)의 후면을 강도가 높은 절연 물질, 예컨대, 에폭시 몰딩 컴파운드로 몰딩한다. 그러면, 반도체 기판들(411)의 후면들과 측면들은 모두 절연 물질에 의해 감싸진다.
도 11에 도시된 바와 같이, 웨이퍼(201)의 후면을 2차로 그라인딩한다. 웨 이퍼(201)의 후면은 보후부(481)에 의해 두꺼워졌으므로, 보호부(481)를 그라인딩하여 웨이퍼(201)를 원하는 만큼 얇게 만든다.
도 12에 도시된 바와 같이, 웨이퍼(201) 위에 부착된 임시 지지판(711)을 제거하고, 웨이퍼(201)를 크리닝한다. 웨이퍼(201)의 후면이 보호부(481)에 의해 지지되므로, 임시 지지판(711)을 제거하여도 반도체 기판들(411)은 낱개로 분리되지 않는다. 임시 지지판(711)을 제거할 경우, 임시 지지판(711)의 접착 물질 또는 임시 지지판(711)을 접착하는 과정에서 이물질이 웨이퍼(201)의 상부에 붙어 있을 수가 있다. 이러한 접착 물질 또는 이물질을 제거하기 위하여 웨이퍼(201)를 크리닝한다.
도 13에 도시된 바와 같이, 볼 패드들(471)에 도전성 볼들(311)을 접착한다. 볼들(311) 대신에 구리, 금, 니켈 등과 같은 금속으로 구성된 범프들을 형성할 수도 있다.
도 14에 도시된 바와 같이, 웨이퍼(201)를 2차로 절단하여 반도체 기판들(411)을 낱개로 분리한다. 따라서, 웨이퍼 레벨 칩 스케일 패키지들(205)이 완성된다.
도면과 명세서에서 최적 실시예가 개시되었으며, 본 기술 분야의 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시예가 가능할 것이다. 따라서, 본 발명의 진정한 기술적 보호 범위는 첨부된 특허청구범위에 기재된 기술적 사상에 의해 정해져야 할 것이다.
상술한 바와 같이, 웨이퍼 레벨 칩 스케일 패키지의 하부와 측면에 강도가 높은 보호부를 형성함으로써, 웨이퍼 레벨 칩 스케일 패키지의 하부나 측면에 외부 충격이 가해지더라도 쉽게 깨어지지 않는다.
또한, 웨이퍼 레벨 칩 스케일 패키지의 후면에 보호부가 형성되어 있기 때문에, 웨이퍼 레벨 칩 스케일 패키지를 얇게 그라인딩하더라도 웨이퍼 레벨 칩 스케일 패키지는 잘 깨어지지 않는다. 따라서, 본 발명의 웨이퍼 레벨 칩 스케일 패키지는 두께가 얇은 칩 스케일 패키지를 요구하는 곳에 아무런 문제없이 채용될 수가 있다.

Claims (12)

  1. 집적회로가 구성된 반도체 기판;
    상기 반도체 기판의 상부에 형성되며, 상기 집적회로와 전기적으로 연결된 다수개의 본딩 패드들;
    상기 본딩 패드들의 가장자리를 포함한 상기 반도체 기판의 상부에 형성된 보호막;
    상기 보호막 위에 형성된 제1 절연층;
    상기 제1 절연층과 상기 본딩 패드들 위에 형성된 금속 기저층;
    상기 금속 기저층 위에 형성된 재배선층;
    상기 재배선층 위에 형성된 제2 절연층;
    상기 제2 절연층의 일부가 노출되어 형성된 다수개의 볼 패드들;
    상기 다수개의 볼 패드들 위에 접착된 다수개의 도전성 볼들; 및
    상기 반도체 기판의 하부와 측면을 감싸며, 절연 물질로 구성된 보호부를 구비하는 것을 특징으로 하는 웨이퍼 레벨 칩 스케일 패키지.
  2. 제1항에 있어서, 상기 보호부는
    에폭시 몰딩 컴파운드로 구성된 것을 특징으로 하는 웨이퍼 레벨 칩 스케일 패키지.
  3. 제1항에 있어서, 상기 볼들은 각각
    솔더로 구성된 것을 특징으로 하는 웨이퍼 레벨 칩 스케일 패키지.
  4. 삭제
  5. (a) 집적회로 및 상기 집적회로에 연결된 다수개의 볼 패드들이 형성된 칩이 다수개 제조된 웨이퍼를 준비하는 단계;
    (b) 상기 웨이퍼의 하부를 얇게 그라인딩하는 단계;
    (c) 상기 웨이퍼의 상부에 임시 지지판을 부착하는 단계;
    (d) 상기 다수개의 칩들을 개별로 분리하기 위해 상기 웨이퍼를 1차로 절단하는 단계;
    (e) 상기 웨이퍼의 하부를 절연 물질로 몰딩하는 단계;
    (f) 상기 임시 지지판을 제거하는 단계;
    (g) 상기 다수개의 볼 패드들에 다수개의 도전성 볼들을 접착하는 단계; 및
    (h) 상기 웨이퍼를 2차로 절단하여 상기 칩들을 낱개로 분리하는 단계를 포함하는 것을 특징으로 하는 웨이퍼 레벨 칩 스케일 패키지의 제조 방법.
  6. 삭제
  7. 제5항에 있어서, 상기 (c) 단계의 웨이퍼 절단 과정에서 상기 임시 지지판은 절단하지 않는 것을 특징으로 하는 웨이퍼 레벨 칩 스케일 패키지의 제조 방법.
  8. 제5항에 있어서, 상기 (d) 단계는
    상기 웨이퍼의 하부를 몰딩한 후에 상기 웨이퍼의 하부를 얇게 그라인딩하는 단계를 더 포함하는 것을 특징으로 하는 웨이퍼 레벨 칩 스케일 패키지의 제조 방법.
  9. 제5항에 있어서, 상기 (d) 단계의 절연 물질은
    에폭시 몰딩 컴파운드인 것을 특징으로 하는 웨이퍼 레벨 칩 스케일 패키지의 제조 방법.
  10. 제5항에 있어서, 상기 (e) 단계는
    상기 임시 지지판을 제거한 후에 상기 웨이퍼를 크리닝하는 단계를 더 포함하는 것을 특징으로 하는 웨이퍼 레벨 칩 스케일 패키지의 제조 방법.
  11. 제5항에 있어서, 상기 (f) 단계의 볼들은 각각
    솔더로 구성하는 것을 특징으로 하는 웨이퍼 레벨 칩 스케일 패키지의 제조 방법.
  12. 제5항에 있어서, 상기 (a) 단계는
    (a-1) 상기 칩들은 반도체 기판들의 상부에 형성된 집적회로들을 구비하고, 상기 반도체 기판들 위에 상기 집적회로들에 연결된 다수개의 본딩 패드들을 형성하는 단계;
    (a-2) 상기 본딩 패드들의 가장자리들을 포함하여 상기 반도체 기판들 위에 보호막들을 형성하는 단계;
    (a-3) 상기 보호막들 위에 제1 절연층들을 형성하는 단계;
    (a-4) 상기 제1 절연층들과 상기 본딩 패드들 위에 금속 기저층들을 형성하는 단계;
    (a-5) 상기 금속 기저층들 위에 재배선층들을 형성하는 단계;
    (a-6) 상기 재배선층들 위에 제2 절연층들을 형성하는 단계; 및
    (a-7) 상기 제2 절연층들의 일부를 노출시켜서 상기 볼 패드들을 형성하는 단계를 포함하는 것을 특징으로 하는 웨이퍼 레벨 칩 스케일 패키지의 제조 방법.
KR1020050066960A 2005-07-22 2005-07-22 웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법 KR100688560B1 (ko)

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US11/444,410 US20070018324A1 (en) 2005-07-22 2006-06-01 Wafer-level-chip-scale package and method of fabrication
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