CN101154641A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN101154641A CN101154641A CNA2007101541917A CN200710154191A CN101154641A CN 101154641 A CN101154641 A CN 101154641A CN A2007101541917 A CNA2007101541917 A CN A2007101541917A CN 200710154191 A CN200710154191 A CN 200710154191A CN 101154641 A CN101154641 A CN 101154641A
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- Prior art keywords
- semiconductor chip
- wiring pattern
- semiconductor device
- external connection
- connection terminals
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Abstract
本发明公开一种半导体器件及其制造方法,所述半导体器件包括由封装树脂封装的半导体芯片,本发明的目的是提供一种可以减小尺寸的半导体器件及其制造方法。该半导体器件包括:半导体芯片(15);外部连接端子焊盘(18),其与所述半导体芯片(15)电连接;封装树脂(16),其用于封装半导体芯片(15),其中,外部连接端子焊盘(18)形成于配线图案(12)上面,该配线图案(12)设置在半导体芯片(15)和外部连接端子焊盘(18)之间,半导体芯片(15)倒装结合到所述配线图案(12)上。
Description
技术领域
本发明涉及半导体器件及其制造方法,更具体地涉及包括由封装树脂封装的半导体芯片的半导体器件及其制造方法。
背景技术
在传统半导体器件中,存在这样一种半导体器件,其中,为了实现小型化而从中除去了核心基板(例如,参见图1)。
图1是传统半导体器件的横截面图。在图1中,“J”表示在半导体芯片10上形成的封装树脂103的厚度(下文称之为“厚度J”)。
参考附图1,传统半导体器件100包括芯片固定树脂101、半导体芯片102、封装树脂103、外部连接端子104和金(Au)线105。
芯片固定树脂101用于将半导体芯片102固定在后面描述的金属板110(见图5)上。芯片固定树脂101的底面101A与封装树脂103的底面103A基本齐平。
半导体芯片102以面朝上的方式固定在芯片固定树脂101上。半导体芯片102具有电极片107。电极片107通过金(Au)线105与外部连接端子104连接。也就是说,半导体芯片102引线接合到外部连接端子104。
设置封装树脂103以便封装半导体芯片102和金(Au)线105。封装树脂103具有凸起部108,该凸起部108从封装树脂103的底面103A突出。
设置外部连接端子104以便覆盖凸起部108。外部连接端子104通过金(Au)线105电连接到半导体芯片102。
图2到图6是示出传统半导体器件的制造步骤的视图。在图2到图6中,任何与图1所示的半导体器件100相同的构成部分由相同的附图标记表示。
下面将参考图2到图6描述传统半导体器件100的制造方法。在图2所示的制造步骤中,在金属板110上形成凹入部111。接着,在图3所示的制造步骤中,在金属板110上形成阻挡膜113,该阻挡膜具有开口113A从而仅露出凹入部111,然后,通过电解镀法在金属板110上与凹入部111对应的区域中沉积镀膜,从而形成外部连接端子104。在图4所示的随后的制造步骤中,除去阻挡膜113。
接下来,在图5所示的制造步骤中,通过芯片固定树脂101以面朝上的方式将半导体芯片102固定在金属板110上,随后,通过金(Au)线105连接(引线接合)电极片107和外部连接端子104。
接下来,在图6所示的制造步骤中,在金属板110上形成封装半导体芯片102和金线105的封装树脂103。随后,通过除去金属板110完成如图1所示的半导体器件100(例如,参见专利文献1:JP-A-9-162348)。
然而,在传统半导体器件100中,由于半导体芯片102和外部连接端子104引线接合,并且金(Au)线105的多个部分设置在半导体芯片102上方,所以为了封装金线105的这些部分,在半导体102上形成的封装树脂103的厚度J必须较大(具体地说,至少为150μm)。这使得半导体器件100较厚,因此存在这样的问题,即难以实现半导体器件100的小型化。
发明内容
相应地,考虑到上述问题而做出本发明,本发明的目的是提供一种可以小型化的半导体器件及其制造方法。
根据本发明的第一方面,提供一种半导体器件,包括:
半导体芯片;
外部连接端子焊盘,其与所述半导体芯片电连接;
封装树脂,其用于封装所述半导体芯片;以及
配线图案,其上安装有所述外部连接端子焊盘,所述配线图案设置在所述半导体芯片和所述外部连接端子焊盘之间;其中
所述半导体芯片倒装结合到所述配线图案的朝向所述半导体芯片的部分上。
根据本发明,通过将设置有所述外部连接端子焊盘的配线图案设置在所述半导体芯片和所述外部连接端子焊盘之间,并将所述半导体芯片倒装结合到所述配线图案的朝向所述半导体芯片的部分上,可以减小设置在所述半导体芯片上方的所述封装树脂的厚度,这样,可以实现所述半导体器件的小型化(具体地说,减小所述半导体器件在厚度方向上的尺寸)。
根据本发明的第二方面,提供一种半导体器件的制造方法,所述半导体器件包括:半导体芯片,其上设置有内部连接端子;外部连接端子焊盘,其电连接到所述半导体芯片上;封装树脂,其封装所述半导体芯片;以及配线图案,其设置在所述半导体芯片和所述外部连接端子焊盘之间,并电连接到所述半导体芯片上,
所述方法包括:
金属层层压步骤,其用于在构成支撑板的金属板上依次层压第一金属层和第二金属层;
配线图案形成步骤,其用于蚀刻所述第二金属层以形成所述配线图案;
各向异性导电树脂形成步骤,其用于在所述第一金属层上形成各向异性导电树脂,以覆盖所述配线图案;以及
半导体芯片结合步骤,其用于将所述半导体芯片按压在所述各向异性导电树脂上,以使得所述内部连接端子与所述配线图案压力结合,从而将所述半导体芯片倒装结合到所述配线图案上。
此外,根据本发明的第三方面,提供一种半导体器件的制造方法,所述半导体器件包括:半导体芯片,其上设置有内部连接端子;外部连接端子焊盘,其电连接到所述半导体芯片上;封装树脂,其封装所述半导体芯片;以及配线图案,其设置在所述半导体芯片和所述外部连接端子焊盘之间,并电连接到所述半导体芯片上,
所述方法包括:
金属层层压步骤,其用于在构成支撑板的金属板上依次层压第一金属层、第二金属层和第三金属层;
配线图案形成步骤,其用于蚀刻所述第三金属层以形成所述配线图案;
各向异性导电树脂形成步骤,其用于在所述第一金属层上形成各向异性导电树脂,以覆盖所述配线图案;以及
半导体芯片结合步骤,其用于将所述半导体芯片按压在所述各向异性导电树脂上,以使得所述内部连接端子与所述配线图案压力结合,从而将所述半导体芯片倒装结合到所述配线图案上。
根据本发明,在所述第一金属层上形成所述各向异性导电树脂以覆盖所述配线图案,然后,通过将所述半导体芯片按压在所述各向异性导电树脂上,以使得所述内部连接端子和所述配线图案压力结合,从而将所述半导体芯片倒装结合到所述配线图案上,可以减小设置在所述半导体芯片上方的所述封装树脂的厚度,从而可以实现所述半导体器件的小型化(具体地说,减小所述半导体器件在厚度方向上的尺寸)。
此外,通过采用所述各向异性导电树脂,与采用一般绝缘树脂的情况相比,按压所述半导体芯片的压力更小,这样可以更容易地制造所述半导体器件。
根据本发明的第四方面,提供一种半导体器件的制造方法,所述半导体器件包括:半导体芯片,其上设置有内部连接端子;外部连接端子焊盘,其电连接到所述半导体芯片上;封装树脂,其封装所述半导体芯片;以及配线图案,其设置在所述半导体芯片和所述外部连接端子焊盘之间,并电连接到所述半导体芯片上,
所述方法包括:
金属层形成步骤,其用于在构成支撑板的金属板上依次层压第一金属层和第二金属层;
配线图案形成步骤,其用于蚀刻所述第二金属层以形成所述配线图案;
绝缘树脂形成步骤,其用于在所述第一金属层上形成绝缘树脂,以覆盖所述配线图案;以及
半导体芯片结合步骤,其用于将所述半导体芯片按压在所述绝缘树脂上,以使得所述内部连接端子与所述配线图案压力结合,从而将所述半导体芯片倒装结合到所述配线图案。
此外,根据本发明的五方面,提供一种半导体器件的制造方法,所述半导体器件包括:半导体芯片,其上设置有内部连接端子;外部连接端子焊盘,其电连接到所述半导体芯片上;封装树脂,其封装所述半导体芯片;以及配线图案,其设置在所述半导体芯片和所述外部连接端子焊盘之间,并电连接到所述半导体芯片上,
所述方法包括:
金属层形成步骤,其用于在构成支撑板的金属板上依次层压第一金属层、第二金属层和第三金属层;
配线图案形成步骤,其用于蚀刻所述第三金属层以形成所述配线图案;
绝缘树脂形成步骤,其用于在所述第一金属层上形成绝缘树脂,以覆盖所述配线图案;以及
半导体芯片结合步骤,其用于将所述半导体芯片按压在所述绝缘树脂上,以使得所述内部连接端子与所述配线图案压力结合,从而将所述半导体芯片倒装结合到所述配线图案上。
根据本发明,在所述第一金属层上形成所述绝缘树脂以覆盖所述配线图案,然后,通过将所述半导体芯片按压在所述绝缘树脂上,以使得所述内部连接端子和所述配线图案压力结合,从而将所述半导体芯片倒装结合到所述配线图案上,可以减小设置在所述半导体芯片上方的所述封装树脂的厚度,从而可以实现所述半导体器件的小型化(具体地说,减小所述半导体器件在厚度方向上的尺寸)。
根据本发明,可以实现半导体器件的小型化。
附图说明
图1是示出传统半导体器件的横截面图。
图2示出传统半导体器件的制造步骤(第一步)。
图3示出传统半导体器件的制造步骤(第二步)。
图4示出传统半导体器件的制造步骤(第三步)。
图5示出传统半导体器件的制造步骤(第四步)。
图6示出传统半导体器件的制造步骤(第五步)。
图7是根据本发明第一实施例的半导体器件的横截面图。
图8示出根据本发明第一实施例的半导体器件的制造步骤(第一步)。
图9示出根据本发明第一实施例的半导体器件的制造步骤(第二步)。
图10示出根据本发明第一实施例的半导体器件的制造步骤(第三步)。
图11示出根据本发明第一实施例的半导体器件的制造步骤(第四步)。
图12示出根据本发明第一实施例的半导体器件的制造步骤(第五步)。
图13示出根据本发明第一实施例的半导体器件的制造步骤(第六步)。
图14示出根据本发明第一实施例的半导体器件的制造步骤(第七步)。
图15示出根据本发明第一实施例的半导体器件的制造步骤(第八步)。
图16示出根据本发明第一实施例的半导体器件的制造步骤(第九步)。
图17示出根据本发明第一实施例的半导体器件的制造步骤(第十步)。
图18示出根据本发明第一实施例的半导体器件的制造步骤(第十一步)。
图19是根据本发明第二实施例的半导体器件的横截面图。
图20是根据本发明第三实施例的半导体器件的横截面图。
图21示出根据本发明第三实施例的半导体器件的制造步骤(第一步)。
图22示出根据本发明第三实施例的半导体器件的制造步骤(第二步)。
图23示出根据本发明第三实施例的半导体器件的制造步骤(第三步)。
图24示出根据本发明第三实施例的半导体器件的制造步骤(第四步)。
图25示出根据本发明第三实施例的半导体器件的制造步骤(第五步)。
图26示出根据本发明第三实施例的半导体器件的制造步骤(第六步)。
图27示出根据本发明第三实施例的半导体器件的制造步骤(第七步)。
具体实施方式
现在将参考附图描述本发明的实施例。
第一实施例
图7是根据本发明第一实施例的半导体器件的横截面图。
参考图7,根据本发明第一实施例的半导体器件10包括绝缘树脂11、配线图案12和13、半导体芯片15、封装树脂16、阻焊层17、外部连接端子焊盘18、外部连接端子19及内部连接端子21。
设置绝缘树脂11以覆盖配线图案12、13的顶面12A、13A和侧面12C、13C。处于半固化状态的绝缘树脂11具有粘接剂的功能。对于绝缘树脂11,可以使用例如粘接性片状绝缘树脂(即NCF(非导电膜))、膏状绝缘树脂(即NCP(非导电膏))或者在形成堆积层时采用的堆积绝缘树脂等。绝缘树脂11的厚度T1可以是,例如,20μm。
在绝缘树脂11上设置配线图案12、13。绝缘树脂11覆盖配线图案12、13的顶面12A、13A和侧面12C、13C。配线图案12、13的底面12B、13B从绝缘树脂11中露出。配线图案12、13的底面12B、13B与绝缘树脂11的底面11B基本齐平。配线图案12具有:芯片连接区域22,其与内部连接端子21相连;以及焊盘形成区域23,其上形成外部连接端子焊盘18。芯片连接区域22设置在配线图案12的顶面12A上。焊盘形成区域23设置在配线图案12的底面12B上。对于配线图案12、13的材料,例如可以采用铜(Cu)。配线图案12、13的厚度可以为例如10μm。
通过设置这种配线图案12,可以将外部连接焊盘18的形成位置相应地调整到与半导体器件10连接的安装板(未示出)上的焊盘的位置。
半导体芯片15具有电极片25。半导体芯片15设置在绝缘树脂11上,以便使得半导体芯片15的设置有电极片25的表面15A与绝缘树脂11的顶面11A接触。电极片25通过内部连接端子21电连接到配线图案12上。也就是说,半导体芯片15倒装结合到配线图案12上。半导体芯片15由封装树脂16覆盖。
这样,通过将半导体芯片15倒装结合到配线图案12上,在半导体芯片15上方将不再有引线接合连接的引线,从而可以减小在半导体芯片15上方形成的封装树脂16的厚度T2,从而可以实现半导体器件的小型化(具体地说,减小半导体器件在厚度方向上的尺寸)。形成于半导体芯片15上方的封装树脂16的厚度T2可以是,例如,30μm至60μm。
设置封装树脂16以便覆盖绝缘树脂11的顶面11A和侧面11C以及半导体芯片15。封装树脂16的底面16A与绝缘树脂11的底面11B基本齐平。封装树脂16用于保护半导体芯片15免受外部冲击等损害。封装树脂可以例如采用金属模具通过转移成型法形成。对于封装树脂16,可以采用例如环氧树脂。
设置阻焊层17以覆盖绝缘树脂11的底面11B、配线图案12的底面12B的除了焊盘形成区域23以外的部分、配线图案13的底面13B和封装树脂16的底面16A。阻焊层17用于保护配线图案12、13。
外部连接端子焊盘18包括镍(Ni)膜17和金(Au)膜28。镍(Ni)膜27设置在焊盘形成区域23内。金(Au)膜28设置在镍(Ni)膜27下方。
外部连接端子19设置在作为外部连接端子焊盘18的构成部分的金(Au)膜28的底面上。外部连接端子19用于将半导体器件10连接到诸如母板等安装板(未示出)上。对于外部连接端子19,可以采用例如焊料凸点。
内部连接端子21设置在绝缘树脂11内。内部连接端子21的一端与电极片25连接,另一端与配线图案12的对应于芯片连接区域22的部分连接。对于内部连接端子21,例如,可以使用金(Au)凸点、镀金(Au)膜或金属膜,所述金属膜包括通过无电解镀方法形成的镍(Ni)膜和覆盖镍(Ni)膜的金(Au)膜。
根据本实施例的半导体器件,通过在半导体芯片15和外部连接端子焊盘18之间设置配线图案12(其上设置有外部连接端子焊盘18),并且将半导体芯片15倒装结合到配线图案12上,可以减小在半导体芯片15上方形成的封装树脂16的厚度T2,从而实现半导体器件的小型化(具体地说,减小半导体器件在厚度方向上的尺寸)。
图8至图18是示出根据本发明第一实施例的半导体器件的制造步骤的视图。在图8至图18中,任何与图7所示第一实施例的半导体器件10相同的构成部分都以相同的附图标记表示。
下面将参考图8至图18描述根据本发明第一实施例的半导体器件的制造方法。首先,在图8所示的制造步骤中,提供了作为支撑板的金属板35。金属板35在平面图中具有圆形形状。金属板35具有多个半导体形成区域A,在这些半导体形成区域上形成半导体器件10。对于金属板35,例如可以使用铜(Cu)箔。金属板35的厚度可以为例如100μm。在图8中,“B”表示在封装树脂16上由切割机切断的位置(下文中称之为“切断位置B”)。
此外,金属板35可以具有矩形而不是圆形的形状。
接下来,在图9所示的制造步骤中,形成金属层36以覆盖金属板35。对于金属层36,可以使用例如铜(Cu)箔。金属层36的厚度可以为例如10μm。
接下来,在图10所示的制造步骤中,使金属层36图案化,以在金属板35上方形成与半导体器件形成区域A对应的配线图案12、13(配线图案形成步骤)。更具体的说,在图9所示的金属层36上方形成图案化的阻蚀膜,随后,采用该阻蚀膜作为掩模通过各向异性蚀刻法蚀刻金属层36,以形成配线图案12、13。
接下来,在图11所示的制造步骤中,形成绝缘树脂11,以覆盖在金属板35上形成的配线图案12、13的顶面12A、13A和侧面12C、13C。对于绝缘树脂11,可以使用例如粘接性片状绝缘树脂(即NCF(非导电膜))、或者膏状绝缘树脂(即NCP(非导电膏))。当使用膏状绝缘树脂(即NCP(非导电膏))作为绝缘树脂11时,采用印刷方法形成膏状绝缘树脂,然后将膏状绝缘树脂预烤至半固化状态。该半固化绝缘树脂具有粘接剂的功能。绝缘树脂11的厚度T1可以为例如20μm。
接下来,在图12所示的制造步骤中,提供具有电极片25的半导体芯片15,在该电极片25上形成有内部连接端子21。在加热图12所示结构的同时,将半导体芯片15按压在绝缘树脂11上,从而使得内部连接端子21压入配合在绝缘树脂11内,并且使得内部连接端子21和配线图案12的与芯片连接区域22对应的部分压力结合,从而将半导体芯片15倒装连接到配线图案12上(半导体芯片连接步骤)。此时,通过加热如图12所示的结构,使绝缘树脂11固化。
这样,通过将半导体芯片15倒装结合到配线图案12上,在半导体芯片15的上方将不再有引线接合连接的引线,可以减小在半导体芯片15上方形成的封装树脂16的厚度T2,从而可以实现半导体器件的小型化(具体地说,减小半导体器件10在厚度方向上的尺寸)。
对于内部连接端子21,可以使用例如金(Au)凸点、金(Au)镀膜或者金属膜,所述金属膜包括通过非电解镀形成的镍(Ni)膜和覆盖镍(Ni)膜的金(Au)膜。
接下来,在图13所示的制造步骤中,在金属板35上形成封装树脂16,以覆盖形成在多个半导体器件形成区域A内的绝缘树脂11以及半导体芯片15。更具体地说,采用金属模具通过转移成型法形成封装树脂16。对于封装树脂16,可以使用例如环氧树脂。在半导体芯片15上方形成的封装树脂16的厚度T2可以为例如30μm到60μm。
接下来,在图14所示的制造步骤中,除去金属板35(金属板除去步骤),然后在配线图案12、13的底面12B、13B上进行粗糙化处理。更具体地说,通过湿式蚀刻法蚀刻金属板35以除去金属板35,然后,通过黑氧化处理(black oxide process)或者通过切克劳斯基处理(CZ process)使配线图案12、13的底面12B、13B粗糙化。粗糙化处理用于提高配线图案12、13与将要形成于配线图案12、13的底面12B、13B上的阻焊层17之间的结合力。
接下来,在图15所示的制造步骤中,在图14所示结构的底侧形成具有开口17A的阻焊层17。形成开口17A以露出配线图案12的与焊盘形成区域23对应的部分。
接下来,在图16所示的制造步骤中,在配线图案12的底面12B的经由开口17A露出的部分上,通过电解镀方法依次沉积镍(Ni)膜27和金(Au)膜28(外部连接端子焊盘形成步骤)。
接下来,在图17所示的制造步骤中,在作为外部连接端子焊盘18的构成部分的金(Au)膜28的底面上形成外部连接端子19。接下来,在图18所示的制造步骤中,通过采用切割机沿切断位置B切断封装树脂16和阻焊层17,完成多个半导体器件10的制造。
根据本实施例的半导体器件的制造方法,在金属板35上形成绝缘树脂11以覆盖配线图案12、13,然后半导体芯片按压在绝缘树脂11上,从而使得内部连接端子21与配线图案压力结合,以便将半导体芯片15倒装结合到配线图案12上,从而可以使得设置在半导体芯片15上方的封装树脂16的厚度T2较薄,这样可以实现半导体器件10的小型化(具体地说,减小半导体器件在厚度方向上的尺寸)。
第二实施例
图19是根据本发明第二实施例的半导体器件的横截面图。在图19中,任何与第一实施例的半导体器件10相同的构成部分都以相同的附图标记表示。
参考图19,除了在半导体器件10中设置各向异性导电树脂41来代替绝缘树脂11之外,第二实施例的半导体器件40的构造方式与第一实施例的半导体器件10相似。
对于各向异性导电树脂41,可以使用粘接性片状各向异性导电树脂(即ACF(各向异性导电膜))或者膏状各向异性导电树脂(即ACP(各向异性导电膏))等。ACP和ACF包括环氧树脂基绝缘树脂,其含有由分散于其中的镍(Ni)/金(Au)覆盖的小树脂球,并且在竖直方向上具有导电性,在水平方向上具有绝缘性。
当使用膏状各向异性导电树脂(即ACP(各向异性导电膏))作为各向异性导电树脂41时,通过印刷方法形成膏状各向异性导电树脂,然后将膏状各向异性导电树脂预烤至半固化状态。该半固化的各向异性导电树脂具有作为粘接剂的功能。
同样,在使用该各向异性导电树脂41的情况下,可以采用与第一实施例的半导体器件10相似的方法来制造半导体器件40,并且可以获得与第一实施例的半导体器件10的制造方法相似的结果。
此外,在采用上述各向异性导电树脂41制造半导体器件40时,按压半导体芯片时所施加的压力可以比采用一般绝缘树脂的情况更小,这样可以容易地制造半导体器件40。
第三实施例
图20是根据本发明第三实施例的半导体器件的横截面图。在图20中,任何与第一实施例的半导体器件10相同的构成部分以相同的附图标记表示。
参考图20,除了在半导体器件10中设置外部连接端子焊盘51来代替外部连接端子焊盘18之外,第三实施例的半导体器件50的构造方式与第一实施例的半导体器件10相似。
外部连接端子焊盘51设置在配线图案12的底面12B上与焊盘形成区域23对应的部分上。对于外部连接端子焊盘51,可以使用例如锡(Sn)膜。
具有该构造的第三实施例的半导体器件50也可以获得与第一实施例的半导体器件10相似的效果。
图21至图27是示出根据本发明第三实施例的半导体器件的制造步骤的视图。在图21至图27中,任何与图20所示第三实施例的半导体器件50相同的构成部分都以相同的附图标记表示。
下面将参考图21至图27描述第三实施例的半导体器件50的制造方法。首先,在图21所示的制造步骤中,形成第一金属层55以覆盖根据第一实施例所述的金属板35(图8),然后形成第二金属层56以覆盖第一金属层55(金属层层压步骤)。
第一金属层55作为蚀刻第二金属层56时的阻蚀层,同时作为蚀刻并除去金属板35时的阻蚀层。当使用铜(Cu)作为金属板35和第二金属层56的材料时,可以使用例如锡(Sn)作为第一金属层55的材料。第一金属层55的厚度可以为例如2μm。另外,第二金属层56的厚度可以为例如10μm。
接下来,在图22所示的制造步骤中,蚀刻第二金属层56以形成配线图案12、13(配线图案形成步骤)。更具体地说,该步骤按照与根据第一实施例所述的图10所示步骤相似的方式执行。
此时,由于在蚀刻第二金属层56时作为阻蚀层的第一金属层55设置在第二金属层56和金属板35之间,因此在蚀刻第二金属层56时将不蚀刻金属板35,从而可以提高配线图案12、13的厚度精度。
接下来,在图23所示的制造步骤中,执行与结合第一实施例所述的图11至图13所示的步骤相似的步骤。更具体地说,将半导体芯片15倒装结合到配线图案12上,然后,在第一金属层55上形成封装树脂16,以封装绝缘树脂11和半导体器件15。
接下来,在图24所示的制造步骤中,通过蚀刻除去金属板35(金属板除去步骤)。此时,由于在蚀刻金属板35时作为阻蚀层的第一金属层55设置在第二金属层56和金属板35之间,所以在蚀刻金属板35时可以防止蚀刻第二金属层56。
接下来,在图25所示的制造步骤中,使第一金属层55图案化,以在配线图案12的底侧形成外部连接端子焊盘51(外部连接端子焊盘形成步骤)。更具体地说,在图23所示的第一金属层55的底面上形成图案化抗蚀膜,然后采用该抗蚀膜作为掩模通过各向异性蚀刻法蚀刻第一金属层55,以形成外部连接端子焊盘51。
这样,通过图案化第一金属层55(其在蚀刻第二金属层56和金属板35时作为阻蚀层)而形成外部连接端子焊盘51,与设置单独的金属层来形成外部连接端子焊盘51的情况相比,简化了半导体器件50的制造步骤。
接下来,在图26所示的制造步骤中,通过与结合第一实施例所述的图15所示的制造步骤相似的方法,在图25所示结构的底面上形成具有开口17A的阻焊层17,然后,通过结合第一实施例所述的图17所示的制造步骤相似的方法,在外部连接端子焊盘51上形成外部连接端子19。
接下来,在图27所示的制造步骤中,通过采用切割机沿切断位置B切断封装树脂16,完成多个半导体器件50的制造。
根据本实施例的半导体器件的制造方法,在第一金属层55上形成绝缘树脂11以覆盖配线图案12、13,然后通过将半导体芯片15按压在绝缘树脂11上来使内部连接端子21和配线图案12压力结合,以便将半导体芯片15倒装结合到配线图案12上,可以减小设置在半导体芯片15上方的封装树脂16的厚度T2,从而可以实现半导体器件50的小型化(具体地说,减小半导体器件50在厚度方向上的尺寸)。
此外,通过图案化第一金属层55(其在蚀刻第二金属层56和金属板35时作为阻蚀层)而形成外部连接端子焊盘51,与设置单独的金属层来形成外部连接端子焊盘51的情况相比,可以简化半导体器件50的制造步骤。
在本实施例中,半导体器件50描述为采用绝缘膜11进行制造,然而,可以采用结合第二实施例所述的各向异性导电树脂41制造半导体器件50。
尽管至此已经描述了本发明的优选实施例,然而本发明不限于所公开的任何具体的实施例,而是可以在权利要求书所述的本发明的范围和精髓内进行各种变化和修改。
本发明适用于具有由封装树脂封装的半导体芯片的半导体器件及其制造方法。
此外,本发明适用于凸点位于电极(输入端)内侧的情况以及凸点位于电极(输出端)外侧的情况。
Claims (17)
1.一种半导体器件,包括:
半导体芯片;
外部连接端子焊盘,其与所述半导体芯片电连接;
封装树脂,其用于封装所述半导体芯片;以及
配线图案,其上设置有所述外部连接端子焊盘,所述配线图案设置在所述半导体芯片和所述外部连接端子焊盘之间;其中,
所述半导体芯片倒装结合到所述配线图案的朝向所述半导体芯片的部分上。
2.一种半导体器件的制造方法,所述半导体器件包括:半导体芯片,其上设置有内部连接端子;外部连接端子焊盘,其与所述半导体芯片电连接;封装树脂,其用于封装所述半导体芯片;以及配线图案,其设置在所述半导体芯片和所述外部连接端子焊盘之间,并电连接到所述半导体芯片上,
所述方法包括:
金属层层压步骤,其用于在构成支撑板的金属板上依次层压第一金属层和第二金属层;
配线图案形成步骤,其用于蚀刻所述第二金属层以形成所述配线图案;
各向异性导电树脂形成步骤,其用于在所述第一金属层上形成各向异性导电树脂,以覆盖所述配线图案;以及
半导体芯片结合步骤,其用于将所述半导体芯片按压在所述各向异性导电树脂上,以使得所述内部连接端子与所述配线图案压力结合,从而将所述半导体芯片倒装结合到所述配线图案上。
3.根据权利要求2所述的半导体器件的制造方法,其中,
所述第一金属层是蚀刻所述第二金属层时的阻蚀层。
4.根据权利要求2所述的半导体器件的制造方法,还包括:
在形成所述封装树脂之后执行如下步骤:
金属板除去步骤,其通过蚀刻除去所述金属板;以及
外部连接端子焊盘形成步骤,其使所述第一金属层图案化以形成所述外部连接端子焊盘。
5.根据权利要求4所述的半导体器件的制造方法,其中,
所述第一金属层是蚀刻所述金属板时的阻蚀层。
6.一种半导体器件的制造方法,所述半导体器件包括:半导体芯片,其上设置有内部连接端子;外部连接端子焊盘,其与所述半导体芯片电连接;封装树脂,其用于封装所述半导体芯片;以及配线图案,其设置在所述半导体芯片和所述外部连接端子焊盘之间,并电连接到所述半导体芯片上,
所述方法包括:
金属层形成步骤,其用于在构成支撑板的金属板上依次层压第一金属层和第二金属层;
配线图案形成步骤,其用于蚀刻所述第二金属层以形成所述配线图案;
绝缘树脂形成步骤,其用于在所述第一金属层上形成绝缘树脂,以覆盖所述配线图案;以及
半导体芯片结合步骤,其用于将所述半导体芯片按压在所述绝缘树脂上,以使得所述内部连接端子与所述配线图案压力结合,从而将所述半导体芯片倒装结合到所述配线图案上。
7.根据权利要求6所述的半导体器件的制造方法,其中,
所述第一金属层是蚀刻所述第二金属层时的阻蚀层。
8.根据权利要求6所述的半导体器件的制造方法,还包括:
在形成所述封装树脂之后执行如下步骤:
金属板除去步骤,其通过蚀刻除去所述金属板;以及
外部连接端子焊盘形成步骤,其使所述第一金属层图案化以形成所述外部连接端子焊盘。
9.根据权利要求8所述的半导体器件的制造方法,其中,
所述第一金属层是蚀刻所述金属板时的阻蚀层。
10.一种半导体器件的制造方法,所述半导体器件包括:半导体芯片,其上设置有内部连接端子;外部连接端子焊盘,其与所述半导体芯片电连接;封装树脂,其用于封装所述半导体芯片;以及配线图案,其设置在所述半导体芯片和所述外部连接端子焊盘之间,并电连接到所述半导体芯片上,
所述方法包括:
金属层层压步骤,其用于在构成支撑板的金属板上依次层压第一金属层、第二金属层和第三金属层;
配线图案形成步骤,其用于蚀刻所述第三金属层以形成所述配线图案;
各向异性导电树脂形成步骤,其用于在所述第一金属层上形成各向异性导电树脂,以覆盖所述配线图案;以及
半导体芯片结合步骤,其用于将所述半导体芯片按压在所述各向异性导电树脂上,以使得所述内部连接端子与所述配线图案压力结合,从而将所述半导体芯片倒装结合到所述配线图案上。
11.根据权利要求10所述的半导体器件的制造方法,其中,
所述第二金属层是蚀刻所述第三金属层时的阻蚀层。
12.根据权利要求10所述的半导体器件的制造方法,还包括:
在形成所述封装树脂之后执行如下步骤:
金属板除去步骤,其通过蚀刻除去所述金属板;以及
外部连接端子焊盘形成步骤,其使所述第一金属层图案化以形成所述外部连接端子焊盘。
13.根据权利要求12所述的半导体器件的制造方法,其中,
所述第一金属层是蚀刻所述金属板时的阻蚀层。
14.一种半导体器件的制造方法,所述半导体器件包括:半导体芯片,其上设置有内部连接端子;外部连接端子焊盘,其与所述半导体芯片电连接;封装树脂,其用于封装所述半导体芯片;以及配线图案,其设置在所述半导体芯片和所述外部连接端子焊盘之间,并电连接到所述半导体芯片上,
所述方法包括:
金属层形成步骤,其用于在构成支撑板的金属板上依次层压第一金属层、第二金属层和第三金属层;
配线图案形成步骤,其用于蚀刻所述第三金属层以形成所述配线图案;
绝缘树脂形成步骤,其用于在所述第一金属层上形成绝缘树脂,以覆盖所述配线图案;以及
半导体芯片结合步骤,其用于将所述半导体芯片按压在所述绝缘树脂上,以使得所述内部连接端子与所述配线图案压力结合,从而将所述半导体芯片倒装结合到所述配线图案上。
15.根据权利要求14所述的半导体器件的制造方法,其中,
所述第二金属层是蚀刻所述第三金属层时的阻蚀层。
16.根据权利要求14所述的半导体器件的制造方法,还包括:
在形成所述封装树脂之后执行如下步骤:
金属板除去步骤,其通过蚀刻除去所述金属板;以及
外部连接端子焊盘形成步骤,其使所述第一金属层图案化以形成所述外部连接端子焊盘。
17.根据权利要求16所述的半导体器件的制造方法,其中,所述第一金属层是蚀刻所述金属板时的阻蚀层。
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CN107408547A (zh) * | 2015-03-03 | 2017-11-28 | 苹果公司 | 扇出型系统级封装件及其形成方法 |
CN107408552A (zh) * | 2015-04-07 | 2017-11-28 | 苹果公司 | 薄型低翘曲扇出封装件中的双面安装存储器集成 |
CN111627867A (zh) * | 2019-02-28 | 2020-09-04 | 富泰华工业(深圳)有限公司 | 芯片封装结构及其制作方法 |
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JP2010165940A (ja) * | 2009-01-16 | 2010-07-29 | Shinko Electric Ind Co Ltd | 半導体素子の樹脂封止方法 |
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CN107408547A (zh) * | 2015-03-03 | 2017-11-28 | 苹果公司 | 扇出型系统级封装件及其形成方法 |
CN107408547B (zh) * | 2015-03-03 | 2019-12-24 | 苹果公司 | 扇出型系统级封装件及其形成方法 |
CN107408552A (zh) * | 2015-04-07 | 2017-11-28 | 苹果公司 | 薄型低翘曲扇出封装件中的双面安装存储器集成 |
CN111627867A (zh) * | 2019-02-28 | 2020-09-04 | 富泰华工业(深圳)有限公司 | 芯片封装结构及其制作方法 |
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