TW201203411A - Manufacturing method of chip package and chip package manufactured using the same - Google Patents

Manufacturing method of chip package and chip package manufactured using the same Download PDF

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Publication number
TW201203411A
TW201203411A TW100114085A TW100114085A TW201203411A TW 201203411 A TW201203411 A TW 201203411A TW 100114085 A TW100114085 A TW 100114085A TW 100114085 A TW100114085 A TW 100114085A TW 201203411 A TW201203411 A TW 201203411A
Authority
TW
Taiwan
Prior art keywords
lead
leads
wafer
metal substrate
chip package
Prior art date
Application number
TW100114085A
Other languages
Chinese (zh)
Inventor
Hyung-Eui Lee
Chung-Sik Park
Hyun-A Chun
Sai-Ran Eom
Original Assignee
Lg Innotek Co Ltd
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Filing date
Publication date
Application filed by Lg Innotek Co Ltd filed Critical Lg Innotek Co Ltd
Publication of TW201203411A publication Critical patent/TW201203411A/en

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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
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    • H01L23/495—Lead-frames or other flat leads
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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The present invention relates to a manufacturing method of a chip package, the method comprising: forming first leads and second leads, both having conductivity, on the top and bottom surfaces of a metal substrate; half-etching the top surface of the metal substrate to form a lead portion under the first leads and to form a die pad portion whose bottom is connected to the lead portion; attaching a chip onto the die pad portion and electrically connecting the chip and the first leads by a connector; forming an insulative molding portion on the metal substrate to bury the chip and the connector; and etching the bottom of the metal substrate to short-circuit the lead portion and the die pad portion, and a chip package manufactured using the same. Accordingly, the distance between a chip and first leads can be reduced by forming a conventional bump-shaped I/O pad in a lead shape, thus lead to cost reduction. Moreover, a large number of signal transmission systems can be reliably realized in a micro-pattern due to the lead shape. Moreover, the stability of the product can be improved by treating the thickness of the lead portion in the final step of the process.

Description

201203411 ·, 六、發明說明： 【發明所屬之技術領域】 本發明主張關於2010年07月08日所申請的南韓專利 案號10-2010-0065776的優先權，並在此以引用的方式併 入本文中，以作為參考。 本發明係關於一晶片封裝件之製造方法以及其製品。 更特定而言，為可於低成本下實現大量的訊號傳輸系統之 晶片封裝件製造方法及其製品。 【先前技術】 半導體封裝是一種將晶圓中個別的晶片電性連接的程 序以在實際生活中作為儲存部件，且密閉封裝保護晶片避 免因外力撞擊而損壞。 一晶圓片上通常包括數打或數百個印刷有相同電路的 晶片。每個晶片本身並無法作用為一電子零件，所以必須 以導線來連接於外部，以便從外部接收電子訊號以及傳送 該晶片上所操作的電子訊號。除外，因為晶片包括微型電 路，所以晶片可由於潮濕、灰塵或外部碰撞而容易損壞。 因此，形成在晶圓表面上的晶片無法視為完整的產品，直 到這些晶片被安裝在印刷電路板（P C B)上作為電子部件。據 此，一封裝製程是將晶片封裝成最終成品的一程序，而使 晶圓上的晶片得以電性連接和密閉封裝以禁得起外力撞 擊，才能成為完整的電子元件般來使用。 在半導體封裝時，一引線架（lead frame)扮演著提供 201203411 » ， 安裝晶片和傳送訊號之輸入/輸出整的重要角色，而用於高 整合訊號傳送的不同形狀引線架之發展也持續發展進行 中。 在般的引線架中，一晶片焊塾（die pad)或I/O整 是經由蝕刻技術或沖壓成形方法所形成。然而，要用傳統 引線架製造方法來製造用於高度整合半導體裝置所需要的 多列（multiple-rows)的引線（ieads)卻是不易形成的。 圖1顯不根據習知技術之晶片封裝件製造程序的剖視圖。 參閱圖1，第一引線13〇、第二引線14〇、一上晶片焊墊金 屬部110和一下晶片焊墊金屬部12〇係形成在一金屬基板 100之上表面和下表面（Si)、以及一凸塊19〇其係由半蝕 刻所形成（S2)。接下來，一晶片150安裝在一晶片安裝凹 部10上，且晶片150經由一導線160與各内引線130進行 電性連接（S3)。之後，用以封閉（m〇iding)晶片150、導線 160、以及導線160和第一引線130之間之接觸區域的一模 製部170形成在一絕緣封膠材料（insuiative modling material)上（S4)。最後，金屬基板100的底部經蝕刻以 形成凸塊190以及形成一晶片焊墊部180(S5)。 然而’因為用來結合導線160使用大量的金（Au)，所 以使用需形成凸塊190的製程之成本很高。另外，當藉由 蝕刻形成複數個凸塊190時，且因等向性蝕刻（is〇tropic etching)造成減少凸塊間距之限制。此外，第一和第二引 線130、140與金屬基板100之間和金屬基板1〇〇與模製部 201203411 ，， 17 0之間的附著力很容易減弱，因此降低了可靠度。 【發明内容】 本發明致力於解決上述之問題，而本發明之一目的在 於提供一種晶片封裝件製造方法，其可降低因使用過多的 金線所造成之成本、使利用一微型圖案之成為可行、以及 改善結合可靠度。 (技術解決方案） 根據本發明之一考量面，提供一晶片封裝件的製造方 法，該方法包括：在一金屬基板之上和下表面上形成皆具 有導電性之多個第一引線（f i rst 1 eads)和多個第二引線 (second leads);半蝕刻該金屬基板之該上表面，以在該 第一引線之下形成一引線部以及形成其底部連接於該引線 部之一晶片焊墊部；將一晶片附著在該晶片焊墊部上且藉 由一連接器（connector)將該晶片和該些第一引線電性連 接，在該金屬基板上形成一絕緣模製部（insulative molding portion)以掩埋該晶片與該連接器；以及蝕刻該 金屬基板之該底部以將該引線部和該晶片焊墊部短路 (short-circuit) 〇 在該些第一引線和該些第二引線形成過程中可實施一 電鍍（plating)步驟，使該些第一引線配置於該些第二引線 内侧或該些第一引線配置於該些第二引線外侧。 該些第一引線和該些第二引線可在該金屬基板的至少 一部分上形成一不規則圖案之後形成。或者是一不規則圖 201203411 之上表面和下表*的該些第- 不一彳丨線形成後，形成在 第二引線之至少一者的表面上 °Λ &amp;第一引線和該些 至少該些第一弓卜線或該些第二 ㈤層、銀(¼)層、金⑽層、_❿其中，由: 以-層或多層形式所形成。 胃U及銅（Cu)層 在該些第—引線和該些第二引線 片焊墊金屬部更可开, 、’形成過程中，一晶 該方法更成該金屬基板之頂部或底部。 部和對形成在金屬基板下表面的晶議 因此可實祐 或有機保焊劑(osp)的表面處理。 實施該金屬基板之上表面的半 *的::引:，基板在侧後的厚度為二 在1線#該晶片焊塾部的短路迴路中，該引線部 可藉由該金屬基板的下表 T曰μ W 丨刀/、匕括該些第二引線和該 下曰曰片谭金&gt;1部’形成水平部和垂直部作祕刻拒焊 (etChing reSiSt)。在此情況下，該引線部之水平部和垂 直部之間的-連接部之寬度，可大於形成在該垂直部之表 面上的該第二引線寬度。 根據本發明之晶片封裝件可藉由上述之製程所實現， 其配置如下所述。 特定而言’該晶片封裝件可包括：與一晶片焊墊部間 隔而設的一引線部，且該引線部包含垂直部（vertical portions)和水平部（horizontal portions);具導電性之 201203411 ,, 第-引線（first leads)位於相鄰該晶片焊塾部的位置，且 形成在該引線部之該水平部的上表面上；具導電性之第二 引線（S_d leadS)形成在該引線部之該垂直部的下表: 上；一晶片形成在該晶片焊墊部之上表面上；一連接器電 性連接該晶片與該些第-引線；以及一模製部，其支揮該 引線部和該晶片焊墊部，且掩埋該晶片和該連接器。 -不規則圖案可形成於該引線部、該晶片焊墊部、該 些第一引線、以及該些第二引線的至少一者的表面上。 或者，根據本發明之晶片封裝件可具有一結構，其中 該些第一引線設置在該些第二引線内側或該些第一引線設 置在該些第二引線外側。 進-步而言，該晶片封裝件更可包括一表面處理層由 錫（Sn)或有機保焊劑（0SP)所製成並形成在該些第二引線 的表面上。 另外’本發明可實現一晶片封裝件，其中該引線部之 該水平部和該垂直部之間的一連接部之寬度，大於在該垂 直部之表面形成的該第二引線的寬度。 除此之外’本發明可實現一晶片封裝件，其中該第一 引線和該第二引線包括鎳（Ni)層、銀（Ag)層、金（Au)層、 鈀（Pd)層、以及一銅（Cu)層中的至少一者或多層。 根據本發明’晶片和第一引線之間之距離，可藉由將 一傳統凸塊形狀（bump-shaped)的I/O塾片形成為一引線 形狀而減小，進而導致成本降低。再者，可因為該引線形 201203411 ，, 狀而使一大量訊號傳輸系統得以可靠地在一微型圖案中實 現。此外，產品之穩定性可經由製程中最後步驟的引線部 厚度處理而被改善。 【實施方式】 根據本發明一考量面之晶片封裝件製造方法包括：在 一金屬基板之上和下表面上形成皆具有導電性之多個第一 引線（first leads)和多個第二引線（second leads);半蝕 刻（half-etching)該金屬基板之該上表面，以在該第一 引線之下形成一引線部以及形成其底部連接於該引線部之 一晶片焊墊部；將一晶片附著在該晶片焊墊部上且藉由一 連接器（connector)將該晶片和該些第一引線電性連接；在 該金屬基板上形成一絕緣模製部（insulative molding portion)以掩埋該晶片與該連接器；以及蝕刻該金屬基板 之該底部以將該引線部和該晶片焊墊部短路 (short-circuit) ° 根據本發明一考量面之使用上述製程製造的一晶片封 裝件包括：與一晶片焊墊部間隔而設的一引線部，且該引 線部包含垂直部（vertical portions)和水平部 (horizontal portions);具導電性之第一引線（first leads)位於相鄰該晶片焊墊部的位置，且形成在該引線部 之該水平部的上表面上；具導電性之第二引線（sec〇nd leads)形成在該引線部之該垂直部的下表面上；一晶片形 成在該晶片焊墊部之上表面上；一連接器電性連接該晶片 201203411 與該些第-引線；以及-模製部’其支撐該弓|線部和該晶 片焊墊部’且掩埋該晶片和該連接器。—不規則圖案可形 成於該引線部、該晶片焊墊部、該些第一引線、以及該些 第一引線的至少一者的表面上。 〔實施例〕 以下將伴隨圖示詳細說明根據本發明之配置與作業。 在參照附圖之描述中，相同或等同的元件將以相同的元件 符號表示，且重覆的描述將不贅述。包含例如丨、2之類的 順序數字的名稱將用來描述不同的元件，但該元件將不限 定該名稱。而這些名稱之目僅用以與其他元件作區別。 圖2顯示根據本發明實施例之一晶片封裝件製造方法 的方塊圖。圖3顯示一晶片封裝件製造方法的剖面圖，其 分別對應於圖2之一晶片封裝件製造方法的方塊圖。 根據本發明之一實施例，請參照圖2和圖3，一晶片 封裝件的製造方法’首先，皆具有導電性之第一引線（f丨 leac[s)230和第二引線（second leads)240分別地形成在一 金屬基板200之上表面和下表面上。除了該些第一引線230 和該些第二引線240之外，更可形成一上晶片焊墊金屬部 210與一下晶片焊墊金屬部220。在此實施例中，第一引線 230作為内部引線而第二引線240作為外部引線。此實施 例中之第一引線230形成於金屬基板200之上表面，且比 金屬基板200下表面上的第二引線240設置在更内侧。否 則將如之後所描述，第一引線230可比金屬基板200下表 201203411 , &gt; 面上的第二引線240設置在更外側（參閱圖4)。 更特定而言，金屬基板200係作為電路實施之主要構 件。金屬基板200最好是以銅（Cu)所製成，而且可由如導 電銅合金（Cu alloy)、鐵（Fe)、或鐵合金（alloy of Fe) 所製成的金屬元件。此外，由於形成一薄膜基板時建議該 金屬基板200之厚度小於5mil，所以可以使用厚度小於10 mil之構件。所建議的構件200之兩侧塗佈一光阻膜 (photoresist film)，然後覆蓋一圖案光罩（pattern mask) 與暴露在光之下以形成一導線結合部（wire bonding portion)其包含第一引線230和上晶片焊墊金屬部210， 以及包括第二引線240與下晶片焊墊金屬部220之一焊墊 部（solder mounting pad portion)。在顯影期間從一光 接收部分（或非光接收部分）移除該光阻膜，且暴露該金屬 基板200。以鎳（Ni)電鍍暴露兩側的金屬基板200，然後再 電鍍訊號傳送最佳金屬的金（Au)。此外，可將鈀（Pd)電鍍 在一鎳（Ni)電鍍層上，將金（Au)電鍍在該鈀（Pd)電鍍層 上，以及電鍍取代鎳（Ni)、鈀（Pd)和金（Au)的銀（Ag)。一 電鍍層（plating layer)通常利用電鐘（electroplating) 所形成’但是可藉由無電電鍵（electroplating)或電嫂 與無電電鍍之組合方法所形成。再者，金屬基板200下表 面上之第二引線240和下晶片焊墊金屬部220可以錫（Sn) 和有機保焊劑（organic solderabi 1 ity preservative，0SP) 作表面處理以避免氧化。 11 201203411 ， &gt; 特別的是，一不規則圖案最好在一電鍵製程之前形成 在金屬基板200表面之至少一部分上。如果一不規則圖案 形成於接觸如第一引線230或第二引線240之電錢層區域 之表面，則可增強附著力。 或者，一不規則圖案可形成於已經形成第一弓丨線23q 第二引線240、以及上和下晶片焊墊金屬部210、220中至 少一·者之表面上。在此狀況下，可增強於後製程所形成的 模製部270的結合。 尤其是，如果例如第一引線230和第二引線24〇之— 金屬層包括一複數層，則可於各層之間形成一不規則圖案 以改善結合力。 之後，經由半蝕刻形成具有電路圖案形狀之一引線部 290和一晶片焊替部280(S2)。更特別是，該光阻膜係被移 除，然後再次塗覆一光阻膜用以形成電路圖案。雖然對塗 佈一液態光阻（LPR)膜而言並不成問題，但若是使用一乾膜 光阻（DFR)，則會因金屬基板200和該電鍍層（第一引線 230、第二引線240、以及上和下晶片焊墊金屬部210、220) 之間有一步驟差而可能會減低該光阻膜之黏著性。在此情 況下’則可以使用真空壓合（vacuum lamination)來改善黏 著性。一光接收部（或非光接收部）的光阻膜係經顯影、移 除、然後蝕刻。而執行蝕刻時不暴露金屬基板200是很重 要的。如果暴露出金屬基板200，之後進行的一微型電路 (microcircuit)將無法正確形成。因此，建議在垂直蝕 12 201203411 , 刻後金屬基板200剩餘的厚度在10至60//m的範圍。雖然 金屬基板200可小於1〇//m，但該金屬基板2〇〇可因此而 暴露出，因此需特別留意蝕刻製程。接著，執行圖案之形 成，以及執行用以完成電路之半蝕刻。藉由半蝕刻形成引 線部29G和晶片焊墊部，且引線部29()與晶片焊塾部 280之底部仍然處於連接狀態。此外，蝕刻引線部29〇以 得到從俯視時所需的電路圖案。另外，可由蝕刻過程中在 該曰曰片知墊部280上形成一晶片安裝凹部2〇，以調整晶片 封裝件的整體厚度。 之後’將一晶片250附著在晶片焊墊部280上，且利 用一導線260作為-連接器以連接至第一引線23()(S3)。 特另]的疋，5玄晶片250結合至半姓刻的晶片焊墊部2別的 晶片安裝凹部20上，且利用金線將晶片25〇和第一引線 230及/或上晶片焊墊金屬部21〇進行結合。如果需要，可 以㈣銅線來取代金線。然後晶片250和導線260由樹脂 模製化〇物（eXp〇Xym〇ldingc〇mp〇und)進行封裝而密封 在模製部270中（S4)。 =後’引線部290和晶片焊墊部藉由對金屬基板 ⑽之底部進行⑽而形成短路迴路（如士加也⑷ ()=細言之’利用包括金屬基板2〇〇下表面的第二引 線240和下晶片焊墊金屬部220作為一_拒焊（etching 2⑷’藉以形成引線部_作為水平部咖和垂直部 圖所示。引線部290之水平部290a具有如上述從 13 I · 201203411 俯視時所需的電路圖案。由於此種形式的引線部290不像 習知技術般具有一凸塊形狀，所以如果晶片250連接於接 近晶片桿墊部280之第一引線230，則該晶片250係經由 引線部290之水平部290a電性連接至第二引線240。在此 狀況下’水平部290a和垂直部290b之間之一連接區域之 寬度dl可大於第二引線的寬度d2。以此方式，第二引線 240可具有穩定結構。 上述結構能實現大幅降低導線260長度之優點。另 外’引線部290之水平部290a厚度可在最後步驟（S5)中進 行調整’且沒有後續的步驟會影響到已調整的水平部29〇a 厚度，因此增加產品的整體穩定性。除此之外，該導線形 狀電路圖案具有相較於傳統凸塊形狀電路圖案小很多之蚀 刻面積。所以可能避免由等向性蚀刻造成使該電路圖案間 距（Pitch)擴大之情形，從而實現一微型電路圖案。 圖4繪示根據本發明另一實施例之一晶片封裝件製造 方法。 本製程除了第一引線330設置在金屬基板300之外側 而第二引線340設置在金屬基板3〇〇相對内側之外，基本 上相似於如圖3所述之製程。 (a)首先，第一引線330和第二引線340藉由一電鍵製 程形成於金屬基板300上，其可由如圖3所說明之相同方 法所執行。一晶片焊墊金屬部320更可形成於金屬基板3〇〇 之下表面上。 201203411 、 * 之後如（b)所示，對金屬基板30〇之下表面進行蝕刻以 形成一引線部390 ’和如（c)所示之由触刻形成之一晶片安 裝部。（d)之後’將一晶片350裝設在金屬基板300、導線 接合、以及與例如環氧樹脂之一模製材料370進行模壓 (molded) ’然後藉由蝕刻下側將該外部導線、該引線部、 和該晶片焊墊部進行短路。如同圖3所說明之結構，引線 部390形成於内部導線330之下，且引線部39〇包括垂直 部（vertical portions)和水平部（h〇riz〇ntal p〇rti〇ns) 〇 雖然參考特定實施例說明與描述本發明，但應理解，熟習 此項技術者可想出將落入本發明之範疇内的眾多其他修改。本 發明之技浦料應侷限於财關，但應由附蚊申請 範圍和其等價來解釋。 ％ 【圖式簡單說明】 圖1顯示根據習知技術之一 圖； 片封裝件製造方法的剖 面 圖2顯示根據本發明實施例之一晶 方塊圖； 片封裝件製造方法的 園0顯不…的々蚵裝件製造方法的剖Θ 於圖2之一晶片封裝件製造方法的方塊圖；以及 =緣示根據本發明另—實關之m續件製造方 丹为、別對應 【主要元件符號說明】dl 連接區域寬度 15 201203411 d2 第二引線寬度 10、20 晶片安裝凹部 100 、 200 、 300 金屬基板 110 、 210 上晶片焊墊金屬部 120 、 220 下晶片焊墊金屬部 130 ' 230 &gt; 330 第一引線 140、240、340 第二引線 150 、 250 、 350 晶片 160 、 260 導線 170 、 270 、 370 模製部 180 、 280 晶片焊墊部 190 凸塊 290 、 390 引線部 290a 水平部 290b 垂直部 320 晶片焊墊金屬部 S1-S5 步驟 16201203411 ·, VI. Description of the Invention: [Technical Field of the Invention] The present invention claims priority to the Korean Patent No. 10-2010-0065776 filed on Jul. 08, 2010, which is incorporated herein by reference. In this article, for reference. The present invention relates to a method of fabricating a chip package and articles thereof. More specifically, it is a chip package manufacturing method and an article thereof that can realize a large number of signal transmission systems at low cost. [Prior Art] A semiconductor package is a program for electrically connecting individual wafers in a wafer to be used as a storage member in actual life, and the hermetic package protects the wafer from damage due to an external force. A wafer typically includes several dozen or hundreds of wafers printed with the same circuitry. Each wafer itself does not function as an electronic component, so it must be connected to the outside by wires to receive electronic signals from the outside and to transmit electronic signals operated on the wafer. Except because the wafer includes a microcircuit, the wafer can be easily damaged by moisture, dust, or external impact. Therefore, the wafers formed on the surface of the wafer cannot be regarded as a complete product until the wafers are mounted on a printed circuit board (P C B) as an electronic component. Accordingly, a packaging process is a process of packaging a wafer into a final product, so that the wafer on the wafer can be electrically connected and hermetically sealed to withstand an external force impact, so that it can be used as a complete electronic component. In semiconductor packaging, a lead frame plays an important role in providing 201203411 », mounting chips and transmitting/outputting signals, and the development of different shaped lead frames for highly integrated signal transmission continues to evolve. in. In a conventional lead frame, a die pad or I/O is formed by an etching technique or a press forming method. However, the use of conventional lead frame manufacturing methods to fabricate multiple-rows of leads for highly integrated semiconductor devices is not readily achievable. Figure 1 is a cross-sectional view showing a wafer package manufacturing process in accordance with the prior art. Referring to FIG. 1, a first lead 13A, a second lead 14A, an upper wafer pad metal portion 110, and a lower wafer pad metal portion 12 are formed on the upper surface and the lower surface (Si) of the metal substrate 100, And a bump 19 which is formed by half etching (S2). Next, a wafer 150 is mounted on a wafer mounting recess 10, and the wafer 150 is electrically connected to each of the inner leads 130 via a wire 160 (S3). Thereafter, a molding portion 170 for closing the wafer 150, the wire 160, and the contact region between the wire 160 and the first lead 130 is formed on an insuiative modling material (S4) ). Finally, the bottom of the metal substrate 100 is etched to form bumps 190 and a wafer pad portion 180 is formed (S5). However, since a large amount of gold (Au) is used for bonding the wires 160, the process of forming the bumps 190 is expensive. In addition, when a plurality of bumps 190 are formed by etching, and the limitation of the bump pitch is reduced due to isotropic etching. Further, the adhesion between the first and second lead wires 130, 140 and the metal substrate 100 and between the metal substrate 1 and the molded portion 201203411, 170 is easily weakened, thereby reducing reliability. SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above problems, and an object of the present invention is to provide a method for manufacturing a chip package which can reduce the cost caused by the use of excessive gold wires and make it feasible to utilize a micro pattern. And improve the reliability of the combination. (Technical Solution) According to one aspect of the present invention, a method of manufacturing a chip package is provided, the method comprising: forming a plurality of first leads each having conductivity on a metal substrate and a lower surface (fi rst 1 eads) and a plurality of second leads; semi-etching the upper surface of the metal substrate to form a lead portion under the first lead and forming a wafer pad whose bottom portion is connected to the lead portion Attaching a wafer to the wafer pad portion and electrically connecting the wafer and the first leads by a connector, and forming an insulating molding portion on the metal substrate Causing the wafer and the connector; and etching the bottom of the metal substrate to short-circuit the lead portion and the wafer pad portion in the first lead and the second lead forming process A plating step may be performed to arrange the first leads inside the second leads or the first leads to be disposed outside the second leads. The first leads and the second leads may be formed after forming an irregular pattern on at least a portion of the metal substrate. Or the upper surface of the irregular pattern 201203411 and the first non-twist lines of the following table are formed on the surface of at least one of the second leads, and the first leads and the at least ones The first bow lines or the second (five) layers, the silver (1⁄4) layer, the gold (10) layer, and the ❿ are formed of: in a layer or a plurality of layers. The stomach U and the copper (Cu) layer are more openable in the first lead and the second lead pad metal portions, and the method is formed into a top or bottom of the metal substrate. The surface and the crystallized surface formed on the lower surface of the metal substrate can thus be surface treated with an organic or solder resist (osp). Implementing a half of the surface of the metal substrate:: the thickness of the substrate behind the side is two in the short circuit of the wire bonding portion of the wafer, the lead portion can be formed by the lower surface of the metal substrate The T曰μ W file/, including the second leads and the lower plate tan gold &gt; 1 'forms a horizontal portion and a vertical portion for a tip solder resist (etChing reSiSt). In this case, the width of the - connecting portion between the horizontal portion and the vertical portion of the lead portion may be larger than the width of the second lead formed on the surface of the vertical portion. The chip package according to the present invention can be realized by the above-described process, and its configuration is as follows. Specifically, the chip package may include: a lead portion spaced apart from a wafer pad portion, and the lead portion includes vertical portions and horizontal portions; and conductive 201203411, a first lead is located adjacent to the solder fillet portion of the wafer, and is formed on an upper surface of the horizontal portion of the lead portion; and a second lead (S_d leadS) having conductivity is formed on the lead portion The lower surface of the vertical portion: upper; a wafer is formed on the upper surface of the wafer pad portion; a connector electrically connects the wafer and the first leads; and a molding portion that supports the lead And the wafer pad portion, and burying the wafer and the connector. An irregular pattern may be formed on a surface of at least one of the lead portion, the wafer pad portion, the first leads, and the second leads. Alternatively, the chip package according to the present invention may have a structure in which the first leads are disposed inside the second leads or the first leads are disposed outside the second leads. Further, the chip package may further include a surface treatment layer made of tin (Sn) or an organic solder resist (0SP) and formed on the surface of the second leads. Further, the present invention can realize a chip package in which a width of a connection portion between the horizontal portion and the vertical portion of the lead portion is larger than a width of the second lead formed on a surface of the vertical portion. In addition, the present invention can implement a chip package, wherein the first lead and the second lead include a nickel (Ni) layer, a silver (Ag) layer, a gold (Au) layer, a palladium (Pd) layer, and At least one or more of a layer of copper (Cu). According to the present invention, the distance between the wafer and the first lead can be reduced by forming a conventional bump-shaped I/O dies into a lead shape, resulting in cost reduction. Moreover, because of the lead shape 201203411, a large number of signal transmission systems can be reliably implemented in a miniature pattern. In addition, the stability of the product can be improved by the thickness of the lead portion of the final step in the process. [Embodiment] A method of manufacturing a chip package according to the present invention includes: forming a plurality of first leads and a plurality of second leads each having conductivity on a metal substrate and on a lower surface ( Second leads); half-etching the upper surface of the metal substrate to form a lead portion under the first lead and forming a bottom portion of the lead pad portion connected to the lead pad portion; Attaching to the wafer pad portion and electrically connecting the wafer and the first leads by a connector; forming an insulating molding portion on the metal substrate to bury the wafer And the connector; and etching the bottom of the metal substrate to short-circuit the lead portion and the wafer pad portion. A chip package manufactured using the above process according to the present invention includes: a lead portion of a wafer pad portion spaced apart, and the lead portion includes vertical portions and horizontal portions; a first lead having conductivity (first lea Ds) is located adjacent to the pad portion of the wafer and is formed on an upper surface of the horizontal portion of the lead portion; a second lead having conductivity is formed at the vertical portion of the lead portion a lower surface; a wafer is formed on the upper surface of the wafer pad portion; a connector electrically connects the wafer 201203411 with the first leads; and - a molded portion 'which supports the bow|line portion and the The wafer pad portion 'and buryes the wafer and the connector. An irregular pattern may be formed on a surface of the lead portion, the wafer pad portion, the first leads, and at least one of the first leads. [Embodiment] The configuration and operation according to the present invention will be described in detail below with reference to the drawings. The same or equivalent elements will be denoted by the same element symbols, and the repeated description will not be repeated. Names containing sequential numbers such as 丨, 2 will be used to describe different components, but the component will not be qualified for that name. The names of these names are only used to distinguish them from other components. 2 is a block diagram showing a method of fabricating a chip package in accordance with an embodiment of the present invention. Figure 3 is a cross-sectional view showing a method of fabricating a chip package, which corresponds to a block diagram of a method of fabricating a chip package of Figure 2, respectively. According to an embodiment of the present invention, referring to FIG. 2 and FIG. 3, a method for fabricating a chip package 'firstly, each having a conductive first lead (f丨leac[s) 230 and a second lead) 240 are formed on the upper surface and the lower surface of a metal substrate 200, respectively. In addition to the first leads 230 and the second leads 240, an upper wafer pad metal portion 210 and a lower wafer pad metal portion 220 may be formed. In this embodiment, the first lead 230 serves as an inner lead and the second lead 240 serves as an outer lead. The first lead 230 in this embodiment is formed on the upper surface of the metal substrate 200 and disposed on the inner side than the second lead 240 on the lower surface of the metal substrate 200. Otherwise, as will be described later, the first lead 230 may be disposed on the outer side of the second lead 240 on the surface of the metal substrate 200 in the lower table 201203411, &gt; (see Fig. 4). More specifically, the metal substrate 200 is a main component of the circuit implementation. The metal substrate 200 is preferably made of copper (Cu) and may be made of a metal member such as a copper alloy, iron (Fe), or an alloy of Fe. Further, since it is recommended that the thickness of the metal substrate 200 be less than 5 mils when forming a film substrate, a member having a thickness of less than 10 mil can be used. A suggested photoresist film is coated on both sides of the proposed member 200, and then covered with a pattern mask and exposed to light to form a wire bonding portion containing the first The lead 230 and the upper wafer pad metal portion 210, and a solder mounting pad portion including the second lead 240 and the lower wafer pad metal portion 220. The photoresist film is removed from a light receiving portion (or a non-light receiving portion) during development, and the metal substrate 200 is exposed. The metal substrate 200 on both sides is exposed by nickel (Ni) plating, and then electroplated to transmit the gold (Au) of the optimum metal. Further, palladium (Pd) may be electroplated on a nickel (Ni) plating layer, gold (Au) may be electroplated on the palladium (Pd) plating layer, and electroplating may be substituted for nickel (Ni), palladium (Pd), and gold ( Silver (Ag) of Au). A plating layer is usually formed using electroplating' but can be formed by a combination of electroplating or electroless plating. Further, the second lead 240 and the lower wafer pad metal portion 220 on the lower surface of the metal substrate 200 may be surface-treated with tin (Sn) and an organic solder amp preservative (0SP) to avoid oxidation. 11 201203411, &gt; In particular, an irregular pattern is preferably formed on at least a portion of the surface of the metal substrate 200 prior to a keying process. If an irregular pattern is formed on the surface of the pistol layer region such as the first lead 230 or the second lead 240, the adhesion can be enhanced. Alternatively, an irregular pattern may be formed on the surface of at least one of the upper and lower wafer pad metal portions 210, 220 where the first bow line 23q has been formed. In this case, the bonding of the molded portion 270 formed by the post-process can be enhanced. In particular, if, for example, the first lead 230 and the second lead 24 - the metal layer includes a plurality of layers, an irregular pattern can be formed between the layers to improve the bonding force. Thereafter, one of the lead portions 290 having a circuit pattern shape and a wafer soldering portion 280 (S2) are formed via half etching. More specifically, the photoresist film is removed, and then a photoresist film is applied again to form a circuit pattern. Although it is not a problem for coating a liquid photoresist (LPR) film, if a dry film photoresist (DFR) is used, the metal substrate 200 and the plating layer (the first lead 230, the second lead 240, There is a step difference between the upper and lower wafer pad metal portions 210, 220), which may reduce the adhesion of the photoresist film. In this case, vacuum lamination can be used to improve adhesion. The photoresist film of a light receiving portion (or non-light receiving portion) is developed, removed, and then etched. It is important that the metal substrate 200 is not exposed when etching is performed. If the metal substrate 200 is exposed, a microcircuit that is subsequently performed will not be formed correctly. Therefore, it is recommended that in the vertical etch 12 201203411, the remaining thickness of the metal substrate 200 is in the range of 10 to 60 / / m. Although the metal substrate 200 may be less than 1 Å/m, the metal substrate 2 may be exposed as a result, so that an etching process is particularly required. Next, the formation of the pattern is performed, and half etching to complete the circuit is performed. The lead portion 29G and the pad pad portion are formed by half etching, and the lead portion 29 () and the bottom portion of the wafer pad portion 280 are still in a connected state. Further, the lead portion 29 is etched to obtain a circuit pattern required from a plan view. Alternatively, a wafer mounting recess 2 can be formed on the die pad portion 280 during the etching process to adjust the overall thickness of the wafer package. Thereafter, a wafer 250 is attached to the pad pad portion 280, and a wire 260 is used as a connector to be connected to the first lead 23 () (S3). Specifically, the 5th wafer 250 is bonded to the other wafer mounting recess 20 of the wafer pad portion 2, and the wafer 25 and the first lead 230 and/or the upper wafer pad metal are used by the gold wire. Department 21〇 combines. If necessary, replace the gold wire with (4) copper wire. Then, the wafer 250 and the wire 260 are sealed by a resin molded article (eXp〇Xym〇ldingc〇mp〇und) and sealed in the molded portion 270 (S4). = After 'the lead portion 290 and the wafer pad portion are short-circuited by performing (10) on the bottom of the metal substrate (10) (eg, 士加也(4)()=detailedly, using the second surface including the lower surface of the metal substrate 2 The lead 240 and the lower wafer pad metal portion 220 are shown as a horizontal portion and a vertical portion as a horizontal portion 290a as a horizontal portion 290a. The horizontal portion 290a of the lead portion 290 has the above-mentioned from 13 I · 201203411 The circuit pattern required in a plan view. Since the lead portion 290 of this type does not have a bump shape as in the prior art, if the wafer 250 is attached to the first lead 230 adjacent to the wafer pad portion 280, the wafer 250 The second lead 240 is electrically connected to the second lead 240 via the horizontal portion 290a of the lead portion 290. In this case, the width d1 of the connecting portion between the horizontal portion 290a and the vertical portion 290b may be greater than the width d2 of the second lead. In this manner, the second lead 240 can have a stable structure. The above structure can realize the advantage of greatly reducing the length of the wire 260. In addition, the thickness of the horizontal portion 290a of the lead portion 290 can be adjusted in the last step (S5) 'and no subsequent The step affects the thickness of the adjusted horizontal portion 29〇a, thus increasing the overall stability of the product. In addition, the wire-shaped circuit pattern has a much smaller etching area than the conventional bump-shaped circuit pattern. A microcircuit pattern is realized by the isotropic etching to enlarge the pitch of the circuit pattern, thereby implementing a microcircuit pattern. Fig. 4 illustrates a method of fabricating a chip package according to another embodiment of the present invention. The lead 330 is disposed on the outer side of the metal substrate 300 and the second lead 340 is disposed on the opposite side of the metal substrate 3, substantially similar to the process as described in FIG. 3. (a) First, the first lead 330 and the second The lead wire 340 is formed on the metal substrate 300 by a key bonding process, which can be performed by the same method as illustrated in Fig. 3. A wafer pad metal portion 320 can be formed on the lower surface of the metal substrate 3, 201203411, * Thereafter, as shown in (b), the lower surface of the metal substrate 30 is etched to form a lead portion 390' and one of the wafer mounting portions is formed by etch as shown in (c). (d) Thereafter, a wafer 350 is mounted on the metal substrate 300, wire bonded, and molded with a molding material 370 such as epoxy resin, and then the external wire, the lead is etched by etching the lower side And the wafer pad portion is short-circuited. As with the structure illustrated in Fig. 3, the lead portion 390 is formed under the inner lead 330, and the lead portion 39 includes vertical portions and horizontal portions (h〇riz〇) While the invention has been illustrated and described with respect to the specific embodiments, it will be understood by those skilled in the <RTIgt; The technical material of the present invention should be limited to the fiscal, but should be interpreted by the scope of the application of the mosquito and its equivalent. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a diagram according to a conventional technique; a cross-sectional view 2 of a method for manufacturing a chip package shows a crystal block diagram according to an embodiment of the present invention; FIG. 2 is a block diagram of a method for fabricating a chip package of FIG. 2; and = the edge is shown in accordance with the present invention. Description] dl connection region width 15 201203411 d2 second lead width 10, 20 wafer mounting recesses 100, 200, 300 metal substrate 110, 210 upper wafer pad metal portion 120, 220 lower wafer pad metal portion 130 '230 &gt; 330 First lead 140, 240, 340 second lead 150, 250, 350 wafer 160, 260 lead 170, 270, 370 molded portion 180, 280 wafer pad portion 190 bump 290, 390 lead portion 290a horizontal portion 290b vertical portion 320 Wafer Pad Metal Section S1-S5 Step 16

Claims (1)

201203411 ,， 七、申請專利範圍： 1. --種晶片封裝件製造方法，該方法包括： 在一金屬基板之上表面和下表面形成具有導電性 之多個第一引線和多個第二引線； 半蝕刻該金屬基板之上表面以在該些第一引線之 下形成一引線部以及形成底部連接至該引線部之一晶 片焊墊部； 將一晶片附著於該晶片焊墊部上且藉由一連接器 將該晶片和該些第一引線進行電性連接； 在該金屬基板上形成一絕緣模製部以掩埋該曰 和該連接器；以及 對該金屬基板之底部執行钮刻以使該引線部和該 晶片焊墊部短路。 μ =申請專利_第丨項所述之晶片封裝件製造方法，盆 I該些第一引線和該些第二引線之形成過程中，執： :電鍍製程使該些第一引線設置在該些第二化線的内 3.如申請專利範圍第i項所述之晶 中:些第一引線和該些第二引線之形成過 ^中法 執: :電錢餘使該些第-引線設置在該些第二引線= 4.如申請專利範圍第1項所述之晶片封裝件製造方味 中在該金屬基板之表面至少一部分上形成一 / ，其 不規則圖 17 201203411 、, 案後，再形成該些第1線和該些第二引線。 5. 如申請專·圍第1項所述之晶片封裝㈣造方法，其 中一不規則圖案在分別形成於該金屬基板之上表面和 下表面的該些第一引線或該些第二引線形成後，形成 在該些第-引線和該些第二引線之至少—者的表面 上。 6. 如申請專利範圍第！項所述之晶片封裝件製造方法1 中該些第-引線和該些第二引線中至少一者由錄層、 銀層、金層、叙層、以及銅層中的—層或多層所形成。 7. 如申請專利範圍第2項所述之晶片·件製造方法，其 中該些第-引線和該些第二引線之形成過程中，一晶 片焊墊金屬部更形成於該金屬基板之上表面或下: 面。 8. 如申請專㈣㈣6項所述之晶片封裝件製造方法，更 包括對在該金屬基板之下表面形成之該晶片焊塾部和 該些第二引線以錫或有機保焊劑進行表面處理。 9. 如申請專利範圍第2項所述之晶片封裝件製造方法，其 中執行該金屬基板之上表面的半蝕刻以及該金屬基板 之下表面的蝕刻，使蝕刻後的該金屬基板具有1〇至 60 之厚度。 10·如申請專利範圍第2項所述之晶片封裝件製造方法， 其中在該引線部與該晶片焊墊部之短路迴路中，該引 線部利用包括該金屬基板的下表面的該些第二引線和 1 » 201203411 該下晶片桿墊金屬部形成多個水平部和多個垂直部作 為一钮刻拒焊。 U.如申請專㈣圍第10項所狀W封裝件製造方 法’其中該引線部的該些水平部和該些垂直部之間的 連接刀寬度係大於形成在該些垂直部表面上的該些 第二引線的寬度。 12. —種晶片封裝件包括： 與-晶片烊墊部間隔而設的—引線部，且該引線部 〇括夕個垂直部和多個水平部； 八導電H之夕個第—引線位於相鄰該晶片焊塾部 的位置’且形成在該引線部之該水平部的上表面上； …導電f生之多個第二引線形成在該引線部之該垂 直部的下表面上； 一晶片形成在該晶片焊墊部之上表面上； 一模製部支揮該引線部和該晶片烊塾部，且掩埋該 晶片和該連接器。 3·如申请專利範圍第12項所述之晶片封裝件，其中一不 規則圖案形成於該引線部、該晶片焊墊部、該些第一 引線、以及該些第二引線中至少一者之表面上。 丨4.如申請專利範圍第12項所述之晶片封裝件，其中該些 第一引線設置在該些第二引線之内側。 X一 丨5.如申請專利範圍第12項所述之晶片封震件，其中該些 第—引線設置在該些第二引線之外側。 &quot;一 201203411 . &gt; 16.如申請專利範圍第12項所述之晶片封裝件，更包括在 該些第二引線之表面由錫和有機保焊劑製成之一表面 處理層。 Π.如申請專利範圍第12項所述之晶片封裝件，其中該引 線部的該些水平部和該些垂直部之間的連接部分寬度 係大於形成在該些垂直部表面上的該些第二引線的寬 度。 18.如申請專利範圍第12項所述之晶片封裝件，其中該些 第一引線和該些第二引線包括錄層、銀層、金層、I巴 層、以及銅層的一層或多層。201203411,, VII. Patent application scope: 1. A method for manufacturing a chip package, the method comprising: forming a plurality of first leads and a plurality of second leads having conductivity on a top surface and a lower surface of a metal substrate Semi-etching the upper surface of the metal substrate to form a lead portion under the first leads and forming a bottom portion connected to the wafer pad portion of the lead portion; attaching a wafer to the wafer pad portion and borrowing Electrically connecting the wafer and the first leads by a connector; forming an insulating molding portion on the metal substrate to bury the cymbal and the connector; and performing a button on the bottom of the metal substrate to enable The lead portion and the wafer pad portion are short-circuited. The method of manufacturing the chip package described in the above-mentioned application, the forming process of the first lead and the second lead of the basin I, the electroplating process: the electroplating process is performed on the first leads The inside of the second line 3. As in the crystal described in the scope of claim i: some of the first lead and the second lead are formed by the method: the electric charge makes the first lead set The second lead=4 is formed on at least a part of the surface of the metal substrate in the manufacturing of the chip package according to claim 1, wherein the irregularity is shown in FIG. 17 201203411, after the case, The first lines and the second leads are formed again. 5. The method of claim 4, wherein the irregular pattern is formed on the first leads or the second leads respectively formed on the upper surface and the lower surface of the metal substrate. Thereafter, it is formed on the surface of at least the first lead and the second lead. 6. If you apply for a patent scope! The method of manufacturing the chip package of claim 1 wherein at least one of the first lead and the second lead is formed by a layer or a plurality of layers in a recording layer, a silver layer, a gold layer, a layer, and a copper layer. . 7. The method of manufacturing a wafer according to the second aspect of the invention, wherein, in the forming of the first lead and the second lead, a metal pad of the wafer pad is formed on the upper surface of the metal substrate. Or below: face. 8. The method of manufacturing a chip package according to the above (4), wherein the wafer soldering portion and the second leads formed on a lower surface of the metal substrate are surface-treated with tin or an organic soldering agent. 9. The method of manufacturing a chip package according to claim 2, wherein the half etching of the upper surface of the metal substrate and the etching of the lower surface of the metal substrate are performed, so that the etched metal substrate has 1 〇 to 60 thickness. The method of manufacturing a chip package according to claim 2, wherein in the short circuit of the lead portion and the wafer pad portion, the lead portion utilizes the second portions including a lower surface of the metal substrate Lead and 1 » 201203411 The lower wafer pad metal portion forms a plurality of horizontal portions and a plurality of vertical portions as a button solder joint. U. The method of manufacturing a W package according to claim 10, wherein the horizontal portion between the horizontal portion and the vertical portion of the lead portion is larger than the surface formed on the surface of the vertical portion The width of these second leads. 12. The chip package comprises: a lead portion spaced apart from the wafer pad portion, and the lead portion includes a vertical portion and a plurality of horizontal portions; Adjacent to the position of the wafer pad portion and formed on the upper surface of the horizontal portion of the lead portion; a plurality of second leads electrically conductive are formed on the lower surface of the vertical portion of the lead portion; Formed on the upper surface of the wafer pad portion; a molding portion supports the lead portion and the wafer defect portion, and bury the wafer and the connector. 3. The chip package of claim 12, wherein an irregular pattern is formed on at least one of the lead portion, the wafer pad portion, the first leads, and the second leads On the surface. The chip package of claim 12, wherein the first leads are disposed inside the second leads. The wafer sealer of claim 12, wherein the first lead is disposed on an outer side of the second lead. The chip package of claim 12, further comprising a surface treatment layer made of tin and an organic soldering agent on the surface of the second leads. The chip package of claim 12, wherein a width of the connecting portion between the horizontal portion and the vertical portion of the lead portion is greater than the plurality of portions formed on the surface of the vertical portion The width of the two leads. The chip package of claim 12, wherein the first leads and the second leads comprise one or more layers of a recording layer, a silver layer, a gold layer, an I ba layer, and a copper layer.
TW100114085A 2010-07-08 2011-04-22 Manufacturing method of chip package and chip package manufactured using the same TW201203411A (en)

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KR101631558B1 (en) * 2014-12-05 2016-06-24 주식회사 에스에프에이반도체 routable QFN semiconductor package and method thereof

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TWI614861B (en) * 2015-01-30 2018-02-11 矽品精密工業股份有限公司 Electronic package structure and the manufacture thereof

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