WO2012005435A9 - Manufacturing method of chip package and chip package manufactured using the same - Google Patents

Manufacturing method of chip package and chip package manufactured using the same Download PDF

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Publication number
WO2012005435A9
WO2012005435A9 PCT/KR2011/002628 KR2011002628W WO2012005435A9 WO 2012005435 A9 WO2012005435 A9 WO 2012005435A9 KR 2011002628 W KR2011002628 W KR 2011002628W WO 2012005435 A9 WO2012005435 A9 WO 2012005435A9
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WO
WIPO (PCT)
Prior art keywords
leads
metal substrate
die pad
chip
lead portion
Prior art date
Application number
PCT/KR2011/002628
Other languages
French (fr)
Other versions
WO2012005435A1 (en
Inventor
Hyung Eui Lee
Chung Sik Park
Hyun A Chun
Sai Ran Eom
Original Assignee
Lg Innotek Co., Ltd.
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Publication date
Application filed by Lg Innotek Co., Ltd. filed Critical Lg Innotek Co., Ltd.
Publication of WO2012005435A1 publication Critical patent/WO2012005435A1/en
Publication of WO2012005435A9 publication Critical patent/WO2012005435A9/en

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
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    • H01L23/495—Lead-frames or other flat leads
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Definitions

  • the present invention relates to a manufacturing method of a chip package and a chip package manufactured using the same, and more particularly, to a manufacturing method of a chip package, which can stably realize a large number of signal transmission systems at low cost, and a chip package manufactured using the same.
  • Semiconductor packaging is a procedure in which individual chips fabricated in a wafer process are electrically connected for use as storage parts in real life and hermetically packaged for protection from external impacts.
  • a sheet of wafer usually includes several dozens or several hundreds of chips with the same electrical circuits printed thereon.
  • Each chip itself cannot function as an electronic part.
  • it is necessary to provide electric wires connected to the exterior to receive electrical signals from the exterior and transmit the electrical signals operated in the chips.
  • the chip since the chip contains micro-circuits, the chip may be easily damaged by moisture, dust, and external impacts. Consequently, the chips formed on the surface of the wafer cannot be regarded as complete products until they are mounted as electronic parts on a printed circuit board (PCB).
  • PCB printed circuit board
  • a packaging process is a procedure of packaging chips into final products so that an electrical connection is provided between the chips on the wafer and hermetically packaged to endure external impacts to thereby render them usable as complete electronic components.
  • a lead frame plays an important role of providing an input/output pad for mounting a chip and transmitting signals, and the development of leads frames of various shapes for high-integrity signal transmission is underway.
  • FIG. 1 is a cross-sectional view showing a manufacturing process of a chip package according to the prior art.
  • first leads 130, second leads 140, an upper die pad metallic portion 110, and a lower die pad metallic portion 120 are formed on the top and bottom surfaces of a metal substrate 100 (S1), and a bump 190 is formed by half-etching (S2).
  • a chip 150 is mounted in a chip mounting recess 10, and the chip 150 is electrically connected to the respective inner leads 130 by a wire 160 (S3).
  • a molding portion 170 for molding the chip 150, the wire 160, and a contact area between the wire 160 and the first leads 130 is formed of an insulative molding material (S4).
  • the bottom of the metal substrate 100 is etched to complete the formation of the bump 190 and to form a die pad portion 180 (S5).
  • the cost of the manufacturing process using the formation of the bump 190 is high due to high amount of gold (Au) used for bonding the wire 160.
  • Au gold
  • the adhesive force between the first and second leads 130 and 140 and the metal substrate 100 and between the metal substrate 100 and the molding portion 170 is easily reduced, thus lowering the reliability.
  • the present invention has been made in an effort to solve the aforementioned problems, and it is an object of the present invention to provide a manufacturing method of a chip package, which reduces costs incurred by excessive use of gold wire, enables the use of a micro pattern, and improves bonding reliability.
  • a manufacturing method of a chip package comprising: forming first leads and second leads, both having conductivity, on the top and bottom surfaces of a metal substrate; half-etching the top surface of the metal substrate to form a lead portion under the first leads and to form a die pad portion whose bottom is connected to the lead portion; attaching a chip onto the die pad portion and electrically connecting the chip and the first leads by a connector; forming an insulative molding portion on the metal substrate to bury the chip and the connector; and etching the bottom of the metal substrate to short-circuit the lead portion and the die pad portion.
  • a plating process may be carried out such that the first leads are disposed inwardly of the second leads or the first leads are disposed outwardly of the second leads.
  • the first leads and the second leads may be formed after forming an irregular pattern on at least part of the surface of the metal substrate.
  • an irregular pattern may be formed on the surface of at least either of the first leads and the second leads after forming the first leads and the second leads, respectively, on the top and bottom surfaces of the metal substrate.
  • At least either of the first leads and the second leads may be formed of one or more of an Ni layer, an Ag layer, an Au layer, a Pd layer, and a Cu layer.
  • a die pad metallic portion may be further formed on the top or bottom of the metal substrate.
  • the method may further comprise surface-treating the die pad portion and the second leads, which are formed on the bottom surface of the metal substrate, with Sn or OSP.
  • Half-etching of the top surface of the metal substrate and etching of the bottom surface thereof may be carried out such that the metal substrate left after etching is 10 to 60 ⁇ m thick.
  • the lead portion may formed as horizontal portions and vertical portions by using portions, excluding the second leads and the lower die pad metallic portion, of the bottom surface of the metal substrate as an etching resist.
  • the width of a connecting portion between the horizontal portions and vertical portions of the lead portion may be greater than the width of the second leads formed on the surfaces of the vertical portions
  • the chip package according to the present invention to be realized by the above manufacturing process is configured as follows.
  • the chip package may comprise: a lead portion spaced apart from a die pad portion, and including vertical portions and horizontal portions; conductive first leads positioned adjacent to the die pad portion, and formed on the top surfaces of the horizontal portions of the lead portion; conductive second leads formed on the bottom surfaces of the vertical portions of the lead portion; a chip formed on the top surface of the die pad portion; a connector electrically connecting the chip and the first leads; and a molding portion supporting the lead portion and the die pad portion, and burying the chip and the connector.
  • An irregular pattern may be formed on the surface of at least either of the lead portion, the die pad portion, the first leads, and the second leads.
  • the chip package according to the present invention may have a structure in which the first leads are disposed inwardly of the second leads or the first leads are disposed outwardly of the second leads.
  • the chip package may further comprise a surface treatment layer made of Sn and OSP on the surfaces of the second leads.
  • the present invention can realize a chip package in which the width of a connecting portion between the horizontal portions and vertical portions of the lead portion is greater than the width of the second leads formed on the surfaces of the vertical portions.
  • the present invention can realize a chip package in which the first and second leads comprise one or more of an Ni layer, an Ag layer, an Au layer, a Pd layer, and a Cu layer.
  • the distance between a chip and first leads can be reduced by forming a conventional bump-shaped I/O pad in a lead shape, thus lead to cost reduction. Moreover, a large number of signal transmission systems can be reliably realized in a micro-pattern due to the lead shape. Moreover, the stability of the product can be improved by treating the thickness of the lead portion in the final step of the process.
  • FIG. 1 is a cross-sectional view showing a manufacturing process of a chip package according to the prior art
  • FIG. 2 shows block diagrams of a manufacturing method of a chip package according to one exemplary embodiment of the present invention
  • FIG. 3 shows cross-sectional views of the manufacturing method of a chip package, respectively corresponding to the block diagrams of the manufacturing method of a chip package of FIG. 2;
  • FIG. 4 illustrates a manufacturing process of a chip packaging according to another exemplary embodiment of the present invention
  • a manufacturing process of a chip package comprises: forming first leads and second leads, both having conductivity, on the top and bottom surfaces of a metal substrate; half-etching the top surface of the metal substrate to form a lead portion under the first leads and to form a die pad portion whose bottom is connected to the lead portion; attaching a chip onto the die pad portion and electrically connecting the chip and the first leads by a connector; forming an insulative molding portion on the metal substrate to bury the chip and the connector; and etching the bottom of the metal substrate to short-circuit the lead portion and the die pad portion.
  • a chip package manufactured using the above process according to one aspect of the present invention comprise: a lead portion spaced apart from a die pad portion, and including vertical portions and horizontal portions; conductive first leads positioned adjacent to the die pad portion, and formed on the top surfaces of the horizontal portions of the lead portion; conductive second leads formed on the bottom surfaces of the vertical portions of the lead portion; a chip formed on the top surface of the die pad portion; a connector electrically connecting the chip and the first leads; and a molding portion supporting the lead portion and the die pad portion, and burying the chip and the connector.
  • An irregular pattern may be formed on the surface of at least either of the lead portion, the die pad portion, the first leads, and the second leads.
  • FIG. 2 shows block diagrams of a manufacturing method of a chip package according to one exemplary embodiment of the present invention.
  • FIG. 3 shows cross-sectional views of the manufacturing method of a chip package, respectively corresponding to the block diagrams of the manufacturing method of a chip package of FIG. 2.
  • first leads 230 and second leads 240 are respectively formed on the top and bottom surfaces of a metal substrate 200.
  • an upper die pad metallic portion 210 and a lower die pad metallic portion 220 may be further formed.
  • the first leads 230 serve as inner leads
  • the second leads 240 serve as outer leads.
  • the first leads 230 are formed on the top surface of the metal substrate 200 and disposed more inwardly than the second leads 240 on the bottom surface of the metal substrate 200. Otherwise, as will described later, the first leads 230 may be disposed more outwardly than the second leads 240 on the bottom surface of the metal substrate 200 (see FIG. 4).
  • the metal substrate 200 is prepared as a primary member for circuit implementation.
  • the metal substrate 200 is preferably made of Cu, and may be a metallic member such as a conductive Cu alloy, Fe, or an alloy of Fe.
  • the thickness of the metal substrate 200 is less than 5 mil for the formation of a thin film substrate, a member having a thickness of less than 10 mil can be used.
  • Both sides of the suggested member 200 are coated with a photoresist film, and then covered with a pattern mask and exposed to light to form a wire bonding portion including the first leads 230 and the upper die pad metallic portion 210 and a solder mounting pad portion including the second leads 240 and the lower die pad metallic portion 220.
  • the photoresist film is removed from a light receiving portion (or non-light receiving portion) during development, and the metal substrate 200 is exposed.
  • the metal substrate 200 exposed to both sides is plated with Ni, and then plated with Au known to be the best metal for signal transmission.
  • Pd may be plated on an Ni plating layer
  • Au may be plated on the Pd plating layer
  • Ag instead of Ni, Pd, and Au, may be plated.
  • a plating layer is usually formed by electroplating, but may be formed by electroless plating or a combination of electroplating and electroless plating.
  • the second leads 240 and lower die pad metallic portion 220 on the bottom surface of the metal substrate 200 may be surface-treated with Sn and OSP (organic solderability preservative) to prevent oxidization.
  • Sn and OSP organic solderability preservative
  • an irregular pattern is formed on at least part of the surface of the metal substrate 200 before a plating process. If an irregular pattern is formed on the surfaces of regions contacting the plating layer such as the first leads 230 or the second leads 240, the adhesive force can be strengthened.
  • an irregular pattern may be formed on the surface of at least either of the first leads 230, second leads 240, and upper and lower die pad metallic portions 210 and 220 that have been already formed. In this case, bonding with the molding portion 270 to be formed later can be strengthened.
  • a metallic layer such as the first leads 230 and the second leads 240, comprises a plurality of layers
  • an irregular pattern may be formed between the layers to thus improve the bonding force.
  • a lead portion 290 having a circuit pattern shape and a die pad portion 280 are formed by half-etching (S2). More particularly, the photoresist film is removed, and then a photoresist film is coated over again for circuit pattern formation.
  • a liquid photoresist (LPR) film the use of a dry film photoresist (DFR) may deteriorate the adhesion of the photoresist film due to a step difference between the metal substrate 200 and the plating layer (first leads 230, second leads 240, and upper and lower die pad metallic portions 210 and 220). In this case, the adhesion can be improved by vacuum lamination.
  • a light receiving portion (or non-light receiving portion) of the photoresist film is developed, removed, and then etched. It is important that the etching be performed so as not to expose the metal substrate 200. In case that the metal substrate 200 is exposed, the formation of a micro circuit to be conducted later will not be properly done. It is recommended that the thickness of the metal substrate 200 left after vertical etching ranges from 10 to 60 ⁇ m. Although the metal substrate 200 may be less than 10 ⁇ m, the metal substrate 200 may be exposed and therefore care must be taken during the etching process. Next, pattern formation is performed, and half-etching is performed for circuit implementation.
  • the lead portion 290 and the die pad portion 280 are formed, and the lead portion 290 and the bottom of the die pad portion 280 are still connected. Moreover, the lead portion 290 is etched to have a desired circuit pattern when viewed from the top. In addition, the overall thickness of the chip package can be adjusted by forming a chip mounting recess 20 in the die pad portion 280 during etching.
  • a chip 250 is attached onto the die pad portion 280, and connected to the first leads 230 by a wire 260 as a connector (S3).
  • the chip 250 is bonded onto the chip mounting recess 20 of the half-etched die pad portion 280, and wire bonding between the chip 250 and the first leads 230 and/or upper die pad metallic portion 210 is performed using gold lines. If necessary, copper lines can be used instead of the gold lines.
  • the chip 250 and the wire 260 are buried in the molding portion 270 by being encapsulated by an epoxy molding compound (S4).
  • the lead portion 290 and the die pad portion 280 are short-circuited by etching the bottom of the metal substrate 200 (S5).
  • half-etching is performed using portions, excluding the second leads 240 and the lower die pad metallic portion 220, of the bottom surface of the metal substrate 200 as an etching resist, thereby forming the lead portion 290 as horizontal portions 290a and vertical portions 290b as shown in the drawing.
  • the horizontal portions 290a of the lead portion 290 have a desired circuit pattern as discussed above when viewed from the top.
  • the lead portion 290 of this type does not have a bump shape as in the prior art, if the chip 250 is connected to the first leads 230 close to the die pad portion 280, the chip 250 is electrically connected to the second leads 240 via the horizontal portions 290a of the lead portion 290.
  • the width d1 of a connecting region between the horizontal portion 290a and the vertical portion 290b may be greater than the width d2 of the second lead. In this way, the second leads can have a stable structure.
  • the above-described structure can realize the advantage of a considerable reduction in the length of the wire 260.
  • the thickness of the horizontal portions 290a of the lead portion 290 is adjusted in the final step (S5), and there is no subsequent step which will affect the thickness of the adjusted horizontal portions 290a, thus enhancing the overall stability of the product.
  • the lead-shaped circuit pattern has a much smaller etched area as compared to the conventional bump-shaped circuit pattern. Thus, it is possible to prevent the pitch of the circuit pattern from being widened due to isotropic etching, thereby realizing a micro-circuit pattern.
  • FIG. 4 illustrates a manufacturing process of a chip packaging according to another exemplary embodiment of the present invention.
  • first leads 330 are disposed at outer sides of the metal substrate and second leads 340 are disposed at relatively inner sides of a metal substrate 300.
  • the first leads 330 and the second leads 340 are formed on the metal substrate 300 by a plating process, which can be performed using the same method as described in FIG. 3.
  • a die pad metallic portion 320 may be further formed on the bottom surface of the metal substrate 300.
  • the bottom surface of the metal substrate 300 is etched to form a lead portion 390, and, as shown in (c), a chip mounting portion is formed by etching.
  • a chip 350 is mounted on the metal substrate 300, wire-bonded, and molded with a molding material 370 such as epoxy, and then the outer leads, the lead portion, and the die pad portion are short-circuited by etching the lower side.
  • the lead portion 390 is formed under the inner leads 330, and the lead portion 390 comprises vertical portions and horizontal portions.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The present invention relates to a manufacturing method of a chip package, the method comprising: forming first leads and second leads, both having conductivity, on the top and bottom surfaces of a metal substrate; half-etching the top surface of the metal substrate to form a lead portion under the first leads and to form a die pad portion whose bottom is connected to the lead portion; attaching a chip onto the die pad portion and electrically connecting the chip and the first leads by a connector; forming an insulative molding portion on the metal substrate to bury the chip and the connector; and etching the bottom of the metal substrate to short-circuit the lead portion and the die pad portion, and a chip package manufactured using the same. Accordingly, the distance between a chip and first leads can be reduced by forming a conventional bump-shaped I/O pad in a lead shape, thus lead to cost reduction. Moreover, a large number of signal transmission systems can be reliably realized in a micro-pattern due to the lead shape. Moreover, the stability of the product can be improved by treating the thickness of the lead portion in the final step of the process.

Description

MANUFACTURING METHOD OF CHIP PACKAGE AND CHIP PACKAGE MANUFACTURED USING THE SAME
The present invention relates to a manufacturing method of a chip package and a chip package manufactured using the same, and more particularly, to a manufacturing method of a chip package, which can stably realize a large number of signal transmission systems at low cost, and a chip package manufactured using the same.
Semiconductor packaging is a procedure in which individual chips fabricated in a wafer process are electrically connected for use as storage parts in real life and hermetically packaged for protection from external impacts.
A sheet of wafer usually includes several dozens or several hundreds of chips with the same electrical circuits printed thereon. Each chip itself cannot function as an electronic part. Thus, it is necessary to provide electric wires connected to the exterior to receive electrical signals from the exterior and transmit the electrical signals operated in the chips. In addition, since the chip contains micro-circuits, the chip may be easily damaged by moisture, dust, and external impacts. Consequently, the chips formed on the surface of the wafer cannot be regarded as complete products until they are mounted as electronic parts on a printed circuit board (PCB). Accordingly, a packaging process is a procedure of packaging chips into final products so that an electrical connection is provided between the chips on the wafer and hermetically packaged to endure external impacts to thereby render them usable as complete electronic components.
In fabricating a semiconductor package, a lead frame plays an important role of providing an input/output pad for mounting a chip and transmitting signals, and the development of leads frames of various shapes for high-integrity signal transmission is underway.
In a common lead frame, a die pad or I/O pad is formed by an etching technique or stamping method. However, it is not easy to form multiple rows of leads required for the high integration of semiconductor devices by using a conventional manufacturing method of a lead frame. FIG. 1 is a cross-sectional view showing a manufacturing process of a chip package according to the prior art. Referring to FIG. 1, first leads 130, second leads 140, an upper die pad metallic portion 110, and a lower die pad metallic portion 120 are formed on the top and bottom surfaces of a metal substrate 100 (S1), and a bump 190 is formed by half-etching (S2). Next, a chip 150 is mounted in a chip mounting recess 10, and the chip 150 is electrically connected to the respective inner leads 130 by a wire 160 (S3). Thereafter, a molding portion 170 for molding the chip 150, the wire 160, and a contact area between the wire 160 and the first leads 130 is formed of an insulative molding material (S4). Finally, the bottom of the metal substrate 100 is etched to complete the formation of the bump 190 and to form a die pad portion 180 (S5).
However, the cost of the manufacturing process using the formation of the bump 190 is high due to high amount of gold (Au) used for bonding the wire 160. Moreover, when forming a plurality of bumps 190 by etching, there is a limitation in reducing pitches between the bumps because of isotropic etching. In addition, the adhesive force between the first and second leads 130 and 140 and the metal substrate 100 and between the metal substrate 100 and the molding portion 170 is easily reduced, thus lowering the reliability.
The present invention has been made in an effort to solve the aforementioned problems, and it is an object of the present invention to provide a manufacturing method of a chip package, which reduces costs incurred by excessive use of gold wire, enables the use of a micro pattern, and improves bonding reliability.
According to one aspect of the present invention, there is provided a manufacturing method of a chip package, the method comprising: forming first leads and second leads, both having conductivity, on the top and bottom surfaces of a metal substrate; half-etching the top surface of the metal substrate to form a lead portion under the first leads and to form a die pad portion whose bottom is connected to the lead portion; attaching a chip onto the die pad portion and electrically connecting the chip and the first leads by a connector; forming an insulative molding portion on the metal substrate to bury the chip and the connector; and etching the bottom of the metal substrate to short-circuit the lead portion and the die pad portion.
In the formation of the first leads and the second leads, a plating process may be carried out such that the first leads are disposed inwardly of the second leads or the first leads are disposed outwardly of the second leads.
The first leads and the second leads may be formed after forming an irregular pattern on at least part of the surface of the metal substrate. Alternatively, an irregular pattern may be formed on the surface of at least either of the first leads and the second leads after forming the first leads and the second leads, respectively, on the top and bottom surfaces of the metal substrate.
At least either of the first leads and the second leads may be formed of one or more of an Ni layer, an Ag layer, an Au layer, a Pd layer, and a Cu layer.
In the formation of the first leads and the second leads, a die pad metallic portion may be further formed on the top or bottom of the metal substrate.
The method may further comprise surface-treating the die pad portion and the second leads, which are formed on the bottom surface of the metal substrate, with Sn or OSP.
Half-etching of the top surface of the metal substrate and etching of the bottom surface thereof may be carried out such that the metal substrate left after etching is 10 to 60μm thick.
In the short-circuiting of the lead portion and the die pad portion, the lead portion may formed as horizontal portions and vertical portions by using portions, excluding the second leads and the lower die pad metallic portion, of the bottom surface of the metal substrate as an etching resist. In this case, the width of a connecting portion between the horizontal portions and vertical portions of the lead portion may be greater than the width of the second leads formed on the surfaces of the vertical portions
The chip package according to the present invention to be realized by the above manufacturing process is configured as follows.
Specifically, the chip package may comprise: a lead portion spaced apart from a die pad portion, and including vertical portions and horizontal portions; conductive first leads positioned adjacent to the die pad portion, and formed on the top surfaces of the horizontal portions of the lead portion; conductive second leads formed on the bottom surfaces of the vertical portions of the lead portion; a chip formed on the top surface of the die pad portion; a connector electrically connecting the chip and the first leads; and a molding portion supporting the lead portion and the die pad portion, and burying the chip and the connector.
An irregular pattern may be formed on the surface of at least either of the lead portion, the die pad portion, the first leads, and the second leads.
Alternatively, the chip package according to the present invention may have a structure in which the first leads are disposed inwardly of the second leads or the first leads are disposed outwardly of the second leads.
Moreover, the chip package may further comprise a surface treatment layer made of Sn and OSP on the surfaces of the second leads.
In addition, the present invention can realize a chip package in which the width of a connecting portion between the horizontal portions and vertical portions of the lead portion is greater than the width of the second leads formed on the surfaces of the vertical portions.
Furthermore, the present invention can realize a chip package in which the first and second leads comprise one or more of an Ni layer, an Ag layer, an Au layer, a Pd layer, and a Cu layer.
According to the present invention, the distance between a chip and first leads can be reduced by forming a conventional bump-shaped I/O pad in a lead shape, thus lead to cost reduction. Moreover, a large number of signal transmission systems can be reliably realized in a micro-pattern due to the lead shape. Moreover, the stability of the product can be improved by treating the thickness of the lead portion in the final step of the process.
FIG. 1 is a cross-sectional view showing a manufacturing process of a chip package according to the prior art;
FIG. 2 shows block diagrams of a manufacturing method of a chip package according to one exemplary embodiment of the present invention;
FIG. 3 shows cross-sectional views of the manufacturing method of a chip package, respectively corresponding to the block diagrams of the manufacturing method of a chip package of FIG. 2; and
FIG. 4 illustrates a manufacturing process of a chip packaging according to another exemplary embodiment of the present invention;
A manufacturing process of a chip package according to one aspect of the present invention comprises: forming first leads and second leads, both having conductivity, on the top and bottom surfaces of a metal substrate; half-etching the top surface of the metal substrate to form a lead portion under the first leads and to form a die pad portion whose bottom is connected to the lead portion; attaching a chip onto the die pad portion and electrically connecting the chip and the first leads by a connector; forming an insulative molding portion on the metal substrate to bury the chip and the connector; and etching the bottom of the metal substrate to short-circuit the lead portion and the die pad portion.
A chip package manufactured using the above process according to one aspect of the present invention comprise: a lead portion spaced apart from a die pad portion, and including vertical portions and horizontal portions; conductive first leads positioned adjacent to the die pad portion, and formed on the top surfaces of the horizontal portions of the lead portion; conductive second leads formed on the bottom surfaces of the vertical portions of the lead portion; a chip formed on the top surface of the die pad portion; a connector electrically connecting the chip and the first leads; and a molding portion supporting the lead portion and the die pad portion, and burying the chip and the connector. An irregular pattern may be formed on the surface of at least either of the lead portion, the die pad portion, the first leads, and the second leads.
Hereinafter, configurations and operations according to the present invention will be described in detail with reference to the accompanying drawings. In the description with reference to the accompanying drawings, the same or equivalent components regardless of reference numerals will be provided with the same reference numbers, and description thereof will not be repeated. Terms containing ordinal numbers such as 1, 2 and the like, may be used to describe various components, but the components may not be limited to the terms. The terms are used for the purpose of distinguishing one component from another component.
FIG. 2 shows block diagrams of a manufacturing method of a chip package according to one exemplary embodiment of the present invention. FIG. 3 shows cross-sectional views of the manufacturing method of a chip package, respectively corresponding to the block diagrams of the manufacturing method of a chip package of FIG. 2.
Referring to FIGS. 2 and 3, in the manufacturing method of a chip package according to one exemplary embodiment of the present invention, firstly, first leads 230 and second leads 240, both having conductivity, are respectively formed on the top and bottom surfaces of a metal substrate 200. In addition to the first leads 230 and the second leads 240, an upper die pad metallic portion 210 and a lower die pad metallic portion 220 may be further formed. In this exemplary embodiment, the first leads 230 serve as inner leads, and the second leads 240 serve as outer leads. In this exemplary embodiment, the first leads 230 are formed on the top surface of the metal substrate 200 and disposed more inwardly than the second leads 240 on the bottom surface of the metal substrate 200. Otherwise, as will described later, the first leads 230 may be disposed more outwardly than the second leads 240 on the bottom surface of the metal substrate 200 (see FIG. 4).
More specifically, the metal substrate 200 is prepared as a primary member for circuit implementation. The metal substrate 200 is preferably made of Cu, and may be a metallic member such as a conductive Cu alloy, Fe, or an alloy of Fe. Moreover, while it is recommended that the thickness of the metal substrate 200 is less than 5 mil for the formation of a thin film substrate, a member having a thickness of less than 10 mil can be used. Both sides of the suggested member 200 are coated with a photoresist film, and then covered with a pattern mask and exposed to light to form a wire bonding portion including the first leads 230 and the upper die pad metallic portion 210 and a solder mounting pad portion including the second leads 240 and the lower die pad metallic portion 220. The photoresist film is removed from a light receiving portion (or non-light receiving portion) during development, and the metal substrate 200 is exposed. The metal substrate 200 exposed to both sides is plated with Ni, and then plated with Au known to be the best metal for signal transmission. Besides, Pd may be plated on an Ni plating layer, Au may be plated on the Pd plating layer, and Ag, instead of Ni, Pd, and Au, may be plated. A plating layer is usually formed by electroplating, but may be formed by electroless plating or a combination of electroplating and electroless plating. Moreover, the second leads 240 and lower die pad metallic portion 220 on the bottom surface of the metal substrate 200 may be surface-treated with Sn and OSP (organic solderability preservative) to prevent oxidization.
Especially, it is preferred that an irregular pattern is formed on at least part of the surface of the metal substrate 200 before a plating process. If an irregular pattern is formed on the surfaces of regions contacting the plating layer such as the first leads 230 or the second leads 240, the adhesive force can be strengthened.
Alternatively, an irregular pattern may be formed on the surface of at least either of the first leads 230, second leads 240, and upper and lower die pad metallic portions 210 and 220 that have been already formed. In this case, bonding with the molding portion 270 to be formed later can be strengthened.
In particular, if a metallic layer, such as the first leads 230 and the second leads 240, comprises a plurality of layers, an irregular pattern may be formed between the layers to thus improve the bonding force.
After that, a lead portion 290 having a circuit pattern shape and a die pad portion 280 are formed by half-etching (S2). More particularly, the photoresist film is removed, and then a photoresist film is coated over again for circuit pattern formation. Although not a problem in coating a liquid photoresist (LPR) film, the use of a dry film photoresist (DFR) may deteriorate the adhesion of the photoresist film due to a step difference between the metal substrate 200 and the plating layer (first leads 230, second leads 240, and upper and lower die pad metallic portions 210 and 220). In this case, the adhesion can be improved by vacuum lamination. A light receiving portion (or non-light receiving portion) of the photoresist film is developed, removed, and then etched. It is important that the etching be performed so as not to expose the metal substrate 200. In case that the metal substrate 200 is exposed, the formation of a micro circuit to be conducted later will not be properly done. It is recommended that the thickness of the metal substrate 200 left after vertical etching ranges from 10 to 60μm. Although the metal substrate 200 may be less than 10μm, the metal substrate 200 may be exposed and therefore care must be taken during the etching process. Next, pattern formation is performed, and half-etching is performed for circuit implementation. By means of half-etching, the lead portion 290 and the die pad portion 280 are formed, and the lead portion 290 and the bottom of the die pad portion 280 are still connected. Moreover, the lead portion 290 is etched to have a desired circuit pattern when viewed from the top. In addition, the overall thickness of the chip package can be adjusted by forming a chip mounting recess 20 in the die pad portion 280 during etching.
Thereafter, a chip 250 is attached onto the die pad portion 280, and connected to the first leads 230 by a wire 260 as a connector (S3). Specifically, the chip 250 is bonded onto the chip mounting recess 20 of the half-etched die pad portion 280, and wire bonding between the chip 250 and the first leads 230 and/or upper die pad metallic portion 210 is performed using gold lines. If necessary, copper lines can be used instead of the gold lines. Then, the chip 250 and the wire 260 are buried in the molding portion 270 by being encapsulated by an epoxy molding compound (S4).
Finally, the lead portion 290 and the die pad portion 280 are short-circuited by etching the bottom of the metal substrate 200 (S5). In detail, half-etching is performed using portions, excluding the second leads 240 and the lower die pad metallic portion 220, of the bottom surface of the metal substrate 200 as an etching resist, thereby forming the lead portion 290 as horizontal portions 290a and vertical portions 290b as shown in the drawing. The horizontal portions 290a of the lead portion 290 have a desired circuit pattern as discussed above when viewed from the top. Since the lead portion 290 of this type does not have a bump shape as in the prior art, if the chip 250 is connected to the first leads 230 close to the die pad portion 280, the chip 250 is electrically connected to the second leads 240 via the horizontal portions 290a of the lead portion 290. In this case, the width d1 of a connecting region between the horizontal portion 290a and the vertical portion 290b may be greater than the width d2 of the second lead. In this way, the second leads can have a stable structure.
The above-described structure can realize the advantage of a considerable reduction in the length of the wire 260. Moreover, the thickness of the horizontal portions 290a of the lead portion 290 is adjusted in the final step (S5), and there is no subsequent step which will affect the thickness of the adjusted horizontal portions 290a, thus enhancing the overall stability of the product. In addition, the lead-shaped circuit pattern has a much smaller etched area as compared to the conventional bump-shaped circuit pattern. Thus, it is possible to prevent the pitch of the circuit pattern from being widened due to isotropic etching, thereby realizing a micro-circuit pattern.
FIG. 4 illustrates a manufacturing process of a chip packaging according to another exemplary embodiment of the present invention.
This process is basically similar to the above-described process of FIG. 3 except that first leads 330 are disposed at outer sides of the metal substrate and second leads 340 are disposed at relatively inner sides of a metal substrate 300.
(a) First, the first leads 330 and the second leads 340 are formed on the metal substrate 300 by a plating process, which can be performed using the same method as described in FIG. 3. A die pad metallic portion 320 may be further formed on the bottom surface of the metal substrate 300.
Afterwards, as shown in (b), the bottom surface of the metal substrate 300 is etched to form a lead portion 390, and, as shown in (c), a chip mounting portion is formed by etching. (d) Afterwards, a chip 350 is mounted on the metal substrate 300, wire-bonded, and molded with a molding material 370 such as epoxy, and then the outer leads, the lead portion, and the die pad portion are short-circuited by etching the lower side. Like the structure illustrated in FIG. 3, the lead portion 390 is formed under the inner leads 330, and the lead portion 390 comprises vertical portions and horizontal portions.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes may be made therein without departing from the scope of the invention. The technical spirit of the invention should not be limited to the embodiments, but should be defined by the appended claims and equivalents thereof.

Claims (18)

  1. A manufacturing method of a chip package, the method comprising:
    forming first leads and second leads, both having conductivity, on the top and bottom surfaces of a metal substrate;
    half-etching the top surface of the metal substrate to form a lead portion under the first leads and to form a die pad portion whose bottom is connected to the lead portion;
    attaching a chip onto the die pad portion and electrically connecting the chip and the first leads by a connector;
    forming an insulative molding portion on the metal substrate to bury the chip and the connector; and
    etching the bottom of the metal substrate to short-circuit the lead portion and the die pad portion.
  2. The method of claim 1, wherein, in the formation of the first leads and the second leads, a plating process is carried out such that the first leads are disposed inwardly of the second leads.
  3. The method of claim 1, wherein, in the formation of the first leads and the second leads, a plating process is carried out such that the first leads are disposed outwardly of the second leads.
  4. The method of claim 1, wherein the first leads and the second leads are formed after forming an irregular pattern on at least part of the surface of the metal substrate.
  5. The method of claim 1, wherein an irregular pattern is formed on the surface of at least either of the first leads and the second leads after forming the first leads and the second leads, respectively, on the top and bottom surfaces of the metal substrate.
  6. The method of claim 1, wherein at least either of the first leads and the second leads is formed of one or more of an Ni layer, an Ag layer, an Au layer, a Pd layer, and a Cu layer.
  7. The method of claim 2, wherein, in the formation of the first leads and the second leads, a die pad metallic portion is further formed on the top or bottom of the metal substrate.
  8. The method of claim 6, further comprise surface-treating the die pad portion and the second leads, which are formed on the bottom surface of the metal substrate, with Sn or OSP.
  9. The method of claim 2, wherein half-etching of the top surface of the metal substrate and etching of the bottom surface thereof are carried out such that the metal substrate left after etching is 10 to 60μm thick.
  10. The method of claim 2, wherein, in the short-circuiting of the lead portion and the die pad portion, the lead portion is formed as horizontal portions and vertical portions by using portions, excluding the second leads and the lower die pad metallic portion, of the bottom surface of the metal substrate as an etching resist.
  11. The method of claim 10, wherein the width of connecting portions between the horizontal portions and vertical portions of the lead portion is greater than the width of the second leads formed on the surfaces of the vertical portions.
  12. A chip package comprising:
    a lead portion spaced apart from a die pad portion, and including vertical portions and horizontal portions;
    conductive first leads positioned adjacent to the die pad portion, and formed on the top surfaces of the horizontal portions of the lead portion;
    conductive second leads formed on the bottom surfaces of the vertical portions of the lead portion;
    a chip formed on the top surface of the die pad portion;
    a connector electrically connecting the chip and the first leads; and
    a molding portion supporting the lead portion and the die pad portion, and burying the chip and the connector.
  13. The chip package of claim 12, wherein an irregular pattern is formed on the surface of at least either of the lead portion, the die pad portion, the first leads, and the second leads.
  14. The chip package of claim 12, wherein the first leads are disposed inwardly of the second leads.
  15. The chip package of claim 12, wherein the first leads are disposed outwardly of the second leads.
  16. The chip package of claim 12, further comprising a surface treatment layer made of Sn and OSP on the surfaces of the second leads.
  17. The chip package of claim 12, wherein the width of connecting portions between the horizontal portions and vertical portions of the lead portion is greater than the width of the second leads formed on the surfaces of the vertical portions.
  18. The chip package of claim 12, wherein the first and second leads comprise one or more of an Ni layer, an Ag layer, an Au layer, a Pd layer, and a Cu layer.
PCT/KR2011/002628 2010-07-08 2011-04-13 Manufacturing method of chip package and chip package manufactured using the same WO2012005435A1 (en)

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