TW201123391A - Lead frame and manufacturing method of the same - Google Patents

Lead frame and manufacturing method of the same Download PDF

Info

Publication number
TW201123391A
TW201123391A TW099138153A TW99138153A TW201123391A TW 201123391 A TW201123391 A TW 201123391A TW 099138153 A TW099138153 A TW 099138153A TW 99138153 A TW99138153 A TW 99138153A TW 201123391 A TW201123391 A TW 201123391A
Authority
TW
Taiwan
Prior art keywords
lead
portions
wafer
lead frame
pad portion
Prior art date
Application number
TW099138153A
Other languages
Chinese (zh)
Inventor
Sai-Ran Eom
Hyun-A Chun
Chung-Sik Park
Hyung-Eui Lee
Original Assignee
Lg Innotek Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020090108497A external-priority patent/KR101168413B1/en
Priority claimed from KR1020090108907A external-priority patent/KR101197777B1/en
Priority claimed from KR1020090116935A external-priority patent/KR101107756B1/en
Application filed by Lg Innotek Co Ltd filed Critical Lg Innotek Co Ltd
Publication of TW201123391A publication Critical patent/TW201123391A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4801—Structure
    • H01L2224/48011—Length
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

An aspect of the present invention provides a lead frame, comprising lead portions each composed of a vertical portion and a horizontal portion, a die pad portion disconnected from the lead portions by support portions made of an insulating material, inner leads disposed to neighbor the die pad portion and formed on a top surface of the horizontal portions of the lead portions, and outer leads formed on a bottom surface of the vertical portions of the lead portions. In accordance with the present invention, a lead frame having a reduced wire length due to a fine circuit pattern, enabling flipchip bonding due to routability, and improving adhesive strength upon soldering due to a swell structure can be fabricated. Further, a warpage phenomenon in a manufacturing process can be prevented.

Description

201123391 六、發明說明： 【發明所屬之技術領域】 本發明主張於2009年11月11日所申請之韓國專利申靖 案號腦97、2_年U月12日所中請之韓國^ 申請案號1G-2_-_89()7、以及年1U3Q日所申請 之韓國專利申請案號10-2009-0116935的優先權，此全文將併 入本案以作為參考。 本發明係關於一種引線架及其製造方法。 【先前技術】 胃半導體封裝制卜種電性連結由晶圓製程所生產的獨 立曰曰片的製程，因此晶片可被作為實際的電子元件且封閉 (seal ing)和财（paekaging)該晶以賴衫受外部的 衝擊。 曰通^ ’ -晶圓上有著數十或數百個印製有相同線路的 曰曰片每曰曰片並無法作為一電子元件。因此，用來連接 卜P並配置來為接收外部電子職和傳輸在晶片中產生 =子訊號的引線必需形成在晶片中。晶片容易因潮濕、 灰塵、和外部衝擊而損壞，因為其包含了非常精細的線路。 :以這麼^形成在晶圓表面的晶片不能算是一完整的產 Γ查而必需直到它安裝到印刷電路板上。因此，形成-電 線到形成在晶圓上晶片，封閉㈣祕構裝 201123391 (packaging)該晶片以保護其不受外部的衝擊，以及最後產 出〇日0片使日日片作為一完整的電子元件的製程為封裝製 程。 在半導體封裝的製造中，引線架扮演使晶片安裝於其 上的重要的角色及供輸入和輸出手段（以⑸⑽）用於傳輸 訊號。而用以傳輸訊號的各種類型的整合式引線架已被發 展出。 在一般型式的引線架中，晶片焊墊（die pad)和引線 部藉由蝕刻法或衝壓法（stamping meth〇d)所形成。然而， 以現有的引線架製造方法並不容易形成半導體高度整合所 需的多列（multi-column)引線。 使用兩段式蝕刻法製作引線架會有縮小内引線間間距 的限制，因而造成了引線接腳（lead pins)數量上的限制。 此外，另有一缺點在於：用於維持晶片焊墊部和引線部間 的間隔之支撐部是由厚度薄的聚亞醯胺膜（p〇lyimide film)所形成，從而支撐力較弱。 再者，當引線架的線路圖案藉由兩段式蝕刻法形成 時，則因等向性蝕刻（isotropic etching)而無法形成 具有恆定厚度（constant thickness)的線路圖案。亦即， 藉由蝕刻而被去除（cut)的邊緣部分為一凹面狀，因此一部 份其内安置有構成内引線和外引線的金屬部份高於其餘的 201123391 部份。所以，造成對線路圖案的厚度和精細度的限制。 再者，支撐力是薄弱的，且在耐用性具有—顯著的門 題，因為在焊接製程（soldering process)中，沒有用以固 定錫球結合（bond to)到外引線的結構。 尤其，習知的引線架製造方法存在著引線架在敍刻和 研磨製程（polishing process)期間彎折的翹曲（warpage) 現象問題。 因此’鑑於上述問題而產生本發明，而本發明之—目 的在於提供一引線架的製造方法，其具有實現精細線路圖 案、增加與錫球的結合強度（adhesive strength)和物性強 度、以及改善翹曲的能力。 【發明内容】 根據本發明一考量面之引線架包括多個引線部，而 每一引線部由一垂直部和一水平部所組成；一晶片焊墊 部藉由絕緣材料所製成之多個支撐部而從引線部斷開 (disconnected);多個内引線設置來鄰接晶片焊墊部且 形成在引線部的水平部之上表面；以及多個外引線形成 在引線部的垂直部之下表面。 在本例中，水平部能藉由一金屬膠（metal paste) 而被印製在該垂直部。 201123391 支撐部的下表面可較晶片焊墊部的外引線的下表 面突出。 該絕緣材料可包括環氧樹脂或玻璃纖維。 尤其，引線架可更包括多個晶片焊墊金屬部形成在 晶月焊墊部的上表面或下表面上。 該水平。卩可有一恆定厚度。在本例中，垂直部的朝 上方向的寬度最好比垂直部的朝下方向的寬度要窄。 該些内引線或該些外引線可以由兩種或更多種的 金屬堆疊所形成。 再者，該兩種或更多種的金屬最好選自由鎳（Ni)、 鈀（Pd)、金（Au)、以及銀（Ag)之中的金屬。 同時，根據本發明另一考量面提供一引線架製造方 ^包括（a)形成多個支撐部凹槽、—晶片焊墊部、以及 稭由執仃半_於—金屬基板的多個引線部；⑹藉由 填充姆材料於該些支撐部凹槽形成多個支撐部；以及 ()藉由飯刻該金屬基板將晶片焊塾部和該引線部分 離0 這裡步驟（b)包括壓縮（compress)樹脂包覆銅箔 (RCC)在軸支料凹槽，以及㈣⑹可包括步驟（⑴ 露出引線朴晶片焊塾部的突起表面；步驟⑽）藉由 電錢金屬基板的雙側形成㈣線和外引線，其中外引線 201123391 可經電鍍使其外引線的高度低於環繞部；步驟（c3)藉由 蝕刻金屬基板將晶片焊墊部和引線部分離；以及步驟 (c4)移除該銅（Cu)基板。 再者，步驟（c)可包括藉由印製一金屬漿料在該些 引線部上以形成線路圖案和藉由蝕刻該金屬基板形成 該線路圖案表面的另一面而分離該晶片焊墊部和該些 引線部。 再者，步驟（b)可包括藉由絕緣材料填充該些支撐 部凹槽而形成該些支撐部和形成一背架在該些支撐部 上。步驟（C)可包括步驟（cl)暴露該些引線部和該晶片 知塾部的突起表面；（C2)藉由電鑛金屬基板的雙側形成 多個内引線和多個外引線；（c3)藉由蝕刻金屬基板而分 離晶片焊塾部和該些引線部以及移除背架。 再者，步驟（cl)可包括藉由執行一微影製程，以暴 露出在該些引線部和晶片焊墊部的突起表面上的該些 支撐部以及藉由使用除膠渣（desmear)移除暴露出的該 些支撐部。 再者，步驟（c)的金屬漿料可包括銅（Cu)、鋁（A1)、 以及鎮（Mg)中其中一種或多種。 再者’步驟（c)可包括印製金屬漿料以使該些線路 圖案具有一恆定厚度。 201123391 再者，步驟（b)的背架可包括銅（Cu)。在此例中， 步驟（cl)可包括藉由蝕刻該背架以暴露出在該些引線 部和晶片焊墊部的突起表面的該些支撐部以及藉由化 學研磨（chemical polishing)移除暴露出的該些支撐 部。在步驟（C2)可包括藉由連續地電鍍鎳（[)、鈀 (Pd)、金（Au)、以及銀（Ag)中的兩種或多種金屬而形 成該些内引線和該些外引線。 依據本發明，能製造出之引線架由於精細線路圖案 而可減少導線長度、由於可繞線性（routability)而能 夠覆晶接合、以及由於隆起結構（swell structure)而 於焊接時改善黏合強度（adhesive strength)。再者， 發生於製造過程中的翹曲（warpage)現象亦得以避免。 特別是因為隆起結構（sweil structure)是藉由蝕 J所升/成，所以邊緣部份（edge p〇rti〇n)不會被去除 (cut)。因此，錫球附著在隆起結構的空間内可被更精 巧地固定。 再者’製程的數量可藉由印製金屬㈣的方法而被 減少，而訊號傳輸和導熱性（thermal c〇nductivi⑺實 際上可糟由金屬件而被改善，不像pCB基板，其中連接 線路的晶片焊墊部和引線部的表面是藉由電錢所形成 201123391 此外，因為支樓部是由環氧樹脂（epoxy )或玻璃纖維 (glass fiber)所製成，物性強度和支樓力可被改善，且在 製造過成中的輕曲（warpage)現象可藉由背架（back frame) 而得以避免。 【實施方式】 後文中，根據本發明一些實施例的引線架的數種製造 方法將參照附圖詳細說明。在描述本發明實施例時，如果 已知的功能或結構的描述會造成模糊本發明的焦點，該部 份的描述將被省略。 再者，在實施例的描述中，當提及一元件是形成在另 一元件之「上/下」，該名詞「上/下」包括所有元件直接形 成在其他元件之「上/下」以及非直接形成在其他元件之「上 /下」且有一第三件插入於其中。而參照中每一元件的内/ 下依據圖示為基準。是依照圖示為參照。應注意的是元件 的尺寸是被放大而非實際尺寸。 圖1至圖9為根據本發明第一實施例之引線架製造方 法的剖視圖。 如圖1所示，準備一金屬基板110 (亦即，一線路的本 體）。金屬基板110最好由銅（Cu)所製成，但也可由傳導材 料的金屬構件，例如銅合金、鐵（Fe)、或鐵合金所製成。 10 5 201123391 本例中，金屬基板110的厚度較好是lOmil或更少d mi 1 = 1/1，〇〇〇 inches)，5 mi 1 或更少的話更好。 如圖2所示，光阻120形成在金屬基板11〇的上和下 表面上。這裡，一種液體狀的液態光阻（LPR)或乾膜光阻 (DFR)可被作為光阻丨2〇。形成在金屬基板11〇的上和下表 面上的光阻120藉由使用光罩（photomask) 130的微影餘刻 (photolithography process)製程而被曝光與顯影。 雖然光阻120可僅塗佈在金屬基板110的上表面上， 但光阻120最好被塗佈在金屬基板11〇的雙面上以保護在 下方的元件。 這裡，光罩130包括一遮蓋層形成在一石英基板上的 遮光區域S1以及僅存在石英基板的光傳輸區域％。在設 置於金屬基板110的上部的光罩13Q t，光傳輸區域設置 在將形成絕緣部凹槽的部份，而它們將在曝光製程中傳輸 t外光。因此’在顯影製程後’將設置絕緣部凹槽地方的 光阻120將被移除。在此，^ 12〇包括曝露在紫外光的 部份被移除的類如及未曝露在紫外光㈣份被移除的類 型。在此步驟中，使用前者類型的姐12〇。 接者’在金屬基板11〇執行半餘刻，藉此形成多個絕 緣相槽(亦即’絕緣體將填充的空間 > 此處，有需要時， 可控制钱刻的深度。 11 201123391 執行。亥钱刻時’由於等向性蚀刻 etching) ’形成的凹槽的邊緣部也被侧掉，因而造成如 圖3所不凹形的邊緣部。亦即，引線部⑽朝上方向的寬 度車义引線部18G朝下方向的寬度窄。而如此的#刻使引線 部要具有恆定厚度將變的困難。 接著，具有一形狀的金屬基板11〇，例如圖3所示， 疋藉由剝落光阻12〇所形成。具有如圖3所示形狀的金屬 基板11G包括引線部⑽、多個絕緣部凹槽、以及一晶片 焊墊部115。 如圖4所不，具有絕緣功能的樹脂是塗佈在金屬基板 110的上部’藉以填充該絕緣部凹槽。當使用液態樹脂時， 絕緣部凹槽必須經由網版印刷（町咖pHnting)填充然 後固化（未緣示）以增加液態樹脂的硬度。同時，當使用⑽ 如預浸材（Prepreg)或樹脂包覆銅羯（Resin c〇ated⑽卿， RCC))的一膜態樹脂時’該樹脂是麗合（laminated)在金屬 基板ll〇_h，然後再藉由施加一適當壓力和溫度而填充。 如圖5所示，執行一研磨步驟（p〇Ushing师娜） 以暴露出未填充樹脂的部份（亦^引線部18〇的上表面和 晶片焊墊部115)。 這裡，另-種執行填充半姓刻表面的方法是藉由使用 行抗焊劑㈤der resist ; SR)。當抗焊劑為液態抗焊劑 12 201123391 時’經由網版印刷進行塗佑 n 然後使用圖樣罩幕層 (pattern mask)130 進行瞌杏。s 九暴露在光的部份經由顯影 製程而被移除，無需填充樹脂的區域的元件表面被暴露 出，然後固化填充在半蝕刻區域的抗焊劑。在本例中，可 進行-_步驟以使填充的樹脂和暴露㈣金屬表面具有 相同的回度。4者’亦可使用—膜態的乾膜抗 。接著，進行使用圖樣罩幕層⑽的曝光製 程，然後再進行顯影製 , 裏耘。然而，乾膜抗焊因為有著和抗 焊劑相似的特性因而费 口阳而要一固化步驟。 接者’如圖6所千，4 '、猎由使用一金屬漿料（metal paste) 形成線路圖案16〇名社 k二引線部180和該些支撐部150的 上表面上。特別是， +例而言，可使用擠壓（squeezing) 金屬漿料印刷於—金 、 卫碣遮罩（metal mask)而使金屬遮罩形 成八有所而線路圖案的網板印刷法。因此，在厚度上來說， 精細和規則的觀料“㈣·。 線路圖案的i # 又16〇 (亦即，高度）可藉由印刷的次數 (舉例而言，執行 & 火或更多次的印刷使厚度變厚）或控制 漿料的黏性來控也丨 。再者，每一線路圖案的寬度可藉由控 制使用來印製金屬將 萄水枓的金屬遮罩的線路圖案的寬度來控 制。 13 201123391 、此處，銅（Cu)漿料、鋁（A1)漿料、以及鎂（Mg)漿料中 的其中-者或使關漿料、㈣料、以及錢料中的兩種 或更多的一混合漿料可被用來作為金屬漿料。或者，其它 f導材料亦可被絲作為金屬㈣。特別是在當金屬衆料 是由銅所製成時，最好是銅衆料具有和金屬基板相同的成 伤和同導熱性。線路圖案16〇必須相互間隔開，因此線路 圖案160與晶片焊塾部115絕緣。如圖1〇所示，形成有線 路圖案160於引線架的上表面的視圖。 特別疋’如上所述藉由印製金屬聚料而形成的線路圖 案與S知使用㈣方法所形成的線路圖案有著不同的形 式。亦即，在習知的姓刻方法中，金屬部份，例如内引線 和外引線’是先被電鑛，然後經由等向性钱刻（i如计〇如 etching)而形成線路圖案。因此，線路圖案在外引線和内 引線正下方的部份（因敍刻而安置在邊緣部份）高於線路圖 案的剩餘部份。 在本發明中，然而，並未進行钱刻。因此，因為邊緣 部並未被去除，所以具有怪定厚度的線路圖案得以形成。 如此，引線架可以做的很薄。 ® 1G為根據本發明第—實施例顯示引線架的線路圖 案⑽的平面視圖。參閱圖1〇，因為介於線路圖案之間的 間距（lnterVal)非㈣窄，因此大量的訊號傳輸系統得以 14 201123391 被建構。 明再參閱圖7，金屬基板11〇的下表面因韻刻而完全 地被移除。而金屬基板11〇的下表面之所以完全被姓刻移 除的原因疋為了將引線部180和晶片焊墊部us電性絕 緣。因此，引線部180和晶片焊墊部丨15彼此相互間隔開 而支撑部150插入在其_。 此處，圖6和圖7的步驟順序可相互調換。換言之， 金屬基板11G的下表面可先被㈣掉，錢再形成線路圖 案160。當金屬基板110的下表面如上所述先被钱刻掉時， 因為該些支撐部150和該些引線部18〇是同時暴露出，因 此線路圖案160可形成在金屬基板UG的下表面，而 圖3 —樣。 然而，如果金屬基板110的下表面先被餘刻掉，對控 制基板厚度將有點困難。因為這個原因，目7的步驟最好 在圖6的步驟後再執行。 圖12根據本發明第一實施例顯示引線架的錫膏焊墊 _ _部將被安裳的平面視圖。參閱圖12， 在圖7的步驟中_掉，因此暴 路出曰曰片知墊部115的下表面和引線架的下表面。 圖13顯不弓丨線架在㈣後的剖視圖。參 線部180可具有如支撐部15〇 - 予沒如顯示在圖13 15 201123391 的左下侧，或可形成在支撐部150中，如顯干+ ^ 貝不在圖13的右 下側。如果引線部180形成在一絕緣層内時 a 虽—晶片架 (die frame)依續形成及執行焊接製程時，勒著強产了 、 增加。 、 在進行下表面蝕刻後，執行形成打谂 re er 、冰坪塾（wi bonding pad)(或亦指内引線）和〆焊踢固定塾（1 mounting pad)(或亦指外引線）的程序，如圖 Θ 〇所不。更 特別的是，光阻丨2〇塗佈在雙面上姐經使用光罩13〇勺 遮光區域S1和光傳輸區域S2進行曝光和顯影。因此 露出將形成打線焊墊190和焊錫固定墊185的部份。j 接著，暴露出的部份將進行電鍍製種。電錢製程可藉 由在執行鍍鎳（Ni)後的鍍金（Au)製程。或者，把和金 (Au)可依續地電鍍在鍍鎳層上。再者，鎳、鈀（Pd)和金（Au) 中的一者或更多者可被銀（Ag)所取代。電鍍層的完成主要 藉由執行電鍍（electroplating)，但電鑛和無電電錄 (electroless plating)可混合使用。 最後，移除光阻以形成該些打線焊墊19〇和焊錫固定 墊185如圖9所示。形成打線焊墊19〇的上表面如圖u所 再者’線路圖案160的厚度和打線焊墊19〇的厚度於 而要時可控制其厚度。因此，線路圖案160和打線焊墊190 201123391 可具有相同或不同的高度。 因此，相較於現有使用球柵陣列（ball grid BGA)的製造方法，本發明的精細線路圖案16〇可藉由簡單 的製程而形成。再者，不同於習知的結構，由引線部同： 扮演線路圖案160的角色，本發明的線路圖案16〇是藉由 使用-㈣印製方法（paste printing __來分制 成。因此，線路圖案160是較精細、厚度保持恆定、以及 可尚程度整合成型。 圖14至圖25為根據本發明第二實施例之引線架製造 方法的剖視圖。如圖14所示，準備一金屬基板21〇 (亦<即， 一線路的本體）。金屬基板210最好由銅（Cu)所製成，但也 可由傳導材料的金屬構件，例如鋼合金、鐵（Fe)、或鐵合 金所製成。這裡，金屬基板210的厚度較好為1〇mil或更 少（lmil = l/l，〇〇〇 inches)，5 mil 或更少的話更好。 光阻220形成在金屬基板210的上和下表面上。這裡， 一種液體狀的液態光阻（LPR)或乾膜光阻（DFR)可被作為光 阻220。形成在金屬基板210的上和下表面上的光阻22〇 藉由使用光罩（photomask)的微影银刻（phot〇1 i thography process)製程而被曝光與顯影。 雖然光阻220可僅塗佈在金屬基板21〇的上表面上， 但光阻220最好被塗佈在金屬基板21〇的雙面上以保護在 17 201123391 下方的元件。 接著，如圖15所示，多個絕緣部凹槽230、一晶片焊 墊部240、以及多個引線部250藉由執行半蝕刻而形成。 必須要說明的是如圖15所示之絕緣部凹槽230、晶片焊墊 部240、以及引線部250尚未彼此分離。 然後，準備一樹脂包覆銅箔（RCC)。RCC 260藉由施加 熱與壓力而被壓縮（compressed)在金屬基板210上。在本 例中’被RCC260的樹脂260b塗佈的部分是壓縮在金屬基 板210上。此處，壓縮的高度維持在銅基板260a未與晶片 焊墊部240與引線部250的下突起部接觸的程度，如圖16 所示。因此，RCC 260的樹脂260b形成來填充絕緣部凹槽 230和圍繞金屬基板210上所有的部分，包括晶片焊墊部 240與引線部250的下突起部。特別是，如上所描述的， 銅基板260a從金屬基板210的最高處（亦即，晶片焊塾部 240與引線部250的下突起部）以一預定間距間隔開。 接著’塗佈光阻220，然後經由微影製程進行曝光和 顯影，因此形成一蝕刻遮罩（etching mask)。蝕刻遮罩的 圖案形成來暴露在引線部250與晶片焊墊部240的下突起 部的樹脂層260b。接著，在引線部250與晶片焊墊部24〇 的上突起部的樹脂層260b經由蝕刻而暴露出，如圖17所 示。之後，在引線部250與晶片焊墊部240的上突起部的 18 201123391 樹脂層260b經由除膠渣（desmear)而被移除，因而暴露出 引線部250與晶片焊墊部240的上突起部，如圖is所示。 再者，樹脂層260b經由蝕刻而分離，進而形成多個支撐部 270。 接續，光阻220塗佈在金屬基板210的下表面上以及 未被蝕刻掉的剩餘RCC 260的樹脂層260a上，然後經由微 影製程進行曝光和顯影’如此以形成如圖19所示之圖案的 光阻220。在光阻220上執行電鍍，如此以形成内引線 290a、外引線290b、以及晶片焊墊金屬部295a和295b， 如圖20所示。這裡，外引線29〇a或晶片焊墊金屬部295b 形成在隨後將安裝半導體晶片400的表面的另一面上。當 一半導體封裝安裝在一 PCB基板時，形成外引線29〇a或晶 片焊墊金屬部295b的面變成將接觸錫球的面。 外引線290b或晶片焊墊金屬部295b的高度低於鄰近 的支撐部270。亦即，經執行電錢，因此支撐部wo的上 表面是突起的，因此其高於外引線290b或晶片焊墊金屬部 295b的上表面。因為銅基板260a是從晶片焊墊部240和 引線部250的上突起部以一預定間距間隔開，而當RCC26〇 在如圖3中被壓縮時，該預定間距被樹脂所填充，使得如 此的電鑛是為可行的。再者，銅基板260a是從支撐部270 和晶片焊墊部240的上突起部間隔開，而引線部250幾乎 19 201123391 為該預定間距，而該電鍍是在高度的差異上進行。因此， 電鍍的外引線或電鍍的晶片金屬部可以有較支撐部更内凹 的形狀（後文將以隆起結構代替）。 因此，隆起結構能藉由使用Rcc 260而簡單的完成， 且不需要額外的#刻以形成隆起結構。 接著，光感物質（photosensitizer)塗佈在引線架的上 和下表面上（上表面被塗佈是為了保護元件），然後經由微 影製程進行曝光和顯影，如此以形成具有圖案的一光阻 220如圖21所不。接著，建構颠刻遮罩（的咖叫贴成） 的圖案以形成引線架的線路圖案。因此，如圖22所示，引 線部25G和晶片焊塾部24G經由餘刻而斷開，而支撐部270 支撐在引線部250和晶片焊塾部24()之間。再者，藉由使 用樹脂2_作為材料以形成支撐部⑽，因此晶片焊塾部 謂和引線部挪彼此電性絕緣。另外，最好藉由餘刻在 晶片焊墊部240形成凹槽。 接著’半導體晶片彻安裝在該凹槽巾。半導體晶片 400、内引線290a、以及曰Η、ί·θ·ϋτ人η 及日日片烊墊金屬部295a藉由導線 (wires)300而電性遠接。+ ，丄 八 ，曰u ㈣連接。在本例中，半導體晶；M00安裝 塾部24。的凹槽。因此，晶片的黏著力得以增加： +導體晶片封裝的厚度得以減少。此處，圖U顯 22結構上下翻轉後安裂 ，、不圖 戒上阳片的狀態。這是因為為了執行 20 201123391 壓縮如圖16的RCC 260 ’因此將安裝半導徵晶片的面之另 一面被上下翻轉（upside down)。 接著，如圖24所示’引線架和半導體晶片藉由密封劑 (sea 1 ant)被封閉（sea 1 ed)在一壓塊（bund 1 e )内，然後使用 壓模樹脂（mold resin)(例如環氧樹脂模封材料（Ep〇xy M〇1ding Co_und，EMC))5⑽進行封農。如圖25所示， 移除作為RCC 26〇的銅（Cu)基板謹，鋼（Cu)基板26〇的 功能為防止在數難合和㈣製程巾錢_曲（卿) 方法，能有效率 及經由隆起結構 1線架製造方法 如上所述，根據本發明的引線架製造 地製造防止在製造過程中產生翹曲現象以 改善焊接的黏著強度的引線架。 圖26為根據本發明第二實施例使用 所製造的引線架剖視圖。 參閱圖26,根據本實施例的引線架 ⑽、引線部25。、支撐部270、内引線2心括晶片焊塾部 以及晶片焊塾金屬部、和2 :外引線_、 和引線部謂此相互間隔開，因此它=片焊塾部240 =生絕緣。再者，切部270的功能為二：2:° 24〇和引線部250的底部。再者 牙日日片卜墊4 水平部25Ga和-垂直 化線部25G包括— 4 250b。從水平部250a的上表面，201123391 VI. Description of the invention: [Technical field to which the invention pertains] The present invention claims to be applied to the Korean patent application dated on November 11, 2009, and the Korean application filed in the U.S. No. 1G-2_--89()7, and the priority of the Korean Patent Application No. 10-2009-0116935, filed on Jan. The present invention relates to a lead frame and a method of manufacturing the same. [Prior Art] A gastric semiconductor package is electrically connected to a process of a separate wafer produced by a wafer process, so that the wafer can be used as an actual electronic component and seal ing and paekaging the crystal. Lai shirt is affected by the outside.曰通^' - There are dozens or hundreds of dies on the wafer that are printed with the same line. Each cymbal cannot be used as an electronic component. Therefore, the leads used to connect the P and are configured to receive the external electronic device and transmit the = sub-signal in the wafer must be formed in the wafer. Wafers are easily damaged by moisture, dust, and external shocks because they contain very fine lines. The wafer formed on the surface of the wafer is not a complete production inspection until it is mounted on the printed circuit board. Therefore, the -wire is formed into the wafer formed on the wafer, and the wafer is sealed (4) to protect the wafer from external impact, and the final output of the next day is to make the Japanese film a complete electronic The manufacturing process of the component is a packaging process. In the manufacture of semiconductor packages, the lead frame plays an important role in mounting the wafer thereon and means for inputting and outputting (using (5) (10)) for transmitting signals. Various types of integrated lead frames for transmitting signals have been developed. In a general type of lead frame, a die pad and a lead portion are formed by an etching method or a stamping method. However, the existing lead frame manufacturing method does not easily form a multi-column lead required for semiconductor high integration. The use of a two-stage etching process to form a lead frame has limitations in reducing the spacing between the inner leads, thereby limiting the number of lead pins. Further, there is another disadvantage in that the support portion for maintaining the interval between the pad portion and the lead portion is formed of a thin thickness of a polyimide film, so that the supporting force is weak. Further, when the wiring pattern of the lead frame is formed by the two-stage etching method, a line pattern having a constant thickness cannot be formed due to isotropic etching. That is, the edge portion which is cut by etching is concave, so that a portion of the metal portion in which the inner lead and the outer lead are disposed is higher than the remaining portion of 201123391. Therefore, it limits the thickness and fineness of the line pattern. Furthermore, the supporting force is weak and has a significant problem in durability because in the soldering process, there is no structure for fixing the solder balls to the outer leads. In particular, conventional lead frame manufacturing methods have the problem of warpage of the lead frame being bent during the sculpt and the polishing process. Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a lead frame which has a fine wiring pattern, an increased adhesive strength and physical strength with a solder ball, and an improved warpage. The ability of the song. SUMMARY OF THE INVENTION A lead frame according to the present invention includes a plurality of lead portions, and each lead portion is composed of a vertical portion and a horizontal portion; a plurality of wafer pad portions are made of an insulating material. The support portion is disconnected from the lead portion; a plurality of inner leads are disposed to abut the wafer pad portion and formed on an upper surface of the horizontal portion of the lead portion; and a plurality of outer leads are formed on a lower surface of the vertical portion of the lead portion . In this example, the horizontal portion can be printed on the vertical portion by a metal paste. 201123391 The lower surface of the support portion may protrude from the lower surface of the outer lead of the wafer pad portion. The insulating material may comprise epoxy or fiberglass. In particular, the lead frame may further include a plurality of wafer pad metal portions formed on the upper or lower surface of the crystal pad portion. The level.卩 can have a constant thickness. In this example, the width of the vertical portion in the upward direction is preferably narrower than the width of the vertical portion in the downward direction. The inner leads or the outer leads may be formed of two or more metal stacks. Further, the two or more metals are preferably selected from the group consisting of nickel (Ni), palladium (Pd), gold (Au), and silver (Ag). Meanwhile, according to another aspect of the present invention, a lead frame manufacturing method includes: (a) forming a plurality of support portion grooves, a wafer pad portion, and a plurality of lead portions of the straw substrate (6) forming a plurality of support portions by filling the material into the groove of the support portion; and () separating the wafer solder joint portion and the lead portion by the rice substrate by the rice padding, wherein the step (b) includes compression (compress) a resin-coated copper foil (RCC) in the axial support groove, and (d) (6) may include a step ((1) exposing the raised surface of the lead-wafer solder joint portion; step (10)) by forming a (four) line on both sides of the electric money metal substrate and An outer lead, wherein the outer lead 201123391 can be plated such that the outer lead has a lower height than the surrounding portion; the step (c3) separates the wafer pad portion from the lead portion by etching the metal substrate; and the step (c4) removes the copper ( Cu) substrate. Furthermore, the step (c) may include separating the wafer pad portion by printing a metal paste on the lead portions to form a wiring pattern and forming another surface of the wiring pattern surface by etching the metal substrate. The lead portions. Furthermore, step (b) may include forming the support portions by filling the support groove grooves with an insulating material and forming a back frame on the support portions. Step (C) may include the step (cl) of exposing the lead portions and the protruding surface of the wafer knowing portion; (C2) forming a plurality of inner leads and a plurality of outer leads by both sides of the electro-mineral metal substrate; (c3) Separating the wafer pad portion and the lead portions and removing the back frame by etching the metal substrate. Furthermore, the step (cl) may include performing a lithography process to expose the support portions on the protruding surfaces of the lead portions and the wafer pad portion and by using desmear removal Except for the exposed portions of the support. Further, the metal paste of the step (c) may include one or more of copper (Cu), aluminum (A1), and town (Mg). Further, step (c) may include printing a metal paste such that the line patterns have a constant thickness. 201123391 Furthermore, the back frame of step (b) may comprise copper (Cu). In this example, the step (cl) may include exposing the support portions on the protruding surfaces of the lead portions and the pad pads by etching the back frame and removing the exposure by chemical polishing The support parts are out. The step (C2) may include forming the inner leads and the outer leads by continuously electroplating two or more metals of nickel ([), palladium (Pd), gold (Au), and silver (Ag). . According to the present invention, the lead frame which can be manufactured can reduce the length of the wire due to the fine wiring pattern, can be flip-chip bonded due to routability, and improve the bonding strength during soldering due to the swell structure (adhesive) Strength). Furthermore, the warpage phenomenon that occurs during the manufacturing process is also avoided. In particular, since the sweil structure is raised/decreased by the etch J, the edge portion (edge p〇rti〇n) is not cut. Therefore, the solder balls are attached to the space of the ridge structure to be more precisely fixed. Furthermore, the number of processes can be reduced by the method of printing metal (4), and the signal transmission and thermal conductivity (thermal c〇nductivi (7) can be improved by metal parts, unlike pCB substrates, where the lines are connected. The surface of the pad pad and the lead portion is formed by electric money. 201123391 In addition, since the branch portion is made of epoxy or glass fiber, the physical strength and the supporting force can be Improvements, and the warpage phenomenon in the manufacturing process can be avoided by the back frame. [Embodiment] Hereinafter, several manufacturing methods of the lead frame according to some embodiments of the present invention will be DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S) In the description of the embodiments of the present invention, if a description of a known function or structure may obscure the focus of the present invention, the description of the part will be omitted. When a component is referred to as "up/down" of another component, the term "up/down" includes all components that are directly formed "up/down" of other components and are not directly formed in other components. Up/down" and a third piece is inserted therein, and the inside/down of each element in the reference is based on the drawing. It is referred to in accordance with the drawing. It should be noted that the size of the element is enlarged rather than actual size. 1 to 9 are cross-sectional views showing a method of manufacturing a lead frame according to a first embodiment of the present invention. As shown in Fig. 1, a metal substrate 110 (i.e., a body of a line) is prepared. The metal substrate 110 is preferably made of copper. (Cu), but may also be made of a metal member of a conductive material, such as a copper alloy, iron (Fe), or an iron alloy. 10 5 201123391 In this example, the thickness of the metal substrate 110 is preferably 10 mils or less. d mi 1 = 1/1, 〇〇〇inches), 5 mi 1 or less is better. As shown in Fig. 2, a photoresist 120 is formed on the upper and lower surfaces of the metal substrate 11A. Here, a liquid liquid photoresist (LPR) or dry film photoresist (DFR) can be used as the photoresist. The photoresist 120 formed on the upper and lower surfaces of the metal substrate 11 is exposed and developed by a photolithography process using a photomask 130. Although the photoresist 120 may be coated only on the upper surface of the metal substrate 110, the photoresist 120 is preferably coated on both sides of the metal substrate 11 to protect the underlying components. Here, the photomask 130 includes a light shielding region S1 in which a mask layer is formed on a quartz substrate and a light transmission region % in which only the quartz substrate exists. In the photomask 13Q t disposed on the upper portion of the metal substrate 110, the light transmission regions are disposed at portions where the recesses of the insulating portions are to be formed, and they will transmit t-outlights in the exposure process. Therefore, the photoresist 120 where the recess of the insulating portion is disposed after the developing process will be removed. Here, the type including the portion exposed to the ultraviolet light is removed, and the type not exposed to the ultraviolet light (four) is removed. In this step, the former type of sister 12 is used. The picker performs a half-time on the metal substrate 11 to form a plurality of insulating phase grooves (i.e., 'the space that the insulator will fill>. Here, if necessary, the depth of the money can be controlled. 11 201123391 Execution. At the time of engraving, 'the edge portion of the groove formed by the isotropic etching is also side-dropped, thus causing an edge portion which is not concave as shown in FIG. That is, the width of the width of the lead portion (10) in the upward direction is narrower in the downward direction. It is difficult to make the lead portion have a constant thickness. Next, a metal substrate 11 having a shape, for example, as shown in FIG. 3, is formed by peeling off the photoresist 12A. The metal substrate 11G having the shape shown in Fig. 3 includes a lead portion (10), a plurality of insulating portion grooves, and a wafer pad portion 115. As shown in Fig. 4, a resin having an insulating function is applied to the upper portion of the metal substrate 110 to fill the insulating portion groove. When a liquid resin is used, the insulating portion groove must be filled and then cured (not shown) by screen printing (pH nting) to increase the hardness of the liquid resin. Meanwhile, when (10) a film-like resin such as a prepreg or a resin-coated copper crucible (Resin c〇ated (10), RCC) is used, the resin is laminated on the metal substrate 11〇h And then filled by applying a suitable pressure and temperature. As shown in Fig. 5, a grinding step (p〇Ushing Shina) is performed to expose the unfilled portion (also the upper surface of the lead portion 18A and the wafer pad portion 115). Here, another method of performing filling of the surface of a half-name is by using a solder resist (f) der resist; SR). When the solder resist is a liquid solder resist 12 201123391 'by screen printing n then use a pattern mask 130 for apricot. s 九 The portion exposed to light is removed by the developing process, the surface of the component in the region where the resin is not required is exposed, and then the solder resist filled in the half etched region is cured. In this example, the -_ step can be performed to have the same resilience of the filled resin and the exposed (tetra) metal surface. 4 people can also use - film dry film resistance. Next, an exposure process using the pattern mask layer (10) is carried out, and then development is carried out. However, dry film solder resisting requires a curing step because of its similar properties to solder resist. The picker is as shown in Fig. 6, and the hunting is performed by using a metal paste to form a line pattern 16 and a second lead portion 180 and upper surfaces of the supporting portions 150. In particular, for example, a squeezing metal paste can be used to print a metal mask on a metal mask to form a stencil printing method. Therefore, in terms of thickness, fine and regular observation "(4). The line pattern of i # 16 〇 (ie, height) can be printed by the number of times (for example, performing & fire or more The printing makes the thickness thicker or controls the viscosity of the slurry to control. Furthermore, the width of each line pattern can be controlled by the width of the line pattern of the metal mask that is used to print the metal. To control. 13 201123391 Here, two of the copper (Cu) slurry, the aluminum (A1) slurry, and the magnesium (Mg) slurry, or the slurry, the (four) material, and the money material One or more mixed slurries may be used as the metal paste. Alternatively, other f-conducting materials may also be used as the metal (4), especially when the metal mass is made of copper, preferably The copper mass has the same damage and the same thermal conductivity as the metal substrate. The line patterns 16〇 must be spaced apart from each other, so that the line pattern 160 is insulated from the wafer pad portion 115. As shown in FIG. 1A, the line pattern 160 is formed. a view of the upper surface of the lead frame. In particular, 'printed metal as described above The circuit pattern formed by the material has a different form from the circuit pattern formed by the method of the fourth method. That is, in the conventional method of surname, the metal portions, such as the inner leads and the outer leads, are firstly used by the electric ore. And then forming a line pattern via an isotropic punch (i. such as etching). Therefore, the portion of the line pattern directly under the outer lead and the inner lead (positioned at the edge portion due to the engraving) is higher than the line pattern In the present invention, however, no money is engraved. Therefore, since the edge portion is not removed, a wiring pattern having a strange thickness is formed. Thus, the lead frame can be made thin. 1G is a plan view showing a line pattern (10) of a lead frame according to a first embodiment of the present invention. Referring to Fig. 1A, since the spacing between the line patterns (lnterVal) is not (four) narrow, a large number of signal transmission systems are available 14 201123391 Referring to Figure 7, the lower surface of the metal substrate 11〇 is completely removed due to rhyme. The reason why the lower surface of the metal substrate 11〇 is completely removed by the surname疋The lead portion 180 and the wafer pad portion us are electrically insulated. Therefore, the lead portion 180 and the wafer pad portion 15 are spaced apart from each other and the support portion 150 is inserted therein. Here, the steps of FIGS. 6 and 7 The order may be interchanged. In other words, the lower surface of the metal substrate 11G may be first (four) dropped, and the money is further formed into the line pattern 160. When the lower surface of the metal substrate 110 is first scribbled as described above, because of the support portions 150 and The lead portions 18 are simultaneously exposed, so that the wiring pattern 160 may be formed on the lower surface of the metal substrate UG, as shown in Fig. 3. However, if the lower surface of the metal substrate 110 is first removed, the thickness of the control substrate is controlled. It will be a bit difficult. For this reason, the steps of item 7 are preferably performed after the steps of Fig. 6. Figure 12 is a plan view showing the solder paste pad of the lead frame in accordance with the first embodiment of the present invention. Referring to Fig. 12, in the step of Fig. 7, the yoke is removed, so that the rupture of the rim reveals the lower surface of the pad portion 115 and the lower surface of the lead frame. Figure 13 shows a cross-sectional view of the wire frame after (4). The line portion 180 may have, for example, a support portion 15 〇 - which is not shown as shown on the lower left side of Fig. 13 15 201123391, or may be formed in the support portion 150, such as the stem + ^ shell not on the lower right side of Fig. 13. If the lead portion 180 is formed in an insulating layer a, although the die frame is continuously formed and the soldering process is performed, the strength is increased and increased. After performing the lower surface etching, a process of forming a squeaking re er, a wi bonding pad (or an inner lead), and a mounting pad (or an outer lead) is performed. As shown in Figure Θ 〇 〇. More specifically, the photoresist 〇 2 〇 is coated on both sides to expose and develop the light-shielding region S1 and the light-transmitting region S2 using the mask 13 . Therefore, the portion where the bonding pad 190 and the solder fixing pad 185 are to be formed is exposed. j Next, the exposed parts will be electroplated. The electric money process can be performed by a gold plating (Au) process after performing nickel plating (Ni). Alternatively, the gold (Au) can be electroplated on the nickel plating layer. Further, one or more of nickel, palladium (Pd) and gold (Au) may be replaced by silver (Ag). The completion of the plating layer is mainly performed by electroplating, but the electromineral and electroless plating can be used in combination. Finally, the photoresist is removed to form the wire bonding pads 19A and the solder pads 185 as shown in FIG. The upper surface of the wire bonding pad 19 is formed as shown in Fig. 5, and the thickness of the wiring pattern 160 and the thickness of the wire bonding pad 19 are controlled to be controlled. Therefore, the line pattern 160 and the wire bonding pads 190 201123391 may have the same or different heights. Therefore, the fine wiring pattern 16 of the present invention can be formed by a simple process as compared with the conventional manufacturing method using a ball grid BGA. Further, unlike the conventional structure, the wiring pattern 16 of the present invention is formed by the use of the - (four) printing method (paste printing __) by the role of the lead portion: playing the line pattern 160. The wiring pattern 160 is finer, the thickness is kept constant, and can be integrally formed. Fig. 14 to Fig. 25 are cross-sectional views showing a method of manufacturing a lead frame according to a second embodiment of the present invention. As shown in Fig. 14, a metal substrate 21 is prepared. 〇 (also <i.e., a body of a line). The metal substrate 210 is preferably made of copper (Cu), but may also be made of a metal member of a conductive material such as steel alloy, iron (Fe), or iron alloy. Here, the thickness of the metal substrate 210 is preferably 1 mil or less (lmil = 1/l, 〇〇〇inches), more preferably 5 mil or less. The photoresist 220 is formed on the metal substrate 210 and On the lower surface, here, a liquid liquid photoresist (LPR) or dry film photoresist (DFR) can be used as the photoresist 220. The photoresist 22 formed on the upper and lower surfaces of the metal substrate 210 can be used by using Photomask lithography (phot〇1 i thography p Rocess process is exposed and developed. Although the photoresist 220 may be coated only on the upper surface of the metal substrate 21, the photoresist 220 is preferably coated on both sides of the metal substrate 21 to protect it at 17 201123391 Next, as shown in Fig. 15, a plurality of insulating portion grooves 230, a wafer pad portion 240, and a plurality of lead portions 250 are formed by performing half etching. It must be noted that as shown in Fig. 15. The insulating portion recess 230, the wafer pad portion 240, and the lead portion 250 are not separated from each other. Then, a resin-coated copper foil (RCC) is prepared. The RCC 260 is compressed by applying heat and pressure. On the metal substrate 210. In this example, the portion coated by the resin 260b of the RCC 260 is compressed on the metal substrate 210. Here, the height of the compression is maintained at the copper substrate 260a and the wafer pad portion 240 and the lead portion 250. The degree of contact of the lower protrusions is as shown in Fig. 16. Therefore, the resin 260b of the RCC 260 is formed to fill the insulating portion groove 230 and surround all portions on the metal substrate 210, including the wafer pad portion 240 and the lower portion of the lead portion 250. Protrusion. Especially, such as As described, the copper substrate 260a is spaced apart from the highest point of the metal substrate 210 (i.e., the wafer pad portion 240 and the lower protrusion of the lead portion 250) by a predetermined pitch. Then 'coating the photoresist 220, then passing through the micro The shadowing process is exposed and developed, thereby forming an etching mask. The pattern of the etching mask is formed to expose the resin layer 260b of the lead portion 250 and the lower protrusion of the wafer pad portion 240. Next, the resin layer 260b of the upper projection portion of the lead portion 250 and the pad portion 24A is exposed by etching as shown in Fig.17. Thereafter, the 18 201123391 resin layer 260b of the lead portion 250 and the upper protrusion portion of the wafer pad portion 240 is removed via desmear, thereby exposing the lead portion 250 and the upper protrusion portion of the wafer pad portion 240. As shown in Figure is. Further, the resin layer 260b is separated by etching to form a plurality of support portions 270. Subsequently, the photoresist 220 is coated on the lower surface of the metal substrate 210 and the resin layer 260a of the remaining RCC 260 which is not etched away, and then exposed and developed via a lithography process. Thus, a pattern as shown in FIG. 19 is formed. The photoresist 220. Electroplating is performed on the photoresist 220 such that the inner leads 290a, the outer leads 290b, and the wafer pad metal portions 295a and 295b are formed as shown in FIG. Here, the outer lead 29A or the wafer pad metal portion 295b is formed on the other face on which the surface of the semiconductor wafer 400 is to be mounted later. When a semiconductor package is mounted on a PCB substrate, the face forming the outer lead 29a or the die pad metal portion 295b becomes a face that will contact the solder ball. The outer lead 290b or the wafer pad metal portion 295b has a lower height than the adjacent support portion 270. That is, the electric money is executed, so that the upper surface of the support portion wo is convex, and therefore it is higher than the upper surface of the outer lead 290b or the wafer pad metal portion 295b. Since the copper substrate 260a is spaced apart from the upper projection of the wafer pad portion 240 and the lead portion 250 by a predetermined interval, when the RCC 26 is compressed as shown in FIG. 3, the predetermined pitch is filled with the resin, so that Electric mines are feasible. Further, the copper substrate 260a is spaced apart from the upper projection portion of the support portion 270 and the wafer pad portion 240, and the lead portion 250 is almost 19 201123391 as the predetermined pitch, and the plating is performed on the difference in height. Therefore, the plated outer lead or the plated wafer metal portion may have a more concave shape than the support portion (which will be replaced later by the ridge structure). Therefore, the raised structure can be easily accomplished by using the Rcc 260, and no additional etch is required to form the raised structure. Next, a photosensitizer is coated on the upper and lower surfaces of the lead frame (the upper surface is coated to protect the component), and then exposed and developed via a lithography process, thereby forming a photoresist having a pattern. 220 is not as shown in FIG. Next, a pattern of the engraved mask is constructed to form a line pattern of the lead frame. Therefore, as shown in Fig. 22, the lead portion 25G and the wafer pad portion 24G are disconnected by the remaining moment, and the support portion 270 is supported between the lead portion 250 and the wafer pad portion 24 (). Further, by using the resin 2_ as a material to form the support portion (10), the wafer soldering portion and the lead portion are electrically insulated from each other. Further, it is preferable to form a groove by the pad in the pad pad portion 240. Then the semiconductor wafer is completely mounted on the grooved towel. The semiconductor wafer 400, the inner leads 290a, and the 曰Η, ί·θ·ϋτ η and the day mat metal portions 295a are electrically connected by wires 300. + , 丄 八 , 曰 u (four) connection. In this example, the semiconductor crystal; M00 is mounted on the crucible 24. Groove. Therefore, the adhesion of the wafer is increased: + The thickness of the conductor chip package is reduced. Here, the figure U shows that the structure is upside down and then split, and the state of the upper piece is not shown. This is because the RCC 260' as shown in Fig. 16 is compressed in order to perform 20 201123391. Therefore, the other side of the face on which the semiconductor wafer is mounted is upside down. Next, as shown in FIG. 24, the lead frame and the semiconductor wafer are sealed by a sealant (sea 1 ed) in a compact (bund 1 e ), and then a mold resin is used ( For example, epoxy resin molding material (Ep〇xy M〇1ding Co_und, EMC)) 5 (10) is used for agricultural closure. As shown in Fig. 25, the copper (Cu) substrate as the RCC 26 谨 is removed, and the function of the steel (Cu) substrate 26 为 is to prevent the number of difficult and (4) process paper money _ 曲 (Qing) method, can be efficient And a method of manufacturing a wire frame via a ridge structure As described above, a lead frame which prevents the occurrence of warpage during the manufacturing process to improve the adhesion strength of the soldering is manufactured according to the lead frame of the present invention. Figure 26 is a cross-sectional view showing the lead frame manufactured using the second embodiment of the present invention. Referring to Fig. 26, a lead frame (10) and a lead portion 25 according to the present embodiment. The support portion 270, the inner lead 2 includes the wafer solder portion and the wafer solder metal portion, and 2: the outer lead _, and the lead portion are spaced apart from each other, so that it = the pad solder portion 240 = raw insulation. Furthermore, the function of the cut portion 270 is two: 2: ° 24 〇 and the bottom of the lead portion 250. Further, the tooth day pad 4 horizontal portion 25Ga and the - vertical line portion 25G include - 4 250b. From the upper surface of the horizontal portion 250a,

S 21 201123391 内引線290a形成在接近晶片焊墊部240的位置，而外引線 290b形成在垂直部250b的下表面。晶片焊墊金屬部295a 和295b分別形成在晶片焊墊部240的上和下表面。晶片焊 墊金屬部295a和295b最好形成在晶片焊墊部240的整個 表面以改善半導體晶片400的導熱性。 特別是外引線290b的下表面或晶片焊墊金屬部295b 的下表面形成比鄰近的支撐部270來的高。當形成如上所 述的外引線290b或晶片焊墊金屬部295b較支撐部270更 内凹的隆起結構時’得以增加焊接過程（s〇ldering process)的穩定性。這是因為在焊接過程中能夠有優越的 黏著強度。 再者’根據本發明的方法’ RCC 260被壓縮而不需要 蝕刻金屬基板，而一隆起結構能藉由使用除膠渣（d esmear) 來僅移除樹脂260b。 當如同以上所述在沒有蝕刻製程下形成隆起結構時， 因為邊緣部（edge portions)未被蝕刻而被去除，支撐部 270的厚度可規則地維持。因此，在隆起結構空間内，錫 球附著在隆起結構的空間内可被更精巧地固定。 圖27至圖39為根據本發明第三實施例之引線架製造 方法的剖視圖。 首先，如圖27所示，準備一金屬基板310(亦即，引 22 201123391 線架的主體）。金屬基板310最好是由銅（Cu)所製成，但也 可由一金屬構件所製成，例如為傳導材料的銅合金、鐵 (Fe)、或鐵合金。一光阻320形成在金屬基板310的上和 下表面上。這裡，一種液體狀的液態光阻（LPR)320或膜態 的乾膜光阻（DFR)320可被作為光阻320。在此實施例_， 為易於描述，故假設使用乾膜光阻（DFR)。光阻320藉由使 用光罩（未顯示）的微影製程而曝光與顯影於金屬基板31〇 的上和下表面。 雖然光阻320可僅塗佈在金屬基板310的下表面上， 光阻最好是塗佈在金屬基板310的雙面以保護在下方的元 件。藉由如上所述而形成的圖樣罩幕層（pattern masks) 執行半蝕刻，藉此形成多個引線部35〇、多個絕緣部凹槽 330、以及一晶片焊墊部360，如圖28所示。必須注意的 是引線部350和晶片焊墊部360尚未斷開而是。再者，最 好餘刻掉金屬基板310 # 2/3或更多的深度作為穩定製程 的目的。 、接續’如圖29所示，塗佈一絕緣材料在金屬基板3: 的了方，如此以形成-支撐部37G。—背架38()形成在 =州的底部。這裡，支撐部37()形成來填充絕緣部 3 3〇以及圍繞引線部350和晶片焊墊部36〇的下突起剖 特別是建構支撐部370的絕緣材料是由環氧樹脂或玻免 23 201123391 維所構成，因此其作為支撐體和絕緣體。再者，背架380 形成在支撐部370的底部，其作用為防止在習知技藝中慢 性產生的輕曲現象。這裡，背架380最好是由銅（Cu)所製 成，但不限定於此。 接著，如圖30所示，一 DFR是壓合在背架380的下表 面和金屬基板310的上表面上（亦即，為了保護餘刻後的元 件），然後經由曝光和顯影來完成圖案。圖案形成在對應背 架380將被暴露出的位置。接著，蝕刻背架380的底部以 暴露出支撐部370的部份，其低於引線部350和晶片焊墊 部360的下突起部，如圖31所示。然後，執行一化學研磨 製程於支撐部350暴露出的部份，藉而穩定暴露出引線部 350和晶片焊墊部360的下突起部，如圖32所示。接著， 剝落DFR以暴露出金屬基板310的上表面和背架380的下 表面，如圖33所示。 接著，如圖34所示，DFR 320壓合在金屬基板310的 上表面和背架380的下表面，而内引線390a、外引線390b、 以及晶片焊墊金屬部395a和395b將形成的部份則經曝光 和顯影。然後，如圖35所示，藉由電鍍，内引線390a形 成在引線部的350的水平部上表面上，而外引線390b形成 在引線部350的垂直部下表面上。再者，晶片焊墊金屬部 395a和395b可形成在晶片焊墊部360的上和下表面上。 24 201123391 特別是内引線390a、外引線390b、以及晶片焊墊金屬部 395a和395b最好鑛覆上鎳（Ni)、Is (Pd)、金（Au)、或銀 (Ag)，而但鑛覆上兩種或以上之金屬層更好。 再者，外引線390b最好具有較支撐部370更内凹的隆 起結構。該隆起結構的功能為在焊接製程中，結合錫球到 外引線390b，且同時於焊接過程中，固定和穩固地連結錫 球到支撐部370。 接著，為了保護元件，DFR壓合在引線架的底部，如 圖36所示。DFR的上部經曝光及顯影而暴露出引線部350 和晶片焊墊部360將斷開的部份（或相互間隔開）。 然後，引線部350和晶片焊墊部360藉由如圖37所示 的蝕刻製程而斷開，而形成線路圖案（亦即，斷開的引線部 的水平部）。或者，將DFR剝離，安裝一半導體晶片300在 晶片焊墊部360上、以及電性連結半導體晶片300和内引 線390a的導線400結合到半導體晶片300。這裡，引線部 350’為可安排路徑（routed)的，因此能夠減少線路的輸入 和輸出距離而能實現覆晶結構。再者，由於減少了導線400 的長度，因此成本得以降低。接著，引線架和半導體晶片 藉由密封劑（sealant)而被封閉（sealed)，然後使用壓模樹 脂（moId resin)(例如環氧樹脂模封材料，EMC))進行封 裝，如此以完成一半導體封裝，如圖38所示。S 21 201123391 The inner lead 290a is formed at a position close to the wafer pad portion 240, and the outer lead 290b is formed at the lower surface of the vertical portion 250b. Wafer pad metal portions 295a and 295b are formed on the upper and lower surfaces of the wafer pad portion 240, respectively. The wafer pad metal portions 295a and 295b are preferably formed on the entire surface of the wafer pad portion 240 to improve the thermal conductivity of the semiconductor wafer 400. In particular, the lower surface of the outer lead 290b or the lower surface of the wafer pad metal portion 295b is formed higher than the adjacent support portion 270. When the outer lead 290b or the wafer pad metal portion 295b as described above is formed to be more concave than the support portion 270, the stability of the soldering process is increased. This is because of the superior adhesion strength during the soldering process. Further, the method according to the present invention RCC 260 is compressed without etching the metal substrate, and a raised structure can remove only the resin 260b by using desmear. When the ridge structure is formed without an etching process as described above, since the edge portions are removed without being etched, the thickness of the support portion 270 can be regularly maintained. Therefore, in the embossed structure space, the solder balls are attached to the space of the ridge structure to be more delicately fixed. 27 to 39 are cross-sectional views showing a method of manufacturing a lead frame in accordance with a third embodiment of the present invention. First, as shown in Fig. 27, a metal substrate 310 (i.e., the main body of the lead frame 201123391) is prepared. The metal substrate 310 is preferably made of copper (Cu), but may be made of a metal member such as a copper alloy of a conductive material, iron (Fe), or an iron alloy. A photoresist 320 is formed on the upper and lower surfaces of the metal substrate 310. Here, a liquid liquid photoresist (LPR) 320 or a film state dry film photoresist (DFR) 320 can be used as the photoresist 320. In this embodiment, for ease of description, it is assumed that dry film photoresist (DFR) is used. The photoresist 320 is exposed and developed on the upper and lower surfaces of the metal substrate 31 by a lithography process using a photomask (not shown). Although the photoresist 320 may be coated only on the lower surface of the metal substrate 310, the photoresist is preferably coated on both sides of the metal substrate 310 to protect the underlying components. The half etching is performed by the pattern masks formed as described above, thereby forming a plurality of lead portions 35, a plurality of insulating portion grooves 330, and a wafer pad portion 360, as shown in FIG. Show. It must be noted that the lead portion 350 and the wafer pad portion 360 have not been disconnected yet. Furthermore, it is preferable to remove the depth of the metal substrate 310 # 2/3 or more as a stable process. Continuation As shown in Fig. 29, an insulating material is applied to the metal substrate 3: such that the -support portion 37G is formed. - Back frame 38 () is formed at the bottom of the state. Here, the support portion 37 () is formed to fill the insulating portion 33 and the lower protrusion around the lead portion 350 and the wafer pad portion 36A, in particular, the insulating material for constructing the support portion 370 is made of epoxy resin or glass-free 23 201123391 It consists of a dimension, so it acts as a support and insulator. Further, the back frame 380 is formed at the bottom of the support portion 370, which functions to prevent the occurrence of a gentle phenomenon caused by the slowness in the prior art. Here, the back frame 380 is preferably made of copper (Cu), but is not limited thereto. Next, as shown in Fig. 30, a DFR is pressed against the lower surface of the back frame 380 and the upper surface of the metal substrate 310 (i.e., to protect the remaining elements), and then the pattern is completed via exposure and development. The pattern is formed at a position where the corresponding back frame 380 is to be exposed. Next, the bottom of the back frame 380 is etched to expose a portion of the support portion 370 which is lower than the lower projections of the lead portion 350 and the wafer pad portion 360, as shown in FIG. Then, a chemical polishing process is performed on the exposed portion of the support portion 350, whereby the lower projections of the lead portion 350 and the wafer pad portion 360 are stably exposed, as shown in Fig.32. Next, the DFR is peeled off to expose the upper surface of the metal substrate 310 and the lower surface of the back frame 380 as shown in FIG. Next, as shown in FIG. 34, the DFR 320 is pressed against the upper surface of the metal substrate 310 and the lower surface of the back frame 380, and the inner lead 390a, the outer lead 390b, and the wafer pad metal portions 395a and 395b are formed. Then exposed and developed. Then, as shown in Fig. 35, the inner lead 390a is formed on the upper surface of the horizontal portion of the lead portion 350 by electroplating, and the outer lead 390b is formed on the lower surface of the vertical portion of the lead portion 350. Further, wafer pad metal portions 395a and 395b may be formed on the upper and lower surfaces of the wafer pad portion 360. 24 201123391 In particular, the inner lead 390a, the outer lead 390b, and the wafer pad metal portions 395a and 395b are preferably coated with nickel (Ni), Is (Pd), gold (Au), or silver (Ag), but the mine It is better to cover two or more metal layers. Further, the outer lead 390b preferably has a embossed structure that is more concave than the support portion 370. The function of the ridge structure is to bond the solder balls to the outer leads 390b during the soldering process, and at the same time, securely and securely bond the solder balls to the support portion 370 during the soldering process. Next, to protect the components, the DFR is pressed against the bottom of the lead frame as shown in Figure 36. The upper portion of the DFR is exposed and developed to expose portions (or spaced apart) from which the lead portion 350 and the wafer pad portion 360 are to be broken. Then, the lead portion 350 and the wafer pad portion 360 are broken by an etching process as shown in Fig. 37 to form a wiring pattern (i.e., a horizontal portion of the broken lead portion). Alternatively, the DFR is peeled off, and a semiconductor wafer 300 is mounted on the wafer pad portion 360, and the wires 400 electrically connecting the semiconductor wafer 300 and the inner leads 390a are bonded to the semiconductor wafer 300. Here, the lead portion 350' is routed, so that the input and output distances of the line can be reduced and the flip chip structure can be realized. Moreover, since the length of the wire 400 is reduced, the cost is reduced. Then, the lead frame and the semiconductor wafer are sealed by a sealant, and then packaged using a mod resin (for example, an epoxy molding material, EMC), thereby completing a semiconductor. Package, as shown in Figure 38.

25 S 201123391 接著，如圖39所示，藉由蝕刻製程移除背架38〇。在 所有製程中’背架的功能用來固定引線架的整個框架 (frame)，因此能夠顯著地改善趣曲現象。 唯以上所述者，僅為本發明之較佳實施例，當不能以 之限制本發明的。即大凡依本發明申料圍所做 之均等變化及修飾，仍將不失本發明之要義所在，亦不脫 離本發明之精神和範圍。 【圖式簡單說明】25 S 201123391 Next, as shown in FIG. 39, the back frame 38〇 is removed by an etching process. In all processes, the function of the back frame is used to fix the entire frame of the lead frame, thus significantly improving the interesting phenomenon. The above is only the preferred embodiment of the present invention, and the present invention is not limited thereto. It is to be understood that the scope of the present invention is not limited by the spirit and scope of the present invention. [Simple description of the map]

圖1至圖9為根據本發明第—實施例之引線架製造 剖視圖。 / J 圖10為根據本發明第一實施例顯示引線 荦BRIEF DESCRIPTION OF THE DRAWINGS Figures 1 through 9 are cross-sectional views showing the manufacture of a lead frame in accordance with a first embodiment of the present invention. / J Fig. 10 shows a lead wire according to a first embodiment of the present invention.

的平面視圖。 吩團茱IbU 圖12根據本發明第一管 # a丨3, A * 知月弟實施例顯不引線架的錫膏焊墊 (solder paste pad)部將被安裝的平面視圖。 坪墊 線部的 圖13根據本發明第—實施例顯示引線架之該 放大剖視圖。 ~ 1 圖14至圖25為根據本發明 的剖視圖。 圖2 6為藉由根據本發明第 造出的引線架的剖視圖。 第二實施例之引線架製造方法 二實施例之引線架製造方法製 26 201123391 圖27至圖39為根據本發明第三實施例之引線架製造方法 的剖視圖。 【主要元件符號說明】 110 金屬基板 115 晶片焊墊部 120 光阻 130 光罩 150 支撐部 160 線路圖案 180 引線部 185 焊錫固定墊 190 打線焊墊 210 金屬基板 220 光阻 230 絕緣部凹槽 240 晶片焊墊部 250 引線部 250a 水平部 250b 垂直部 260 樹脂包覆銅箔 260a 銅基板 260b 樹脂 27 201123391 270 支撐部 290a 内引線 290b 外引線 295a、 295b 晶片焊墊金屬部 300 導線 310 金屬基板 320 光阻 330 絕緣部凹槽 350 引線部 360 晶片焊墊部 370 支撐部 380 背架 390a 内引線 390b 外引線 395a、 395b 晶片焊墊金屬部 400 半導體晶片 500 孩乳樹脂核封材料 SI 遮光區域 S2 光傳輸區域 28Plane view.吩 b IbU Figure 12 is a plan view showing the first paste of the solder paste pad portion of the first tube in accordance with the first tube of the present invention # a丨3, A * 知月弟. Fig. 13 is a magnified cross-sectional view showing a lead frame in accordance with a first embodiment of the present invention. ~1 Figures 14 through 25 are cross-sectional views in accordance with the present invention. Figure 26 is a cross-sectional view of the lead frame constructed by the first embodiment of the present invention. The lead frame manufacturing method of the second embodiment is a lead frame manufacturing method according to the second embodiment. 26 201123391 FIGS. 27 to 39 are cross-sectional views showing a method of manufacturing a lead frame according to a third embodiment of the present invention. [Main component symbol description] 110 metal substrate 115 wafer pad portion 120 photoresist 130 photomask 150 support portion 160 wiring pattern 180 lead portion 185 solder fixing pad 190 wire bonding pad 210 metal substrate 220 photoresist 230 insulating portion groove 240 wafer Pad portion 250 lead portion 250a horizontal portion 250b vertical portion 260 resin-coated copper foil 260a copper substrate 260b resin 27 201123391 270 support portion 290a inner lead 290b outer lead 295a, 295b wafer pad metal portion 300 wire 310 metal substrate 320 photoresist 330 Insulation groove 350 Lead portion 360 Wafer pad portion 370 Support portion 380 Back frame 390a Inner lead 390b Outer lead 395a, 395b Wafer pad metal portion 400 Semiconductor wafer 500 Latex resin core sealing material SI Shading area S2 Light transmission area 28

Claims (1)

201123391 七、申請專利範圍： 1. 一種引線架，包括： 夕個引線°卩，母—該引線部包含一垂直部盘一水平 部； /、 -晶片焊㈣藉由絕緣材料所製叙多個支撐部從 該些引線部斷開； 多個内引線設置在鄰近該晶片焊墊部和形成在該些 引線部的該些水平部的一上表面上；以及 夕個外引線形成在該些引線部的該些垂直部的一下 表面卜。 2·如申請專利範圍第1項所述之引線架，其中該些水平部 藉由使用一金屬漿料印製在該些垂直部上。 3 > .如申凊專利範圍第1項所述之引線架，其中該些支撐部 的一下表面較圍繞部突起。 4’如申請專利範圍第1項所述之引線架’其中該絕緣材料 包括環氧樹脂或玻璃纖維。 5. 如申請專利範圍第2項所述之引線架，其中該水平部具 有一恆定厚度。 6. 如申請專利範圍第3項所述之引線架’更包括多個晶片 焊塾金屬部形成在該晶片焊墊部的一上表面或一下表 面。 29 201123391 7·如:請專利範圍第5項所述之引線架，其中在該垂直部 的一朝上方向的寬度窄於該垂直部的-朝下方向的寬 度。 8·如申請專利範圍第4項所述之引線架，其中該些内引線 或該些外引線由兩種或更多種的金屬堆疊形成。 9.如申請專利第8項所述之引線架，其中朗種或更 多種金屬係選自由鎳⑹、纪⑽、金（Au)、及銀⑽ 所組成的群組。 忉.一種引線架的製造方法，包括步驟： (a) 藉由執行半蝕刻於一金屬基板上以形成多個支撐 部凹槽、一晶片焊墊部、以及多個引線部； (b) 藉由填充一絕緣材料於該些支撐部凹槽以形成多 個支撐部；以及 (c) 藉由蝕刻該金屬基板分離該晶片焊墊部和該些引 線部。 如申請專利第10項所述之製造方法，其中該步驟 (c)包括藉由印製一金屬漿料在該些引線部上以形成線 路圖案和藉由钕刻該金屬基板形成該線路圖案表面的 另一面而分離該晶片焊塾部和該些引線部。 12.如申請專利範圍第項所述之製造方法，其中： 該步驟（b)包括壓縮樹脂包覆銅箔（RCC)於該些支撐 30 201123391 部凹槽，以及 該步驟（c)包括步驟 (cl)暴路该些引線部和該晶片焊墊部的突起表 面； (c2)藉由電鑛該金屬基板的雙側以形成多個内引 線和夕個外引線’其中該些外引線經電鑛使該些外引 線低於環繞部； (c3)藉由蝕刻該金屬基板分離該晶片焊墊部和該 些引線部；以及 (c4)移除該銅（cu)基板。 13.如申請專利範圍第項所述之製造方法，其中： 忒步驟（b)包括藉由该絕緣材料填充該些支樓部凹槽 而形成該些支撐部以及形成一背架在該些支撐部上，以 該步驟（c)包括步驟： (cl)暴露該些引線部和該晶片焊墊部的突起表 面； (c2)藉由電鍵該金屬基板的雙側以形成多個内引 線和多個外引線； (c3)藉由钱刻該金屬基板分離該晶片焊墊部和哕 些引線部以及移除該背架。 201123391 14. 如申請專利範圍第11項所述之製造方法，其中該步驟 (c)的該金屬漿料包括銅（Cu)、铭（A1)、以及鎂（Mg) 中的其中一種或多種。 15. 如申請專利範圍第12項所述之製造方法，其中該步驟 (cl)包括： 藉由執行一微影製程以暴露出該些支撐部在該些引 線部和該晶片焊墊部的該突起表面；以及 藉由使用除膠渣（desmear)移除暴露出的該些支撑 部。 16. 如申請專利範圍第11項或第14項所述之製造方法，其 中該步驟（c)包括印製該金屬漿料使該線路圖案具有一 恆定厚度。 17. 如申請專利範圍第13項所述之製造方法，其中該步驟 (b)的該背架包括銅。 18. 如申請專利範圍第17項所述之製造方法，其中該步驟 (cl)包括： 藉由蝕刻該背架以暴露出在該些引線部和該晶片焊 墊部的該突起表面的該些支撐部；以及 藉由化學研磨移除暴露出的該些支撐部。 19. 如申請專利範圍第18項所述之製造方法，其中該步驟(c2)包 括藉由連續地電鍍鎳(Ni)、鈀（Pd)、金(Au)、以及銀(Ag)中 32 201123391 的兩種或多種金屬而形成該些内引線和該些外引線。 33201123391 VII. Patent application scope: 1. A lead frame, comprising: a lead wire 卩, a mother--the lead portion includes a vertical portion of a horizontal portion; /, - wafer welding (four) is made of a plurality of insulating materials The support portion is disconnected from the lead portions; a plurality of inner leads are disposed adjacent to the wafer pad portion and an upper surface of the horizontal portions formed on the lead portions; and an outer lead is formed on the leads The lower surface of the vertical part of the part. 2. The lead frame of claim 1, wherein the horizontal portions are printed on the vertical portions by using a metal paste. The lead frame of claim 1, wherein the lower surface of the support portion protrudes from the surrounding portion. 4' The lead frame as described in claim 1, wherein the insulating material comprises epoxy or fiberglass. 5. The lead frame of claim 2, wherein the horizontal portion has a constant thickness. 6. The lead frame as described in claim 3, further comprising a plurality of wafer solder metal portions formed on an upper surface or a lower surface of the wafer pad portion. The lead frame of claim 5, wherein the width of the vertical portion in an upward direction is narrower than the width of the vertical portion in the downward direction. 8. The lead frame of claim 4, wherein the inner leads or the outer leads are formed from a stack of two or more metals. 9. The lead frame of claim 8, wherein the seed or more metal is selected from the group consisting of nickel (6), ge (10), gold (Au), and silver (10). A method of manufacturing a lead frame, comprising the steps of: (a) forming a plurality of support portion grooves, a wafer pad portion, and a plurality of lead portions by performing half etching on a metal substrate; (b) borrowing Forming a plurality of support portions by filling an insulating material in the support portion grooves; and (c) separating the wafer pad portion and the lead portions by etching the metal substrate. The manufacturing method of claim 10, wherein the step (c) comprises forming a line pattern on the lead portions by printing a metal paste and forming the line pattern surface by engraving the metal substrate The other side of the wafer is separated from the pad portion and the lead portions. 12. The manufacturing method according to claim 1, wherein: the step (b) comprises compressing a resin-coated copper foil (RCC) on the support 30 201123391 grooves, and the step (c) comprises the step ( Cl) exposing the lead portions and the protruding surface of the wafer pad portion; (c2) forming a plurality of inner leads and outer outer leads by electro-mining the both sides of the metal substrate, wherein the outer leads are electrically charged The ore causes the outer leads to be lower than the surrounding portion; (c3) separating the wafer pad portion and the lead portions by etching the metal substrate; and (c4) removing the copper (cu) substrate. 13. The manufacturing method according to claim 1, wherein: 忒 step (b) comprises filling the plurality of groove portions by the insulating material to form the support portions and forming a back frame on the supports In the step, the step (c) includes the steps of: (cl) exposing the lead portions and the protruding surface of the wafer pad portion; (c2) forming a plurality of inner leads and more by electrically bonding the two sides of the metal substrate. An outer lead; (c3) separating the wafer pad portion and the lead portions and removing the back frame by engraving the metal substrate. The manufacturing method of claim 11, wherein the metal paste of the step (c) comprises one or more of copper (Cu), indium (A1), and magnesium (Mg). 15. The manufacturing method of claim 12, wherein the step (cl) comprises: exposing the support portions to the lead portions and the wafer pad portion by performing a lithography process a raised surface; and the exposed portions of the support are removed by using desmear. 16. The method of manufacture of claim 11, wherein the step (c) comprises printing the metal paste to provide the line pattern with a constant thickness. 17. The method of manufacture of claim 13, wherein the backing of the step (b) comprises copper. 18. The manufacturing method of claim 17, wherein the step (cl) comprises: etching the back frame to expose the protrusion surfaces of the lead portions and the wafer pad portion a support portion; and removing the exposed support portions by chemical grinding. 19. The manufacturing method according to claim 18, wherein the step (c2) comprises continuously electroplating nickel (Ni), palladium (Pd), gold (Au), and silver (Ag) 32 201123391 The inner leads and the outer leads are formed by two or more metals. 33
TW099138153A 2009-11-11 2010-11-05 Lead frame and manufacturing method of the same TW201123391A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR1020090108497A KR101168413B1 (en) 2009-11-11 2009-11-11 Leadframe and method of manufacturig same
KR1020090108907A KR101197777B1 (en) 2009-11-12 2009-11-12 Leadframe and method of manufacturig same
KR1020090116935A KR101107756B1 (en) 2009-11-30 2009-11-30 Leadframe and method of manufacturig same

Publications (1)

Publication Number Publication Date
TW201123391A true TW201123391A (en) 2011-07-01

Family

ID=43992190

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099138153A TW201123391A (en) 2009-11-11 2010-11-05 Lead frame and manufacturing method of the same

Country Status (2)

Country Link
TW (1) TW201123391A (en)
WO (1) WO2011059205A2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681377A (en) * 2012-09-01 2014-03-26 万国半导体股份有限公司 Semiconductor device with bottom metal base and preparing method thereof
CN106328624A (en) * 2015-07-01 2017-01-11 艾马克科技公司 Method for fabricating semiconductor package having multi-layer encapsulated conductive substrate and structure
TWI642145B (en) * 2016-04-06 2018-11-21 海成帝愛斯股份有限公司 Semiconductor package substrate and manufacturing method thereof
TWI719994B (en) * 2015-12-08 2021-03-01 美商艾馬克科技公司 Method for fabricating semiconductor package and semiconductor package using the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9087828B2 (en) 2013-03-12 2015-07-21 Alpha & Omega Semiconductor Incorporated Semiconductor device with thick bottom metal and preparation method thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3091779B2 (en) * 1991-11-01 2000-09-25 凸版印刷株式会社 Method for manufacturing lead frame for semiconductor device
JPH05326819A (en) * 1992-05-15 1993-12-10 Nec Kyushu Ltd Lead frame for semiconductor device
JPH09307043A (en) * 1996-05-10 1997-11-28 Dainippon Printing Co Ltd Lead frame member and manufacture thereof, and semiconductor device using lead frame member
US7875988B2 (en) * 2007-07-31 2011-01-25 Seiko Epson Corporation Substrate and manufacturing method of the same, and semiconductor device and manufacturing method of the same
JP4984253B2 (en) * 2007-12-25 2012-07-25 大日本印刷株式会社 Manufacturing method of semiconductor device and manufacturing method of substrate for semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681377A (en) * 2012-09-01 2014-03-26 万国半导体股份有限公司 Semiconductor device with bottom metal base and preparing method thereof
CN103681377B (en) * 2012-09-01 2016-09-14 万国半导体股份有限公司 Semiconductor device with bottom metal pedestal and preparation method thereof
CN106328624A (en) * 2015-07-01 2017-01-11 艾马克科技公司 Method for fabricating semiconductor package having multi-layer encapsulated conductive substrate and structure
TWI719994B (en) * 2015-12-08 2021-03-01 美商艾馬克科技公司 Method for fabricating semiconductor package and semiconductor package using the same
US11145588B2 (en) 2015-12-08 2021-10-12 Amkor Technology Singapore Holding Pte. Ltd. Method for fabricating semiconductor package and semiconductor package using the same
TWI642145B (en) * 2016-04-06 2018-11-21 海成帝愛斯股份有限公司 Semiconductor package substrate and manufacturing method thereof
US10643933B2 (en) 2016-04-06 2020-05-05 Haesung Ds Co., Ltd. Semiconductor package substrate and manufacturing method therefor

Also Published As

Publication number Publication date
WO2011059205A3 (en) 2011-10-13
WO2011059205A2 (en) 2011-05-19

Similar Documents

Publication Publication Date Title
EP2239773B1 (en) Manufacturing method of a semiconductor chip package
US7923367B2 (en) Multilayer wiring substrate mounted with electronic component and method for manufacturing the same
TWI325626B (en) Method for packaging a semiconductor device
JP5605222B2 (en) Three-dimensional mounting semiconductor device and manufacturing method thereof
TWI437647B (en) Thermally enhanced semiconductor assembly with bump/base/flange heat spreader and build-up circuitry
TWI364101B (en) Semiconductor package and a manufacturing method thereof
JP2017038075A (en) Stackable molded ultra small electronic package including area array unit connector
US8294253B2 (en) Semiconductor device, electronic device and method of manufacturing semiconductor device, having electronic component, sealing resin and multilayer wiring structure
WO2012137714A1 (en) Semiconductor device and method for manufacturing semiconductor device
TW201041105A (en) Substrate having single patterned metal layer, and package applied with the same, and methods of manufacturing the substrate and package
US8338924B2 (en) Substrate for integrated circuit package with selective exposure of bonding compound and method of making thereof
JP2009506572A (en) Microfeature assemblies including interconnect structures and methods for forming such interconnect structures
JP2015517745A (en) Substrate-less stackable packages using wirebond interconnects
JP2007115774A (en) Method of manufacturing semiconductor device
JP2004235523A (en) Semiconductor device and manufacturing method therefor
TWI446508B (en) Coreless package substrate and method of making same
TW201142998A (en) System-in-package
US6936927B2 (en) Circuit device having a multi-layer conductive path
TW201123391A (en) Lead frame and manufacturing method of the same
TW201123326A (en) Method of manufacturing substrate for flip chip and substrate for flip chip manufactured using the same
TW200910561A (en) Packaging substrate structure with capacitor embedded therein and method for fabricating the same
TWI459514B (en) A substrate for selective exposing a solder for an integrated circuit package and a method of manufacturing the same
KR100843705B1 (en) Semiconductor chip package having metal bump and methods of fabricating the same
TWI430418B (en) Leadframe and method of manufacuring the same
TW201036113A (en) Substrateless chip package and fabricating method