TWI430418B - Leadframe and method of manufacuring the same - Google Patents

Description

Lead frame and method of manufacturing same

The present invention claims the Korean Patent No. 10-2009-0106142 filed on Nov. 04, 2009, and the Korean Patent No. 10-2009-0108386 filed on Nov. 11, 2009, and filed on November 25, 2009. Korean Patent No. 10-2009-0114287, the entire disclosure of which is incorporated herein by reference.

The present invention relates to a lead frame and a method of manufacturing the same.

The semiconductor package is a process for electrically connecting a wafer fabricated by a wafer process to be used as an electronic component and sealing and sealing the wafer to protect the substrate from external impact.

Typically, hundreds of wafers having the same circuit are formed on the same wafer, but such individual wafers do not operate as electronic components. Therefore, it is necessary to form a wire to connect the wafer to an external device to receive an electrical signal from the external device, and to transfer the processed electrical signal from the wafer to the external device. Since the wafer includes a very fine line pattern, the wafer is susceptible to damage due to moisture, dust, and external impact. That is, the wafer formed on the surface of the wafer is not a finished product and needs to be used as an electronic component until the wafer is mounted on a printed circuit board (PCB). Therefore, the semiconductor package process can be used to make the wafer on the wafer operate as a separate electronic component by forming a wire on the wafer. Furthermore, the semiconductor packaging process protects the wafer and wires from external impact by hermetic and encapsulation. With the package order, the wafer on the wafer can become the final product.

In semiconductor packaging processes, a lead frame plays a major role in mounting the chip and providing input/output means for transmitting signals. A variety of different types of lead frames have been used to transmit highly integrated signals.

In a conventional method of forming a lead frame, an etching method or a stamping method is used to form a die pad and a lead unit. However, using conventional methods to form a multi-column leadframe for highly integrated semiconductors is not an easy task.

Recently, a two-stage etching method has been introduced to form a lead frame. However, the number of lead pins is limited by the limitations of the inner lead pitch reduction in the two-stage etching process. Further, the support unit for maintaining the gap between the wafer pad unit and the lead unit and the support lead frame is made of a thin polyimide layer, and therefore, the supporting force is weak.

In addition to the weak support force, the lead frame has a problem of durability because the lead frame does not have a structure for fixing the solder ball to the outer lead during the soldering process.

If the etching process is performed after the plating process, electroplating is performed due to the rapid plating speed of the plating. However, it is difficult to form a fine plating pattern due to an electroplating process, and it is also difficult to form a plating layer having a superior structure by an electroplating process to reduce plating degeneration. In addition, a plating process requires a rectifier.

Further, copper is usually used as a raw material for the lead frame pattern, but copper is liable to expand due to environmental changes such as temperature and humidity. The expansion of copper can cause significant defects for semiconductor packages having fine structures. Because the expansion of the copper can electrically connect the lead unit that should not be electrically connected to the wafer pad unit or other lead unit.

Accordingly, the present invention is intended to solve the problems of the conventional lead frame and its method of manufacture.

It is an object of the present invention to provide a lead frame and a method of fabricating the same for forming a finer wiring pattern, improving solder ball bonding, and increasing the physical strength of the lead frame.

Another object of the present invention is to provide a lead frame and a method of fabricating the same for preventing expansion due to environmental variations and fine pattern plating and superior plating structure for minimizing plating variations.

It is still another object of the present invention to provide a lead frame having enhanced physical strength and a method of manufacturing the same.

An object of the present invention is to provide a lead frame comprising a lead unit having a vertical portion and a horizontal portion, and a wafer pad unit, wherein a support unit formed of an insulating material is separated from the lead unit and an inner lead is formed. An upper surface near the wafer pad unit and the horizontal portion of the lead unit, and an outer lead are formed on the lower surface of the vertical portion of the lead unit.

The lower surface of the support unit may protrude from the outer surface of the outer lead and the wafer pad unit.

The lead frame may further include an upper metal layer formed on an upper surface or a lower surface of the wafer pad unit, wherein the inner leads may extend to surround the side of the horizontal portion toward the wafer pad unit or may be from a side of the horizontal portion Separated by a predetermined gap.

The lead frame may further include a support unit, wherein the support unit may include an upper support unit surrounding the upper surface of the horizontal portion of the lead unit, and a lower support part of the lower support unit surrounding the horizontal portion of the lead unit.

The lead frame may further include a support unit, wherein the support unit may include an upper support unit formed to fill a separation space between the wafer pad unit and the lead unit, and a lower support unit formed to support a lower portion of the horizontal portion of the lead unit.

The lead frame may further include an insulating layer formed on a horizontal portion of the lead unit or an upper surface of the support unit.

The lead frame may further include a wafer pad metal layer formed on the upper surface of the wafer pad unit.

The upper metal layer formed on the upper surface of the wafer pad unit may extend to surround the side of the wafer pad unit toward the lead unit or may be separated by a predetermined gap from the side of the wafer pad unit. The wafer pad unit includes a step.

The upper metal layer of the wafer pad unit may be formed on the upper step of the step, and the lead frame may further include a lower metal layer formed on the lower step of the stage of the wafer pad unit.

The lead frame may further include a metal layer formed on the step to connect the upper metal layer of the upper step and the lower metal layer of the lower step.

The lower support unit may extend to a lower surface of a vertical portion of an adjacent lead unit.

Another object of the present invention is to provide a method of manufacturing a lead frame. In the manufacturing method, a support unit groove, a wafer pad unit, and a lead unit are formed by etching one side of a metal substrate. A support unit is formed by filling an insulating material in the support unit slot, and the lead unit is separated from the wafer pad unit and an inner lead, an outer lead, and a pad metal layer are plated by a metal substrate. Formed on the side.

In forming a support unit, the support unit may form a vertical portion of the lead unit.

In separating the lead unit from the wafer pad unit, the outer lead may be formed to be recessed from the peripheral region.

When forming an inner lead, an outer lead, and a die pad metal layer, the inner lead, the outer lead, and the die pad metal layer may be formed by an electroless process.

In forming a support unit, an upper support unit can be formed by filling an insulating material in the support unit groove.

In separating the lead unit from the wafer pad unit, the lower support unit can be formed by filling a gap between the lead unit and the wafer pad unit with an insulating material.

In separating the lead unit from the wafer pad unit, an insulating layer may be formed on a support unit of the lead unit.

In forming an inner lead, an outer lead, and a die pad metal layer, the inner lead may be plated to surround one side of the lead unit toward the wafer pad unit or may be plated to provide a side from the side The predetermined gap is separated.

In forming an inner lead, an outer lead, and a wafer pad metal layer, the lower support unit may extend to a surface of the vertical portion of the lead unit.

Hereinafter, a lead frame and a method of manufacturing the same will be described and illustrated in detail in accordance with an embodiment of the present invention and the drawings. In order to clearly explain the present invention, the unrelated portions will be omitted.

It will be understood that when an element such as a layer, a film, a region or a substrate is "on" and "under" another element, it may be directly in the other element or in another element in which the element is interposed. Furthermore, an element is referred to as "upper" or "lower". In the drawings, the size of the constituent elements may be exaggerated for clarity and convenience of description.

1 and 2 are flow charts showing a method of fabricating a semiconductor wafer package using a lead frame in accordance with a first embodiment of the present invention.

In step S1, a metal substrate 110 for the wiring is prepared. The metal substrate 110 may be made of copper (Cu). Further, the metal substrate 110 may be made of a conductive metal material such as a copper alloy, iron (Fe), or an iron alloy. Here, the thickness of the metal substrate 110 can be as thin as about 10 mils, where 1 mil = 1/1,000 inch. Preferably, the thickness of the metal substrate 110 can be as thin as about 5 mils. Here, photo resistors 120 are formed on the upper and lower surfaces of the metal substrate 110. The photoresist 120 may form, for example, a liquid photo resist (LPR) or a dry film resist (DFR). A photolithography process using a photo mask is performed to expose and develop the photoresist 120 formed on the upper and lower surfaces of the metal substrate 110.

The photoresist 120 may be formed only on the lower surface of the metal substrate 110. However, the photoresist 120 is exemplarily formed on both sides of the metal substrate 110 to protect the elements of the upper surface.

In step S2, a half etching process is performed to form a plurality of support unit grooves 130, a die pad unit 140, and a plurality of lead units 150. As shown, the support unit slot 130, the wafer pad unit 140, and the lead unit 150 have not been separated. For the safety of the manufacturing process, the metal substrate can be etched, for example, by a thickness of 2/3 of the thickness of the metal substrate.

In step S3, an insulator is applied in the support unit slot. Solder resist ink (SR), dry film solder resist (CFSR), and epoxy can be used as the insulator.

In step S4, a plurality of support units 170 are formed and the support unit 170 has a lower surface that protrudes downward by exposing and developing the coated insulator, which is larger than the protruding lower surface of the lead unit 150 and the wafer pad unit 140. Alternatively, the support unit 170 may also be formed to have a lower surface protruding downward, the protrusion being larger than the protruding lower surface of one of the lead unit 150 and the wafer pad unit 140

In step S5, the photoresist 120 is coated on the upper and lower surfaces (or only on the upper surface), and a lithography process (exposure and development) using the photomask is performed to form a line on the upper surface of the metal substrate 110. Therefore, a photoresist pattern corresponding to the desired line pattern is formed.

At step S6, a fine line pattern is formed by performing half etching. At the same time, the lead unit 150 and the wafer pad unit 140 are separated by the half pass etching by the support unit 170. Here, "separated" may be referred to as "being shorted." In the top view, the shape of the lead unit 150 forms a line pattern. In step S7, the upper surface of the lead unit 150, that is, The line pattern is exposed by stripping the photoresist 120.

In step S8, a plurality of insulating layers 180 are formed on a predetermined portion of the upper surface exposed by the lead unit 150 and an upper surface exposed by the supporting unit. The insulating layer 180 enhances the physical strength of the lead frame and prevents molding from delaminating.

In step S9, a plurality of inner leads 190a and outer leads 190b are formed by plating the upper and lower surfaces of the lead unit 150. At the same time, a plurality of wafer pad metal units 195 are formed on the upper surface of the wafer pad unit by plating metal. In step S9, gold (Au) may be plated thereon after nickel (Ni) plating. Further, nickel, lead (Pb), and gold may be continuously plated thereon. One of nickel, lead, and gold may be replaced by silver (Ag). The electroplating process is usually performed as a metal plating process. However, the electroplating process and the electroless plating process can be used together.

In particular, the downward projection of the lower surface of the support unit 170 is larger than the lower surface of the outer lead 190b. As described above, a swell structure is formed by forming the outer leads 190b which are thinner than the adjacent supporting units. Such a raised structure improves the reliability of the soldering process because the raised structure enhances the adhesion during the soldering process.

In more detail, when the semiconductor package is attached to a PCB substrate, a solder ball penetrates into a space formed inside the insulating layer. The solder balls closely contact the outer leads 190b and are held by adjacent support units. Therefore, the solder balls can be more closely adhered.

In step S10, after the inner leads 190a, the outer leads 190b, and the wafer pad metal unit 195 are formed, a semiconductor wafer 20 is mounted, and the semiconductor wafer 20 is connected to the inner leads 190a and the wafer pad metal unit 195 via a wire 10. The semiconductor wafer 20 is electrically connected to a PCB substrate to which the lead frame is attached via wire bonding.

In particular, the semiconductor wafer is electrically connected to a plating unit formed on the lower surface of the lead unit via a plating unit formed on the upper surface of the lead unit, thereby forming a wiring pattern. Therefore, the input/output signals can be transmitted and received via the fine line of the embodiment of the present invention. Due to the fine wiring pattern, the length of the semiconductor wafer and the lead unit can be reduced. Therefore, the manufacturing cost can be reduced by reducing the length of the wire.

Furthermore, the wafer pad unit on which the semiconductor wafer has been mounted may form a recess. Since the semiconductor wafer is inserted in the recess, the size of the semiconductor wafer can be reduced and durability can be enhanced. In step S11, the lead frame and the semiconductor wafer are packaged using an encapsulant such as a mold resin or an epoxy mold compound (EMC).

3 and 4 are flow charts showing a method of fabricating a semiconductor wafer package using a lead frame in accordance with a second embodiment of the present invention.

In step S1, a metal substrate 210 for the wiring is prepared. The metal substrate 210 may be made of, for example, copper (Cu). However, the metal substrate 210 may be made of a conductive metal material such as a copper alloy, iron (Fe), and an iron alloy. The thickness of the metal substrate 210 can be as thin as about 10 mils, where 1 mil = 1/1,000 inch. The thickness of the metal substrate 210 can be as thin as about 5 mils.

The photoresist 220 may be formed on upper and lower surfaces of the metal substrate 210. In this example, the photoresist 220 can be formed as a liquid photoresist or a dry film photoresist. A photolithography process using a photomask is performed to expose and develop the photoresist 220 formed on the upper and lower surfaces of the metal substrate 210.

The photoresist 220 may be formed only on the lower surface of the metal substrate 210. However, the photoresist 220 may be formed on both sides of the metal substrate 210 to protect the elements of the upper surface.

In step S2, a half etching process is performed to form a plurality of support cell trenches 230, a wafer pad unit 240, and a plurality of lead cells 250. As shown, the support unit slot 230, the wafer pad unit 240, and the lead unit 250 have not been separated. For the safety of the manufacturing process, the metal substrate can be etched, for example, by a thickness of 2/3 of the thickness of the metal substrate.

In step S3, an insulator 260 such as resin-coated copper foil (RCC) and photo solder resist (PSR) are coated in the support unit grooves. At step S4, the support unit 270 is formed by pressing and grinding the coated RCC or exposing and developing the RCC.

In step S5, the sides of the metal substrate 210 are etched by reducing the thickness of the metal substrate 210. As described above, the fine line pattern is formed by reducing the thickness of the metal substrate 210.

In step S6, a photoresist pattern 220 is applied on the upper and lower surfaces of the metal substrate 210 (or only on the upper surface) and a lithography process (exposure and development) using the photomask is performed to form a line pattern on the metal substrate. The upper surface of 210 is patterned to form a photoresist 220 corresponding to a desired line pattern.

In step S7, a line pattern is formed by performing etching and stripping of the photoresist 220, and a groove is formed at a predetermined depth of the wafer pad unit. The lead unit 250 is also separated from the wafer pad unit 240 by the support unit 270 via an etching process. Here, "separated" may be referred to as "being shorted." In the top view, the shape of the lead unit forms a line pattern. After being separated from the wafer pad unit 240, each lead unit 250 includes a horizontal portion 250a and a vertical portion 250b. Since the groove shape forms a step in the wafer pad unit 240, the wafer pad unit 240 includes an upper step portion 240a and a lower step portion 240b, and a semiconductor The wafer is mounted in the recess of the wafer pad unit 240, that is, at the lower step portion 240b. Therefore, the size of the semiconductor package is reduced and the durability is improved.

In step S8, an insulating layer 280 is formed by coating the PSR on the horizontal portion 250a of the lead unit 250, the wafer pad unit 240, and the exposed portion of the support unit 270. The insulating layer 280 enhances the physical strength of the lead frame and prevents molding from delaminating.

In step S9, a plating mask is formed by exposing and developing the insulating layer 280 through a lithography process. In step S10, the upper and lower surfaces of the lead unit 250 and the wafer pad unit 240 are plated through an electroless plating process to form inner leads 290a, outer leads 290b, and die pad metal units 295a, 295b. , and 295c. In detail, since the lead unit 250 and the wafer pad unit 240 are separated by etching, it is impossible to perform an electroplating process and only an electroless plating process can be performed. Therefore, since it is an electroless plating process, a rectifier is not required. Because the electroless plating process is advantageous for forming a fine pattern of planting due to its characteristics. At the same time, the planting structure is superior and the planting variation is reduced. During the planting process, gold (Au) is planted after nickel (Ni) planting. At the same time, palladium (Pd) and gold (Au) are continuously planted in the nickel (Ni) planting layer. Further, at least one of nickel (Ni), palladium (Pd), and gold (Au) may be replaced by silver (Ag).

In particular, Figure 5 shows various configurations of inner leads 290a and die pad metal units 295a and 295b.

Referring to FIG. 5, the structure (a) shows that the inner lead 290a surrounds one end side of the horizontal portion 250a of the lead unit 250. The structure (a) simultaneously shows that the wafer pad metal unit 295a formed on the wafer pad unit upper portion 240a surrounds one end portion or both end portions (not shown) of the wafer pad unit 240. One end portion of the horizontal portion 250a of the lead unit 250 is an end facing the wafer pad unit 240. Furthermore, the end of the wafer pad unit 240 is toward one end of the lead unit 250. When the lead unit 250 is formed on both sides of the wafer pad unit 240, the wafer pad metal unit 295a is formed to surround the both end portions of the wafer pad unit 240. Such a structure is formed by exposing one end portion of the horizontal portion 250a in step S9 and one end portion or both end portions of the wafer pad unit 240 and implanting the exposed side edges through electroless plating in step S10.

When the side portions of the lead unit 250 and the wafer pad unit 240 are plated to surround the both, the reliability of the lead frame is improved. Copper is generally used as the material of the metal substrate 210. The copper substrate thermally expands due to environmental variations such as temperature and humidity. The thermal expansion of the metal substrate 210 electrically connects the lead unit 250 to the wafer pad unit 240 or the lead unit 250 to other lead units to cause defects. Therefore, such a defect can be prevented by fixing a side of the copper substrate with a plating layer.

The structure (b) shows that the inner lead 290a and the wafer pad metal unit 295a are formed with a predetermined gap from the side. Such a structure can be formed by controlling the pattern structure of the plating mask in step S9 and performing electroless plating in step S10.

The structure (c) shows that the wafer pad metal unit 295b is formed on the lower step portion 240b of the wafer pad unit 240. Structure (d) shows that wafer pad metal unit 295a is connected to wafer pad metal unit 295b at this stage of wafer pad unit 240 by forming wafer pad metal unit 295d. Such a structure can be formed by controlling the pattern structure of the plating mask in step S9 and performing electroless plating in step S10.

Thermal conduction can be improved by forming wafer pad metal cells 295a, 295b, and 295d as shown on wafer pad unit 240.

Referring again to FIG. 4, the semiconductor wafer 20 is mounted and the semiconductor wafer 220 is connected to the inner lead 290a and the wafer pad metal unit 295a through the wire 10 of step S11. The semiconductor wafer 20 is electrically connected to a PCB substrate to which the lead frame is attached via wire bonding. In particular, the semiconductor wafer 20 is electrically connected to the outer lead 290b via the inner lead 290a, and the outer lead 290b is a plated portion formed on the lower surface of the vertical portion 250b of the lead unit 250, and the inner lead 290a is formed in the lead unit 250. A plated portion of the upper surface of the horizontal portion 250a. Thus, in accordance with embodiments of the present invention, input/output signals can be transmitted and received via a fine line pattern. Similarly, the length of the semiconductor wafer 20 and the lead unit is reduced by the fine line pattern, and the length of the wire can be reduced, so that the manufacturing cost is also reduced.

In step S12, the lead frame and the semiconductor wafer are integrally formed using an encapsulant such as a mold resin or an epoxy mold compound (EMC).

Figure 6 is a cross-sectional view showing a method of manufacturing a lead frame in accordance with a third embodiment of the present invention. Referring to FIG. 6, in step S1, a metal substrate 310 is prepared. The metal substrate 310 may be made of copper (Cu). However, a conductive metal material such as a copper alloy, iron (Fe), or an iron alloy can also be used.

Here, the photoresist 320 is formed on the upper and lower surfaces of the metal substrate 310. In this example, the photoresist 320 can be formed such as liquid photoresist (LPR) or dry film photoresist (DFR). A photoresist 320 using a photomask of the photomask to expose and develop the photoresist 320 on the upper and lower surfaces of the metal substrate 310 is performed.

As described above, the etch mask is formed via exposure and etching to form grooves for the wiring pattern and the wafer pad unit.

In step S2, the metal substrate 310 is etched to become a "routable" and is further stripped to the photoresist of the etch mask. Here, "optional path" means that an inner lead and an outer lead can be connected to electrically connect the semiconductor wafer mounted on the wafer pad unit to the PCB substrate on which the semiconductor package is mounted.

At step S3, a plating resist for forming the inner leads 350 and the outer leads 360 is formed. For example, a solder resist (SR) is formed on the upper surface of the metal substrate, and a portion pre-plated as the inner lead 350 of the upper surface of the metal substrate 310 is exposed through exposure and development. Anti-solder support for the lead frame during etching will be performed subsequently. The solder resist also supports the upper surface of a fully fabricated lead frame as an upper support unit. Therefore, the solder resistance is represented by the above support unit 330a hereinafter.

A dry film resist 340 is formed on the lower surface of the metal substrate 310, and is exposed to a predetermined portion of the lower surface of the metal substrate 310 which is pre-plated to the outer lead 360. If a plating resist is formed on the upper and lower surfaces of the metal substrate 310, portions of the upper and lower surfaces of the die pattern to be plated into the metal layers 370 and 380 will be exposed and The lead 350 is the same as the portion of the outer lead 360.

In step S4, the inner lead 350, the outer lead 360, the wafer pad upper metal layer 370, and the wafer under bump metal layer 380 are formed by selectively etching the upper and lower surfaces of the metal substrate 310. The inner leads 350 formed on the upper portion of the wafer pad unit may be separated from the metal pad 370 formed on the lower wafer pad to reduce the plated area.

In particular, heat conduction can be improved by forming a metal pad layer 370 on the wafer pad and a metal pad layer 380 on the wafer pad to the upper and lower surfaces of the wafer pad unit.

At step S5, the lower dry film photoresist (DFR) is peeled off. In step S6, the lead unit 390 and the wafer pad unit 400 which are separated from each other are formed by etching the lower portion of the metal substrate. The space separating the lead unit 390 and the wafer pad unit 400 is filled by the upper supporting unit 330a. Therefore, although the lower portion of the metal substrate is etched away, the upper support unit 330b maintains the shape of the overall lead frame. The thickness of the package can be reduced by first etching the upper surface of the metal substrate 310 and etching the lower surface of the metal substrate 310 as described.

Also, by etching the lower portion of the metal substrate, the lead unit 390 has a horizontal portion and a vertical portion. The horizontal portion has the shape of the line pattern as described in the upper view of the lead frame.

In particular, if the lower portion of the metal substrate 310 is etched, an etching resist is formed as a dry film photoresist (DFR), and etching is performed using the dry film photoresist (DFR) as an etching mask. In this example, while the outer lead 360 is formed on the lower surface of the vertical portion of the lead unit 390, a predetermined portion of the outer lead 360 may be etched to form an insulating material extending from the support unit 330b.

In step S7, the lower support unit 330b is formed by printing, exposing, and developing an anti-solder (SR) on the lower surface of the metal substrate 310 and hardening it. Unlike the typical lead frame supported only by the lower surface, the upper and lower surfaces of the lead frame according to the present invention are surrounded by the lower support unit 330b and the upper support unit 330a. Therefore, the durability of the lead frame can be improved and the lead frame tilt can be prevented.

When a predetermined portion of the outer lead 360 is etched as described in step S6, the lower support unit 330b may be printed to extend to the lower surface of the vertical portion of the lead unit 390 exposed by etching.

FIG. 7 shows a structure in which the lower supporting unit 330b extends to the lower surface of the vertical portion of the lead unit 390. The structure of Fig. 7 prevents an empty space from being formed between the lower support 210 and the vertical portion of the lead unit. Therefore, the defect ratio is reduced.

In step S8, a semiconductor wafer 20 is mounted, and a plurality of wires 10 are formed to electrically connect the semiconductor wafer 20 and the inner leads 350. Since the lead unit 390 is routable, the input/output distance of the line is shortened. Such a structure allows a flip chip structure and shortens the length of the wire 10, thereby reducing manufacturing costs. After the wires are lapped, a semiconductor wafer package can encapsulate the semiconductor wafer and the lead frame by using an encapsulating material such as a stamper resin or an epoxy die-cast compound.

As described above, according to the present invention, since it is routable, it is an example of connecting an inner lead and an outer lead to electrically connect a semiconductor wafer mounted on the wafer pad to a PCB substrate on which a semiconductor package is mounted. The fine line pattern shortens the wire and allows flip-chip bonding. Further, according to the present invention, the swell structure of the lead frame improves the adhesion in the soldering process. Moreover, the physical strength of the lead frame is increased by improving the supporting force of the insulator.

According to the present invention, the above structure of the lead frame prevents the copper lead unit from being electrically connected to other elements due to environmental variations. Furthermore, the thickness of the semiconductor package is reduced by etching both sides of the lead frame. Further, forming an insulating layer between the lead unit and the molding material prevents warpage and improves durability. Furthermore, since an electroless plating process is used instead of the plating process, a rectifier is not required. Since it is an electroless plating process, a fine plating pattern and a superior structure with only minute plating variations can be formed.

Further, according to the present invention, the support unit of the lead frame surrounds the upper and lower portions of the lead unit. Therefore, the lead frame according to the present invention has superior durability. And since the upper and lower surfaces of the wafer pad unit are integrally plated, heat conduction can be improved.

The present invention has been disclosed in some embodiments, and is not intended to limit the invention. Any one of ordinary skill in the art can be made without departing from the spirit of the invention and the appended claims. Change and retouch.

10. . . wire

20. . . . . . Conductor wafer

30. . . Epoxy resin forming composite

110. . . Metal substrate

120. . . Photoresist

130. . . Support unit slot

140. . . Wafer pad unit

150. . . Lead unit

170. . . Support unit

180. . . Insulation

190a. . . Inner lead

190b. . . Outer lead

195. . . Wafer pad metal unit

210. . . Metal substrate

220. . . Photoresist

230. . . Support unit slot

240a. . . Upper stage

240b. . . Lower order

240. . . Wafer pad unit

250a. . . Horizontal department

250b. . . Vertical part

250. . . Lead unit

260. . . Insulator

270. . . Support unit

280. . . Insulation

290a. . . Inner lead

290b. . . Outer lead

295a, 295b, 295c, 295d. . . Wafer pad metal unit

310. . . Metal substrate

320. . . Photoresist

330a, 330b. . . Support unit

340. . . Dry film photoresist

350. . . Inner lead

360. . . Outer lead

370,380. . . Metal layer

390. . . Lead unit

400. . . Wafer pad unit

S1~S12. . . step

1 and 2 are flow charts showing a method of fabricating a semiconductor wafer package using a lead frame in accordance with a first embodiment of the present invention.

3 and 4 are flow charts showing a method of fabricating a semiconductor wafer package using a lead frame in accordance with a second embodiment of the present invention.

Figure 5 shows various structures of inner leads and wafer pad metal units.

Figure 6 is a cross-sectional view showing a method of manufacturing a lead frame in accordance with a third embodiment of the present invention.

Fig. 7 shows a structure in which the lower supporting unit extends to the lower surface of the vertical portion of the lead unit.

10. . . wire

20. . . Conductor wafer

30. . . Epoxy resin forming composite

170. . . Support unit

180. . . Insulation

190a. . . Inner lead

190b. . . Outer lead

195. . . Wafer pad metal unit

S7~S11. . . step

Claims (19)

A lead frame comprising: a lead unit having a vertical portion and a horizontal portion; a wafer pad unit separated from the lead unit by a support unit formed of an insulating material; an inner lead formed in the lead frame Adjacent to an upper surface of the wafer pad unit and the horizontal portion of the lead unit; an outer lead formed on a lower surface of the vertical portion of the lead unit; and a metal layer formed on the wafer pad unit On the upper surface or on the lower surface. The lead frame of claim 1, wherein a lower surface of the support unit protrudes from a lower surface of the outer lead and a lower surface of the wafer pad unit. The lead frame of claim 1, wherein the inner lead extends to surround the one side of the horizontal portion toward the wafer pad unit or from a side of the horizontal portion by a predetermined gap. The lead frame of claim 1, wherein the support unit comprises: an upper surface of the upper support unit surrounding the horizontal portion of the lead unit; and a lower support unit surrounding the horizontal portion of the lead unit surface. The lead frame of claim 1, wherein the support unit comprises: an upper support unit formed to fill a separation space between the wafer pad unit and the lead unit; and a lower support unit formed to support the The lower portion of the horizontal portion of the lead unit. The lead frame as described in claim 2, further comprising an insulating layer formed At the horizontal portion of the lead unit or an upper surface of the support unit. The lead frame of any one of clauses 1 to 6, further comprising a wafer pad metal layer formed on an upper surface of the wafer pad unit. The lead frame of claim 1, wherein an upper metal layer formed on the upper surface of the wafer pad unit extends to surround a side of the wafer pad unit toward the lead unit or from the wafer The side edges of the pad unit are separated by a predetermined gap. The lead frame of claim 8, wherein the die pad unit comprises a first step, wherein the upper metal layer of the die pad unit is formed at an upper portion of the step, and wherein the lead frame further comprises A metal layer is formed on the lower portion of the step of the wafer pad unit. The lead frame of claim 9, further comprising a metal layer formed on the step to connect the upper metal layer of the upper portion of the step and the lower metal layer of the lower portion of the step. The lead frame of claim 4, wherein the lower support unit extends to a lower surface of the vertical portion of the adjacent lead unit. A method for manufacturing a lead frame, comprising: forming a support unit groove, a wafer pad unit, and a lead unit by etching one side of a metal substrate; forming a support in the support unit groove by filling an insulating material a unit; separating the lead unit from the wafer pad unit and forming an inner lead, an outer lead, and a wafer pad metal layer by plating both sides of the metal substrate; And mounting a wafer directly on the metal pad of the die pad. The manufacturing method according to claim 12, wherein in forming a supporting unit, the supporting unit is formed to protrude from a vertical portion of the lead unit. The manufacturing method according to claim 13, wherein the outer lead formed in the lead unit is separated from the peripheral portion by the wafer pad unit. The manufacturing method of claim 12, wherein in forming an inner lead, an outer lead, and a die pad metal layer, the inner lead, the outer lead, and the die pad metal layer are used An electroless process is formed. The manufacturing method of claim 12, wherein in forming a supporting unit, an upper supporting unit is formed in the supporting unit groove by filling an insulating material, and wherein the lead unit is separated from the wafer pad unit The support unit is formed by filling an insulating material between the lead unit and the wafer pad unit. The manufacturing method according to claim 13, wherein in separating the lead unit from the wafer pad unit, an insulating layer is formed on the supporting unit of the lead unit. The manufacturing method of claim 15, wherein an inner lead, an outer lead, and a die pad metal layer are formed, the inner lead is plated to surround a side of the lead unit toward the wafer The pad unit or plated is separated from the side by a predetermined gap. The manufacturing method according to claim 16, wherein an inner lead, an outer lead, and a die pad metal layer are formed, the lower support unit extending to a surface of the vertical portion of the lead unit.