JP2008084959A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP2008084959A JP2008084959A JP2006260949A JP2006260949A JP2008084959A JP 2008084959 A JP2008084959 A JP 2008084959A JP 2006260949 A JP2006260949 A JP 2006260949A JP 2006260949 A JP2006260949 A JP 2006260949A JP 2008084959 A JP2008084959 A JP 2008084959A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor device
- connection terminal
- metal layer
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 233
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 55
- 229920005989 resin Polymers 0.000 claims abstract description 127
- 239000011347 resin Substances 0.000 claims abstract description 127
- 239000002184 metal Substances 0.000 claims description 114
- 238000007789 sealing Methods 0.000 claims description 49
- 238000000034 method Methods 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 20
- 238000010030 laminating Methods 0.000 claims description 8
- 238000003825 pressing Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 4
- 238000005538 encapsulation Methods 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 description 14
- 229910000679 solder Inorganic materials 0.000 description 10
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】半導体チップ15と、半導体チップ15と電気的に接続される外部接続端子用パッド18と、半導体チップ15を封止する封止樹脂16と、を備え、半導体チップ15と外部接続端子用パッド18との間に、外部接続端子用パッド18が形成される配線パターン12を設け、半導体チップ15を配線パターン12に対してフリップチップ接続させた。
【選択図】図7
Description
図7は、本発明の第1の実施の形態に係る半導体装置の断面図である。
図19は、本発明の第2の実施の形態に係る半導体装置の断面図である。図19において、第1の実施の形態の半導体装置10と同一構成部分には同一符号を付す。
図20は、本発明の第3の実施の形態に係る半導体装置の断面図である。図20において、第1の実施の形態の半導体装置10と同一構成部分には同一符号を付す。
11 絶縁樹脂
12,13 配線パターン
11A,12A,13A 上面
11B,12B,13B,16A 下面
11C,12C,13C 側面
15 半導体チップ
15A 面
16 封止樹脂
17 ソルダーレジスト
17A 開口部
18,51 外部接続用パッド
19 外部接続端子
21 内部接続端子
22 チップ接続領域
23 パッド形成領域
25 電極パッド
27 Ni膜
28 Au膜
35 金属板
36 金属層
41 異方性導電樹脂
55 第1の金属層
56 第2の金属層
A 半導体装置形成領域
B 切断位置
T1,T2 厚さ
Claims (9)
- 半導体チップと、前記半導体チップと電気的に接続される外部接続端子用パッドと、前記半導体チップを封止する封止樹脂と、を備えた半導体装置であって、
前記半導体チップと前記外部接続端子用パッドとの間に、前記外部接続端子用パッドが配置される配線パターンを設け、
前記半導体チップが前記半導体チップと対向する部分の前記配線パターンとフリップチップ接続されていることを特徴とする半導体装置。 - 内部接続端子が設けられた半導体チップと、前記半導体チップと電気的に接続される外部接続端子用パッドと、前記半導体チップを封止する封止樹脂と、前記半導体チップと前記外部接続端子用パッドとの間に設けられ、前記半導体チップと電気的に接続される配線パターンと、を備えた半導体装置の製造方法であって、
支持板となる金属板上に、第1の金属層と、第2の金属層とを順次積層する金属層積層工程と、
前記第2の金属層をエッチングして、前記配線パターンを形成する配線パターン形成工程と、
前記配線パターンを覆うように前記第1の金属層上に異方性導電樹脂を形成する異方性導電樹脂形成工程と、
前記半導体チップを前記異方性導電樹脂に押圧して、前記内部接続端子と前記配線パターンとを圧着させて、前記半導体チップを前記配線パターンにフリップチップ接続する半導体チップ接続工程と、を含むことを特徴とする半導体装置の製造方法。 - 前記第1の金属層は、前記第2の金属層をエッチングするときのエッチングストッパーであることを特徴とする請求項2記載の半導体装置の製造方法。
- 前記封止樹脂を形成後に、前記金属板をエッチングにより除去する金属板除去工程と、
前記第1の金属層をパターニングして、前記外部接続端子用パッドを形成する外部接続端子用パッド形成工程と、をさらに有することを特徴とする請求項2または3記載の半導体装置の製造方法。 - 前記第1の金属層は、前記金属板をエッチングするときのエッチングストッパーであることを特徴とする請求項4記載の半導体装置の製造方法。
- 内部接続端子が設けられた半導体チップと、前記半導体チップと電気的に接続される外部接続端子用パッドと、前記半導体チップを封止する封止樹脂と、前記半導体チップと前記外部接続端子用パッドとの間に設けられ、前記半導体チップと電気的に接続される配線パターンと、を備えた半導体装置の製造方法であって、
支持板となる金属板上に、第1の金属層と、第2の金属層とを順次積層する金属層積層工程と、
前記第2の金属層をエッチングして、前記配線パターンを形成する配線パターン形成工程と、
前記配線パターンを覆うように前記第1の金属層上に絶縁樹脂を形成する絶縁樹脂形成工程と、
前記半導体チップを前記絶縁樹脂に押圧して、前記内部接続端子と前記配線パターンとを圧着させて、前記半導体チップを前記配線パターンにフリップチップ接続する半導体チップ接続工程と、を含むことを特徴とする半導体装置の製造方法。 - 前記第1の金属層は、前記第2の金属層をエッチングするときのエッチングストッパーであることを特徴とする請求項6記載の半導体装置の製造方法。
- 前記封止樹脂を形成後に、前記金属板をエッチングにより除去する金属板除去工程と、
前記第1の金属層をパターニングして、前記外部接続端子用パッドを形成する外部接続端子用パッド形成工程と、をさらに有することを特徴とする請求項6または7記載の半導体装置の製造方法。 - 前記第1の金属層は、前記金属板をエッチングするときのエッチングストッパーであることを特徴とする請求項8記載の半導体装置の製造方法。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006260949A JP2008084959A (ja) | 2006-09-26 | 2006-09-26 | 半導体装置及びその製造方法 |
KR1020070089769A KR20080028279A (ko) | 2006-09-26 | 2007-09-05 | 반도체 장치 및 그 제조 방법 |
US11/856,354 US7884453B2 (en) | 2006-09-26 | 2007-09-17 | Semiconductor device and manufacturing method thereof |
TW096135326A TW200816414A (en) | 2006-09-26 | 2007-09-21 | Semiconductor device and manufacturing method thereof |
CNA2007101541917A CN101154641A (zh) | 2006-09-26 | 2007-09-24 | 半导体器件及其制造方法 |
EP07018974A EP1906446A2 (en) | 2006-09-26 | 2007-09-26 | Semiconductor device and manufacturing method thereof |
US12/581,486 US8211754B2 (en) | 2006-09-26 | 2009-10-19 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006260949A JP2008084959A (ja) | 2006-09-26 | 2006-09-26 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008084959A true JP2008084959A (ja) | 2008-04-10 |
JP2008084959A5 JP2008084959A5 (ja) | 2009-08-20 |
Family
ID=38858918
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006260949A Pending JP2008084959A (ja) | 2006-09-26 | 2006-09-26 | 半導体装置及びその製造方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US7884453B2 (ja) |
EP (1) | EP1906446A2 (ja) |
JP (1) | JP2008084959A (ja) |
KR (1) | KR20080028279A (ja) |
CN (1) | CN101154641A (ja) |
TW (1) | TW200816414A (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101303443A (zh) * | 2007-05-11 | 2008-11-12 | 鸿富锦精密工业(深圳)有限公司 | 相机模组及其组装方法 |
JP2010165940A (ja) | 2009-01-16 | 2010-07-29 | Shinko Electric Ind Co Ltd | 半導体素子の樹脂封止方法 |
US9620455B2 (en) * | 2010-06-24 | 2017-04-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming anisotropic conductive film between semiconductor die and build-up interconnect structure |
JP5878054B2 (ja) * | 2012-03-27 | 2016-03-08 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法及び半導体装置 |
JP6196893B2 (ja) * | 2012-12-18 | 2017-09-13 | 新光電気工業株式会社 | 半導体装置の製造方法 |
KR101374770B1 (ko) * | 2013-11-22 | 2014-03-17 | 실리콘밸리(주) | 금속 박판의 적층을 이용한 반도체 검사 패드 및 제조방법 |
CN104576405B (zh) * | 2014-12-16 | 2017-11-07 | 通富微电子股份有限公司 | 单层基板封装工艺 |
US9583472B2 (en) * | 2015-03-03 | 2017-02-28 | Apple Inc. | Fan out system in package and method for forming the same |
US9659907B2 (en) * | 2015-04-07 | 2017-05-23 | Apple Inc. | Double side mounting memory integration in thin low warpage fanout package |
JP6851239B2 (ja) | 2017-03-29 | 2021-03-31 | エイブリック株式会社 | 樹脂封止型半導体装置およびその製造方法 |
CN111627867A (zh) * | 2019-02-28 | 2020-09-04 | 富泰华工业(深圳)有限公司 | 芯片封装结构及其制作方法 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07297227A (ja) * | 1994-04-26 | 1995-11-10 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH1174310A (ja) * | 1997-08-27 | 1999-03-16 | Matsushita Electron Corp | 半導体装置およびその製造方法 |
JP2001144208A (ja) * | 1999-11-15 | 2001-05-25 | Oki Electric Ind Co Ltd | 半導体装置 |
JP2001267461A (ja) * | 2000-03-23 | 2001-09-28 | Mitsui High Tec Inc | 半導体装置の製造方法 |
JP2002184905A (ja) * | 2000-12-14 | 2002-06-28 | Sharp Corp | 半導体装置およびその製造方法 |
JP2004064082A (ja) * | 2000-10-18 | 2004-02-26 | Nec Corp | 半導体装置搭載用配線基板およびその製造方法、並びに半導体パッケージ |
JP2005328057A (ja) * | 1994-03-18 | 2005-11-24 | Hitachi Chem Co Ltd | 半導体パッケージの製造法及び半導体パッケージ |
JP2007250834A (ja) * | 2006-03-16 | 2007-09-27 | Matsushita Electric Ind Co Ltd | 電子部品装置の製造方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01276750A (ja) | 1988-04-28 | 1989-11-07 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP3313547B2 (ja) | 1995-08-30 | 2002-08-12 | 沖電気工業株式会社 | チップサイズパッケージの製造方法 |
JP3007833B2 (ja) | 1995-12-12 | 2000-02-07 | 富士通株式会社 | 半導体装置及びその製造方法及びリードフレーム及びその製造方法 |
JP2000164638A (ja) | 1998-11-27 | 2000-06-16 | Toshiba Corp | 半導体装置 |
JP2001217354A (ja) | 2000-02-07 | 2001-08-10 | Rohm Co Ltd | 半導体チップの実装構造、および半導体装置 |
JP2001257453A (ja) * | 2000-03-09 | 2001-09-21 | Shinko Electric Ind Co Ltd | 配線基板、半導体装置及びそれらの製造方法 |
JP2001298115A (ja) | 2000-04-13 | 2001-10-26 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US7331502B2 (en) * | 2001-03-19 | 2008-02-19 | Sumitomo Bakelite Company, Ltd. | Method of manufacturing electronic part and electronic part obtained by the method |
US7049170B2 (en) * | 2003-12-17 | 2006-05-23 | Tru-Si Technologies, Inc. | Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities |
JP3914239B2 (ja) | 2005-03-15 | 2007-05-16 | 新光電気工業株式会社 | 配線基板および配線基板の製造方法 |
JP5000877B2 (ja) * | 2005-10-07 | 2012-08-15 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US7728437B2 (en) * | 2005-11-23 | 2010-06-01 | Fairchild Korea Semiconductor, Ltd. | Semiconductor package form within an encapsulation |
US8072059B2 (en) * | 2006-04-19 | 2011-12-06 | Stats Chippac, Ltd. | Semiconductor device and method of forming UBM fixed relative to interconnect structure for alignment of semiconductor die |
US7666709B1 (en) * | 2008-12-10 | 2010-02-23 | Stats Chippac, Ltd. | Semiconductor device and method of placing semiconductor die on a temporary carrier using fiducial patterns |
US7642128B1 (en) * | 2008-12-12 | 2010-01-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP |
-
2006
- 2006-09-26 JP JP2006260949A patent/JP2008084959A/ja active Pending
-
2007
- 2007-09-05 KR KR1020070089769A patent/KR20080028279A/ko not_active Application Discontinuation
- 2007-09-17 US US11/856,354 patent/US7884453B2/en active Active
- 2007-09-21 TW TW096135326A patent/TW200816414A/zh unknown
- 2007-09-24 CN CNA2007101541917A patent/CN101154641A/zh active Pending
- 2007-09-26 EP EP07018974A patent/EP1906446A2/en not_active Withdrawn
-
2009
- 2009-10-19 US US12/581,486 patent/US8211754B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005328057A (ja) * | 1994-03-18 | 2005-11-24 | Hitachi Chem Co Ltd | 半導体パッケージの製造法及び半導体パッケージ |
JPH07297227A (ja) * | 1994-04-26 | 1995-11-10 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH1174310A (ja) * | 1997-08-27 | 1999-03-16 | Matsushita Electron Corp | 半導体装置およびその製造方法 |
JP2001144208A (ja) * | 1999-11-15 | 2001-05-25 | Oki Electric Ind Co Ltd | 半導体装置 |
JP2001267461A (ja) * | 2000-03-23 | 2001-09-28 | Mitsui High Tec Inc | 半導体装置の製造方法 |
JP2004064082A (ja) * | 2000-10-18 | 2004-02-26 | Nec Corp | 半導体装置搭載用配線基板およびその製造方法、並びに半導体パッケージ |
JP2002184905A (ja) * | 2000-12-14 | 2002-06-28 | Sharp Corp | 半導体装置およびその製造方法 |
JP2007250834A (ja) * | 2006-03-16 | 2007-09-27 | Matsushita Electric Ind Co Ltd | 電子部品装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP1906446A2 (en) | 2008-04-02 |
US20100041183A1 (en) | 2010-02-18 |
KR20080028279A (ko) | 2008-03-31 |
CN101154641A (zh) | 2008-04-02 |
US7884453B2 (en) | 2011-02-08 |
TW200816414A (en) | 2008-04-01 |
US20080073798A1 (en) | 2008-03-27 |
US8211754B2 (en) | 2012-07-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2008084959A (ja) | 半導体装置及びその製造方法 | |
US8344492B2 (en) | Semiconductor device and method of manufacturing the same, and electronic apparatus | |
TWI325626B (en) | Method for packaging a semiconductor device | |
US8410614B2 (en) | Semiconductor device having a semiconductor element buried in an insulating layer and method of manufacturing the same | |
JP4400802B2 (ja) | リードフレーム及びその製造方法並びに半導体装置 | |
JP4105202B2 (ja) | 半導体装置の製造方法 | |
JP5406572B2 (ja) | 電子部品内蔵配線基板及びその製造方法 | |
KR101538541B1 (ko) | 반도체 디바이스 | |
JP2009302476A (ja) | 半導体装置および半導体装置の製造方法 | |
TW201631715A (zh) | 佈線基板、製造佈線基板之方法及電子組件裝置 | |
JP4446772B2 (ja) | 回路装置およびその製造方法 | |
US7964493B2 (en) | Method of manufacturing semiconductor device | |
KR101009187B1 (ko) | 인쇄회로기판 및 그 제조방법 | |
TWI420610B (zh) | 半導體裝置及其製造方法 | |
JP5295211B2 (ja) | 半導体モジュールの製造方法 | |
JP4626063B2 (ja) | 半導体装置の製造方法 | |
JP2006073953A (ja) | 半導体装置および半導体装置の製造方法 | |
JP2004207381A (ja) | 配線基板及びその製造方法並びに半導体装置 | |
JP4234518B2 (ja) | 半導体搭載用基板製造方法、半導体パッケージ製造方法、半導体搭載用基板及び半導体パッケージ | |
US20090309208A1 (en) | Semiconductor device and method of manufacturing the same | |
JP5794853B2 (ja) | 半導体装置の製造方法 | |
JP2021036574A (ja) | プリント配線板の製造方法及びプリント配線板 | |
JP2009212114A (ja) | 突起電極の構造、素子搭載用基板およびその製造方法、半導体モジュール、ならびに携帯機器 | |
JP2000277652A (ja) | 半導体パッケージ | |
CN107170715A (zh) | 半导体封装结构及其制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090708 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090708 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100318 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120321 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120516 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20130115 |