CN103890939B - 包括与穿硅过孔组合的细间距单镶嵌后侧金属再分布线的3d互连结构 - Google Patents

包括与穿硅过孔组合的细间距单镶嵌后侧金属再分布线的3d互连结构 Download PDF

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CN103890939B
CN103890939B CN201180074419.6A CN201180074419A CN103890939B CN 103890939 B CN103890939 B CN 103890939B CN 201180074419 A CN201180074419 A CN 201180074419A CN 103890939 B CN103890939 B CN 103890939B
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layer
array
tsv
bond pad
chip
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CN103890939A (zh
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K·J·李
M·T·博尔
A·W·杨
C·M·佩尔托
H·科塔里
S·V·萨蒂拉朱
H-S·马
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Intel Corp
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Intel Corp
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Abstract

描述了3D互连结构及制造方法，其中金属再分布层(RDL)与穿硅过孔(TSV)集成并使用单镶嵌型过程流程。氮化硅或碳化硅钝化层可设置在变薄的器件晶片后表面和RDL之间以在过程流程期间提供密封阻挡层和抛光停止层。

Description

包括与穿硅过孔组合的细间距单镶嵌后侧金属再分布线的3D 互连结构
发明领域
本发明涉及三维(3D)封装，且更具体地涉及穿硅过孔(TSV)到3D封装中的集成。
背景技术
3D封装作为朝着片上系统(SOC)和封装中系统(SIP)的微电子发展的解决方案而出现。特别是，具有TSV的3D倒装芯片结构具有被广泛采用的潜力。TSV3D封装通常包含两个或多个垂直堆叠的芯片，穿过硅衬底的过孔代替边缘布线，以在每个芯片上的电路元件之间创建电连接。
联合电子器件工程委员会(JEDEC)当前正发展WideIO标准，其为逻辑到存储器界面界定芯片到芯片接合焊盘(landing pad)界面。照惯例，TSV的物理位置位于芯片上的接合焊盘位置的正下方，芯片占据很多基板面。这意味着所有其它电路布置在TSV位置周围。
在TSV处理期间，TSV的阵列通过变薄的器件晶片来形成。常规TSV结构使用二氧化硅或聚合物作为在变薄的器件晶片的后侧上的绝缘体材料。这些材料不是密封的，且不在变薄的器件晶片的后侧上提供坚固的钝化层。
附图说明
图1-25是根据本发明的实施例使用单镶嵌处理来制造3D互连结构的方法的横截面侧视图。
图26是根据本发明的实施例的3D互连结构的示意性顶视图。
图27是根据本发明的实施例的实现TSV的3D封装的侧视图。
图28示出根据本发明的实施例的系统。
图29示出根据本发明的实施例的计算设备。
具体实施方式
在各种实施例中，描述了3D互连结构和制造3D互连结构的方法。然而，可在没有这些特定细节中的一个或多个的情况下或结合其它已知的方法和材料来实践某些实施例。在下面的描述中，阐述了很多特定的细节，例如特定的材料和过程等，以便提供对本发明的彻底理解。在其它实例中，没有特别详细地描述公知的封装过程和制造技术，以便没有必要地使本发明不清楚。在整个说明书中对“实施例”或“一个实施例”的提及意味着结合这些实施例描述的特定特征、结构、材料或特性包括在本发明的至少一个实施例中。因此，短语“在实施例中”或“在一个实施例中”在整个说明书中的不同地方的出现不一定都指本发明的同一实施例。此外，特定特征、结构、材料或特性可在一个或多个实施例中以任何合适的方式来组合。
如本文使用的术语“在…之上”、“到”、“在…之间”和“在…上”可以指一层相对于其它层的相对位置。在另一层“之上”或接合“到”另一层的一层可以与另一层直接接触或可具有一个或多个中间层。在层“之间”的一层可直接与这些层接触或可具有一个或多个中间层。相反，在第二层上的第一层与该第二层接触。
在一方面，本发明的实施例描述将穿硅过孔(TSV)与极细间距单镶嵌型后侧金属再分布层(RDL)组合的3D互连结构和过程。这个特定的组合可允许TSV的物理位置与芯片到芯片接合焊盘位置去耦，因而提供较大的电路布局灵活性。以这种方式，多个迹线可在相邻的接合焊盘行或列之间延伸。例如，多个迹线可在分隔开10μm–500μm的间距的相邻的接合焊盘行或列之间延伸。本发明的实施例可实现气封的3D互连结构和比可通过抗蚀剂方法利用板所完成的更细间距RDL架构，并允许铜金属的使用，这对于利用相减蚀刻过程来产生铝RDL线而言是不可能的。
在另一方面，本发明的实施例描述使后侧RDL与变薄的器件晶片的体半导体(例如硅)分离的氮化硅或碳化硅钝化层。氮化硅或碳化硅钝化层可提供密封阻挡层，其保护变薄的器件晶片的后侧在TSV和RDL处理期间免受迹线金属和湿气污染。此外，后侧钝化层材料在单镶嵌过程中是有用的，因为钝化层材料也可在氧化物槽蚀刻期间充当蚀刻停止层，以形成 后侧RDL，其允许氧化物沟槽蚀刻包括大量过蚀刻，而并不使相当大量的钝化层也在单镶嵌处理期间被移除。此外，后侧钝化层材料(例如氮化硅或碳化硅)可具有比TSV阻挡层材料(例如钽(Ta)、钛(Ti)、氮化钽(TaN)或氮化钛(TiN))明显更低的移除速率，使得钝化层在不使相当大量的钝化层被移除的情况下允许大量过抛光被并入到TSV阻挡层化学机械抛光(CMP)步骤中。为阻挡层材料(例如Ta、Ti、TaN、TiN)的移除而设计的常见的市场上可买到的阻挡层CMP研磨液(slurry)也被设计来移除氧化物(例如二氧化硅)。因此，在一些实施例中，当移除TSV之间的TSV阻挡层时，可利用由氮化硅或碳化硅形成的钝化层作为抛光停止层，从而保护TSV结构的完整性。
相应地，本发明的实施例描述了将单镶嵌RDL处理与TSV结构相结合的方式，其中单镶嵌处理可允许极细间距后侧RDL的形成和较大的电路布局灵活性，同时将密封阻挡钝化层融入到处理序列中，该密封阻挡钝化层可在从TSV之间移除TSV阻挡层期间充当CMP停止层，在RDL沟槽蚀刻期间充当蚀刻停止层，并提供器件的增强的可靠性能。应理解，虽然参考硅器件晶片的TSV处理描述了实施例，实施例还可应用于除了硅晶片以外的衬底，例如化合物III-V晶片或II-VI晶片。此外，应认识到，虽然详细描述和示出了“过孔最后”TSV处理(过孔在金属化结构之后被制造)，然而本发明的实施例并不被限制于此，并且本发明的实施例也可与“过孔首先”TSV处理(在形成微电子器件之前制造过孔)和“过孔中间”TSV处理(过孔在形成微电子器件和金属化结构之间被制造)兼容。例如，单镶嵌RDL处理也可整合到过孔首先和过孔中间TSV处理序列中。
参考图25，在实施例中，3D互连结构160包括具有前表面102和后表面104的半导体衬底100、穿过半导体衬底100在前表面102和后表面104之间延伸的过孔(例如，TSV)142、以及形成在后表面104之上的单镶嵌再分布层(RDL)144。钝化层120可设置在后表面104和RDL144之间，以防止湿气和迹线金属污染进入半导体衬底100。合适的钝化层材料可以是碳化硅和氮化硅。在一些实施例中，半导体衬底100可以是包括多个所述3D互连结构的TSV处理的器件晶片。可选地，TSV处理的器件晶片被切割以形成多个半导体衬底，其可以或可以不被进一步处理，以形成 多个芯片，其可随后被集成到3D封装结构中。因此，在实施例中，3D互连结构160是芯片。
参考图26，在实施例中，3D互连结构160包括按一连串行和列的形式来布置在后表面104之上的接合焊盘152的阵列。例如，在阵列中的行和列可具有10μm到500μm的间距。TSV142的阵列可布置在后表面104之下，使得TSV142的阵列并不以与接合焊盘152的阵列相同的图案来布置。在实施例中，TSV142的阵列不在接合焊盘152的阵列的正下面。在这样的实施例中，多个RDL144可在两行接合焊盘152之间延伸，从而将这两行之一连接到TSV的阵列中的对应数量的TSV142。例如，两行接合焊盘可分隔开10μm到500μm的间距。以这种方式，RDL144实现了TSV142的物理位置和电路布局的灵活性。
参考图27，在实施例中，3D封装包括基部衬底170，例如印刷电路板或层压衬底。芯片叠层形成在基部衬底之上，其中芯片叠层包括形成有3D互连结构的芯片160。在实施例中，芯片160是逻辑芯片，且一个或多个存储器芯片180堆叠在逻辑芯片160上，逻辑芯片的接合焊盘的阵列(在导电凸块154的阵列下面)与存储器芯片180的接合焊盘182的对应阵列耦合，然而实施例并不限于此并可包括各种芯片到芯片配置。
在实施例中，描述了形成包括过孔(例如TSV)和单镶嵌RDL的3D互连结构的方法。蚀刻停止层可形成在器件晶片的后表面之上，该器件晶片具有从器件晶片的后表面延伸到前表面的过孔(例如TSV)，且介电层形成在蚀刻停止层之上。沟槽开口随后形成在介电层和蚀刻停止层中，以暴露过孔，且沟槽开口的总体积填充有导电材料，以形成包括接合焊盘的RDL。在实施例中，在使用图案化光致抗蚀剂作为掩模来对介电层进行等离子体蚀刻并停止在蚀刻停止层上的等离子体蚀刻的情况下，可形成沟槽开口。可随后使用基本不蚀刻介电层或下层过孔的绝缘衬层的蚀刻化学性质来对蚀刻停止层进行蚀刻。随后，导电凸块形成在接合焊盘之上，其中所填充的过孔不在接合焊盘的正下方。
在实施例中，过孔形成在过孔最后处理序列中。在这样的实施例中，在形成过孔之前，包含钝化层的碳化硅或氮化硅可形成在器件晶片的后表面之上。过孔开口随后形成在器件晶片的后表面和前表面之间的器件晶片 中。绝缘衬层形成在过孔开口的侧壁上。阻挡层在过孔开口内和钝化层之上形成，且随后过孔的总体积可于是通过例如电镀而被填充有导电材料，例如铜。在过孔开口之间的导电金属覆盖层和阻挡层随后通过例如化学机械抛光从钝化层之上移除。以这种方式，钝化层不仅可起作用来防止湿气和迹线金属污染物进入器件晶片，而且还起抛光停止层的作用，从而允许大量的过抛光并入到TSV阻挡层CMP步骤中，而不使相当大量的钝化层也被移除。
现在参考图1-25，参考附图描述了制造3D互连结构的方法。在图1中示出了可包括前表面102和后表面104的倒置器件晶片100。器件晶片100可具有各种构成。例如，器件晶片可以是体半导体，包括覆盖在体半导体上面的外延层，或包括绝缘体上半导体(SOI)结构，然而也可使用其它结构。在所示的特定实施例中，器件晶片100包括(SOI)结构，其包括覆盖在绝缘体层114上面的半导体层116、以及体衬底118。器件晶片100可另外包括掺杂区或其它掺杂特征，以形成各种微电子器件，例如金属-绝缘体-半导体场效应晶体管(MOSFET)、电容器、电感器、电阻器、二极管、微电机系统(MEMS)、其它合适的有源或无源器件、及其组合。
金属化结构112可形成在器件晶片100的前表面102之上。如所示，金属化结构112包括由导电金属(例如铜、铝等)形成的多个互连层和层间介电材料(例如氧化硅、掺碳氧化物、氮化硅等)。钝化层113可形成在金属化结构112的上部分之上，以提供物理和化学保护。一个或多个导电焊盘108(例如，铜、铝等)可设置在钝化层113中的开口之上。
现在参考图2-3，器件晶片100使用市场上可买到的临时接合粘合剂208和设备来接合到临时载体晶片200。器件晶片100可随后通过研磨、化学机械抛光(CMP)、等离子体蚀刻和/或湿蚀刻后表面104而变薄回去。例如，在实施例中，器件晶片100可变薄回大约50–100μm。
在使器件晶片100变薄之后，钝化层120可形成在后表面104之上以提供密封阻挡，如图4所示。用于钝化层120的合适材料包括碳化硅和氮化硅，因为这些材料可提供密封阻挡，其保护变薄的器件晶片100的后表面104免受迹线金属和湿气污染。碳化硅和氮化硅还可在阻挡层材料从TSV之间的钝化层120之上的随后CMP移除期间拥有比随后沉积的TSV 阻挡层材料(例如Ta或Ti)明显更低的移除速率，如关于图12描述的。可通过合适的方法(例如化学气相沉积(CVD))来沉积钝化层120。钝化层120可以可选地包括多个层，例如氮化硅/氧化硅叠层或碳化硅/氧化硅叠层，其中氧化硅形成在氮化硅或碳化硅之上，并可经由开口蚀刻过程在下游处作为硬掩模被利用。
现在参考图5-7，光致抗蚀剂层被涂覆到变薄的器件晶片上，被曝光和显影。在显影之后，在图案化光致抗蚀剂层122中在过孔(例如TSV)被期望的这些位置处具有开口。随后使用合适的方法(例如等离子体蚀刻穿过钝化层120并穿过在后表面104和前表面102之间的器件晶片100，停止在金属化衬底112内的铜接合焊盘上)来蚀刻过孔开口130(例如TSV开口)。图案化光致抗蚀剂122随后被移除，且可清除掉任何剩余的蚀刻聚合物或残留物。
绝缘衬层136随后被沉积，从而给过孔开口130的底部和侧壁以及在如图8所示的钝化层120之上的过孔开口之间的区域加内衬。用于绝缘衬层136的合适材料包括但不限于二氧化硅、氮化硅、碳化硅和各种聚合物。可通过例如CVD、原子层沉积(ALD)和旋涂方法来沉积这些材料。如图9所示，各向异性等离子体蚀刻过程可随后用于从过孔开口130的底表面以及从在钝化层120之上的过孔开口之间的区域来移除绝缘衬层136，而保持在过孔开口130的侧表面上的绝缘衬层136的相当大的厚度。在这样的实施例中，绝缘衬层136可直接形成在由体硅衬底118所界定的过孔开口130的侧壁上。因此，绝缘衬层136在最终3D互连结构中起作用，以使TSV与周围的硅衬底材料绝缘。
参考图10-12，阻挡层138和种晶层可随后沉积到器件晶片表面上。例如，阻挡层138可包括钽、钛或钴。种晶层可以是例如铜。铜的掩盖层140随后被电镀到器件晶片表面上，利用铜完全填充TSV开口130。钝化层120之上的铜覆盖层和阻挡层随后通过CMP被移除，如图12所示。所产生的结构包括TSV142，其穿过器件晶片100在前表面102和后表面104之间延伸。在这样的配置中，单个金属装填物140占据TSV142的总体积，可以利用阻挡层138和种晶层(例如，用于电镀)以及绝缘衬层136给TSV142加内衬。
在实施例中，在第一CMP操作中使用第一研磨液将铜覆盖层140移除，之后在第二CMP操作中使用不同于第一研磨液的第二研磨液从钝化层120之上移除阻挡层138。用于移除阻挡层138的市场上可买到的CMP研磨液被设计用来蚀刻阻挡层材料，例如Ta、Ti、TaN和TiN，且还一般被设计成蚀刻氧化物。根据本发明的实施例，钝化层120可在阻挡层138的移除期间起抛光停止的作用，这允许阻挡层138的CMP操作在不使相当大量的钝化层120被移除的情况下包括大量过抛光。
现在参考图13-16，蚀刻停止层121形成在钝化层120和过孔142之上。用于蚀刻停止层121的合适材料包括氮化硅或碳化硅。介电层123随后形成在蚀刻停止层121之上。例如，介电层123可包括二氧化硅。光致抗蚀剂层随后被涂覆在介电层123之上，被曝光和显影。在显影之后，在图案化光致抗蚀剂层125中在具有接合焊盘的细间距RDL被期望的这些位置处具有开口。随后使用图案化光致抗蚀剂层125作为掩模穿过介电层123的整个厚度停止在蚀刻停止层121上、使用合适的技术(例如等离子蚀刻)，来蚀刻沟槽开口134。在实施例中，一旦介电层123沿着蚀刻停止层121而下被清理，等离子体蚀刻化学性质就发生改变，以选择性地对蚀刻停止层121进行蚀刻，而保持沟槽开口134的介电层123侧壁和下层绝缘衬层136基本未受影响。根据本发明的实施例，蚀刻停止层121可保护绝缘衬层136在沟槽开口134的形成期间不被损坏以保护TSV结构的完整性。在蚀刻过程之后，图案化光致抗蚀剂层125被移除，且可清除掉任何剩余的蚀刻聚合物或残留物。
现在参考图17-19，阻挡层139和种晶层可随后沉积到器件晶片表面上。例如，阻挡层139可包括例如Ta、Ti、TaN、TiN。种晶层可以例如是铜。铜141的掩盖层随后被电镀到器件晶片表面上，利用铜填充沟槽开口134的总体积。在介电层123之上的铜覆盖层和阻挡层随后通过CMP被移除，如图19所示。所产生的RDL144可包括接合焊盘，其中过孔142不在接合焊盘正下方，并可利用阻挡层139和种晶层(例如用于电镀)来加内衬。在实施例中，在第一CMP操作中使用第一研磨液移除铜覆盖层141，之后在第二CMP操作中使用不同于第一研磨液的第二研磨液移除介电层123之上的阻挡层139。
现在参考图20-23，在RDL144之上形成接合焊盘开口。钝化层146沉积在平面化表面之上。合适的材料包括但不限于可提供密封阻挡的氮化硅，该密封阻挡防止迹线金属和湿气污染、以及保护RDL144免受氧化。光致抗蚀剂材料随后被涂覆在钝化层146之上，被曝光并显影以形成图案化光致抗蚀剂层148。在显影之后，在光致抗蚀剂层148中，在RDL144将在芯片到芯片连接所期望的接合焊盘处终止的这些位置处具有开口150。随后使用合适的技术例如(等离子体蚀刻)使用图案化光致抗蚀剂层148作为掩模，穿过钝化层146并停止在下层RDL144的接合焊盘152上，来蚀刻出开口。光致抗蚀剂层148随后被移除，且可清除掉任何剩余的蚀刻聚合物或残留物。
现在参考图24，导电凸块154形成在每个暴露的RDL144的接合焊盘152之上。任何合适的技术可被实现来形成导电凸块154，例如但不限于焊接凸块、使用图案化过程的电镀、和无电式电镀。在图24所示的特定实施例中，使用焊接相容的表面修饰来涂覆所暴露的RDL144的接合焊盘152。导电凸块154的示例性表面修饰包括无电CoP/浸渍Au、无电CoWP/浸渍Au、无电NiP/浸渍Au、无电NiP/无电Pd/浸渍Au、无电Sn、无电NiP/无电Sn、无电CoP/无电Sn、无电CoWP/无电Sn、无电Cu/无电CoP/浸渍Au、无电Cu/无电CoWP/浸渍Au、无电Cu/无电NiP/浸渍Au、无电Cu/无电NiP/无电Pd/浸渍Au、无电Cu/无电Sn、无电Cu/无电NiP/无电Sn、无电Cu/无电CoP/浸渍Au、无电Cu/无电CoWP/无电Sn。其它表面修饰也可以是合适的，这取决于芯片到芯片焊接材料和/或所使用的芯片到芯片附接方法。在另一实施例中，导电凸块154可以是C4或由材料(例如PbSn、Sn、SnAg、Cu、In、SnAgCu、SnCu、Au等)形成的倒装芯片凸块。
载体晶片200和粘合剂208可随后利用市场上可买到的晶片剥离设备和如图25所示的处理从器件晶片100移除。当移除载体晶片200和粘合剂208时，在图25中所示的所产生的多个3D互连结构160可被切割，并随后可以或可以不被进一步处理以形成芯片，其可随后被集成到3D封装结构中。
参考图26，示出用于根据本发明的实施例将第二芯片连接到3D互连结构的示例性标准化芯片到芯片接合焊盘界面。如在放大视图中更详细地 示出的，接合焊盘152的阵列按一连串行和列的形式来布置在后表面104(见图25)之上。TSV142的阵列布置在后表面104之下，使得TSV的阵列未在接合焊盘152的阵列的正下方。多个RDL144在两行接合焊盘152之间延伸，并将这两行接合焊盘152之一连接到在TSV的阵列中的对应数量的TSV142。以这种方式，将后侧接合焊盘152连接到前侧电路(金属化结构112)的TSV可位于芯片上的任何地方。虽然已描述了其中TSV的阵列不在接合焊盘和/或导电凸块的阵列的正下方的本发明的实施例，然而应认识到，一些TSV可以在接合焊盘和/或导电凸块的阵列的正下方。本发明的实施例通过单镶嵌处理的集成来提供TSV的位置的灵活性。结果，并不要求TSV的阵列的位置在TSV所连接到的接合焊盘和/或导电凸块的对应阵列的正下方。
为了进一步说明本发明的实施例能够实现电路设计灵活性的能力，在一个示例中，图26所示的接合焊盘152的阵列可具有50μm的垂直间距和40μm的水平间距，且接合焊盘152具有20μm的直径。这在特定的示例中留下30μm，以在两行接合焊盘152之间延伸六个RDL144。假设相邻RDL144和在RDL144之间的六个RDL线宽和七个空间是相同的，每个RDL144的线宽可具有2.3μm。根据本发明的实施例的单镶嵌型处理可能特别适合于实现这样的示例性细间距RDL架构，虽然实施例不被这样限制且也可用于RDL架构的任何间距。
图27是根据本发明的实施例实现3D互连结构的某些方面的3D封装的例证性示例。如所示，多个芯片堆叠在衬底170(例如印刷电路板或层压衬底)之上。例如，芯片160可包括如本文描述的3D互连结构。在一个实施例中，芯片160是包括如本文描述的3D互连结构的逻辑芯片，而芯片180是存储器芯片。例如，3D封装可包括堆叠在逻辑芯片160之上的一个或多个存储器芯片180。3D封装可以可选地包括堆叠在至少一个存储器芯片180之上的逻辑芯片160。如所示，导电凸块154且因此在导电凸块154下面的接合焊盘152(未示出)的阵列与存储器芯片180的接合焊盘182的对应阵列对齐，且导电焊盘108与衬底170连接。应认识到，虽然图27示出逻辑芯片160和存储器芯片180的示例性堆叠，然而本发明的实施例不限于此，并且芯片可以是任何合适的芯片，例如存储器(例如DRAM、 eFLASH、eRAM等)、插入层、RF、MEMS等。
图28示出根据本发明实施例的计算机系统。在一些实施例中，系统300包括处理器310、存储器设备320、存储器控制器330、图形控制器340、输入和输出(I/O)控制器350、显示器352、键盘354、指示设备356和外围设备358，所有设备都可通过总线360通信地耦合到彼此。处理器310可以是通用处理器或专用集成电路(ASIC)。I/O控制器350可包括用于有线或无线通信的通信模块。存储器设备320可以是动态随机存取存储器(DRAM)设备、静态随机存取存储器(SRAM)设备、闪存设备、或这些存储器设备的组合。因此，在一些实施例中，系统300中的存储器设备320不必包括DRAM设备。
在系统300中示出的一个或多个部件可例如被包括在一个或多个集成电路封装(例如图27的芯片160或3D封装)中和/或可包括一个或多个集成电路封装(例如图27的芯片160或3D封装)。例如，处理器310或存储器设备320或I/O控制器350的至少一部分或这些部件的组合可被包括在集成电路封装中，该集成电路封装包括在各种实施例中描述的结构的至少一个实施例。
这些元件执行它们在本领域中公知的常规功能。特别是，存储器设备320在一些情况中可用于提供对根据本发明的实施例的用于形成封装结构的方法的可执行指令的长期存储，而在其它实施例中可用于在短期基础上在通过处理器310的执行期间存储根据本发明的实施例的用于形成封装结构的方法的可执行指令。此外，指令可被存储，或例如以另外方式与系统通信地耦合的机器可访问介质(例如光盘只读存储器(CD-ROM)、数字通用盘(DVD)和软盘)、载波和/或其它传播信号相关联。在一个实施例中，存储器设备320可给处理器310提供用于执行的可执行指令。
系统300可包括计算机(例如桌上型计算机、膝上型计算机、手持设备、服务器、Web应用、路由器等)、无线通信设备(例如蜂窝电话、无绳电话、寻呼机、个人数字助理等)、与计算机相关的外围设备(例如打印机、扫描仪、监视器等)、娱乐设备(例如电视机、收音机、立体声系统、磁带和光盘播放器、视频盒式磁带记录器、摄录像机、数字相机、MP3(运动图片专家组、音频层3)播放器、视频游戏、手表等)等。
图29示出根据本发明的一个实施例的计算设备400。计算设备400容纳板402。板402可包括多个部件，包括但不限于处理器404和至少一个通信芯片406。处理器404物理地和电气地耦合到板402。在一些实现方式中，至少一个通信芯片406也物理和电气地耦合到板402。在另外的实现方式中，通信芯片406是处理器404的部分。
根据其应用，计算设备400可包括可以或可以不物理和电气地耦合到板402的其它部件。这些其它部件包括但不限于易失性存储器(例如DRAM)、非易失性存储器(例如ROM)、闪存、图形处理器、数字信号处理器、加密处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码译码器、视频编码译码器、功率放大器、全球定位系统(GPS)设备、罗盘、加速度计、陀螺仪、扬声器、相机和大容量存储设备(例如硬盘驱动器、光盘(CD)、数字通用盘(DVD)等)。
通信芯片406实现用于数据至和从计算设备1000的传输的无线通信。术语“无线”及其派生词可用于描述可通过使用经由非固体介质的经调制电磁辐射来通信数据的电路、设备、系统、方法、技术、通信信道等。该术语并不暗示相关的设备不包含任何电线，虽然在一些实施例中它们可以不包含电线。通信芯片406可实现多种无线标准或协议中的任一个，包括但不限于Wi-Fi(IEEE802.11系列)、WiMAX(IEEE802.16系列)、IEEE802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其派生物以及被指定为3G、4G、5G和更高代的任何其它无线协议。计算设备400可包括多个通信芯片406。例如，第一通信芯片406可专用于较短范围的无线通信，例如Wi-Fi和蓝牙，而第二通信芯片406可专用于较长范围的无线通信，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
计算设备400的处理器404包括封装在处理器404内的集成电路管芯。在本发明的一些实施例中，处理器的集成电路管芯可被包括在一个或多个集成电路封装(例如图27的芯片160或3D封装)中和/或可包括一个或多个集成电路封装(例如图27的芯片160或3D封装)。术语“处理器”可以指处理来自寄存器和/或存储器的电子数据以将该电子数据转换成可存储在寄存器和/或存储器中的其它电子数据的任何设备或设备的部分。
通信芯片406还包括封装在通信芯片406内的集成电路管芯。根据本发明的另一实现，通信芯片的集成电路管芯可被包括在一个或多个集成电路封装(例如图27的芯片160或3D封装)中和/或可包括一个或多个集成电路封装(例如图27的芯片160或3D封装)。
在另外的实现方式中，容纳在计算设备400内的另一部件可包含集成电路封装，例如图27的芯片160或3D封装。此外，处理器404、通信芯片406、以及容纳在计算设备400内的其它部件可堆叠在例如图27的3D封装中。
在各种实现方式中，计算设备400可以是膝上型计算机、上网本计算机、笔记本计算机、智能电话、平板计算机、个人数字助理(PDA)、超移动PC、移动电话、桌上型计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字相机、便携式音乐播放器、或数字视频记录器。在另外的实现方式中，计算设备400可以是处理数据的任何其它电子设备。
虽然以结构特征和/或方法行动特有的语言描述了本发明，然而应理解，在所附权利要求中限定的本发明不一定限于所描述的特定特征或行动。所公开的特定特征和行动相反应被理解为对说明本发明有用的所主张的发明的特别适度的实现方式。

Claims (20)

1.一种3D互连结构，包括：
半导体衬底，其具有前表面和后表面；
金属化结构，其位于所述前表面之上，所述金属化结构包括多个互连层和层间介电层；
过孔，其穿过所述半导体衬底在所述前表面和所述后表面之间延伸；以及
单镶嵌再分布层RDL，其形成在所述后表面之上。
2.如权利要求1所述的3D互连结构，还包括设置在所述后表面和所述RDL之间的钝化层。
3.如权利要求2所述的3D互连结构，其中所述钝化层包括碳化硅或氮化硅。
4.如权利要求3所述的3D互连结构，其中所述过孔还包括：
绝缘衬层，其形成在所述半导体衬底中的过孔开口的侧表面上；
连续阻挡层，其形成在所述过孔开口的底表面上，并形成在所述绝缘衬层上，所述绝缘衬层形成在所述过孔开口的侧表面上；以及
导电金属，其填充所述过孔开口的总体积。
5.如权利要求4所述的3D互连结构，其中所述单镶嵌RDL还包括：
阻挡层，其形成在介电层中的沟槽开口的侧表面上，其中所述沟槽开口暴露所述钝化层和所述过孔；以及
导电金属，其填充所述沟槽开口的总体积。
6.如权利要求3所述的3D互连结构，还包括：
接合焊盘的阵列，其按一连串的行和列的形式布置在所述后表面之上；
穿硅过孔TSV的阵列，其布置在所述后表面之下，使得所述TSV的阵列不在所述接合焊盘的阵列的正下方；以及
多个RDL，其在两行所述接合焊盘之间延伸，从而将所述两行中的一行连接到所述TSV的阵列中的对应数量的TSV。
7.如权利要求6所述的3D互连结构，其中所述两行接合焊盘分隔开10μm到500μm的间距。
8.一种3D封装，包括：
基部衬底；以及
芯片叠层，其形成在所述基部衬底之上；
其中所述芯片叠层包括芯片，所述芯片包括：
半导体衬底，其具有前表面和后表面；
金属化结构，其位于所述前表面之上，所述金属化结构包括多个互连层和层间介电层；
过孔，其在所述半导体衬底的所述前表面和所述后表面之间延伸；以及
单镶嵌再分布层RDL，其形成在所述后表面之上。
9.如权利要求8所述的3D封装，其中所述芯片是逻辑芯片。
10.如权利要求9所述的3D封装，还包括系统，所述系统包括通信地耦合到所述3D封装的总线。
11.如权利要求9所述的3D封装，其中所述逻辑芯片还包括：
接合焊盘的阵列，其按一连串的行和列的形式来布置在所述后表面之上；
穿硅过孔TSV的阵列，其布置在所述后表面之下，使得所述TSV的阵列不在所述接合焊盘的阵列的正下方；以及
多个RDL，其在两行所述接合焊盘之间延伸，从而将所述两行中的一行连接到所述TSV的阵列中的对应数量的TSV。
12.如权利要求11所述的3D封装，其中所述接合焊盘的阵列与存储器芯片的接合焊盘的对应阵列耦合。
13.一种形成3D互连结构的方法，包括：
在器件晶片的后表面之上形成蚀刻停止层，所述器件晶片具有从所述器件晶片的所述后表面延伸到前表面的过孔；
在所述蚀刻停止层之上形成介电层；
在所述介电层和蚀刻停止层中形成沟槽开口以暴露所述过孔；
使用导电金属填充所述沟槽开口的总体积，以形成包括接合焊盘的再分布层RDL，其中所述过孔不在所述接合焊盘的正下方；以及
在所述接合焊盘之上形成导电凸块。
14.如权利要求13所述的方法，在形成所述蚀刻停止层之前：
在所述器件晶片的所述后表面之上形成钝化层，其中所述钝化层包括碳化硅或氮化硅；
在所述器件晶片中在所述器件晶片的所述后表面和前表面之间形成过孔开口；
在所述过孔开口内并在所述钝化层之上形成阻挡层；
采用导电金属填充所述过孔开口的总体积；
从所述钝化层之上移除所述阻挡层和所述导电金属的覆盖层，以形成所述过孔。
15.如权利要求14所述的方法，还包括将绝缘衬层沉积在所述过孔开口的侧表面和底表面上。
16.如权利要求15所述的方法，还包括对来自所述过孔开口的所述底表面的所述绝缘衬层进行各向异性地蚀刻，而保持所述过孔开口的所述侧表面上的相当大的厚度。
17.如权利要求16所述的方法，其中使用导电金属填充所述过孔开口的总体积包括电镀铜。
18.如权利要求13所述的方法，其中形成所述沟槽开口包括使用图案化光致抗蚀剂层作为掩模，以及使用对所述蚀刻停止层而言是选择性的等离子体蚀刻化学性质来蚀刻所述蚀刻停止层，而基本上不蚀刻所述介电层和绝缘衬层。
19.如权利要求13所述的方法，还包括：
在所述后表面之上按一连串的行和列的形式来形成接合焊盘的阵列；
在所述后表面之下形成穿硅过孔TSV的阵列，使得所述TSV的阵列不在所述接合焊盘的阵列的正下方；以及
形成在两行所述接合焊盘之间延伸的多个RDL，从而将所述两行中的一行连接到所述TSV的阵列中的对应数量的TSV。
20.如权利要求19所述的方法，其中所述两行接合焊盘分隔开10μm到500μm的间距。
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KR20140024674A (ko) * 2012-08-20 2014-03-03 삼성전자주식회사 관통 비아 구조체 및 재배선 구조체를 갖는 반도체 소자
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US8907488B2 (en) * 2012-12-28 2014-12-09 Broadcom Corporation Microbump and sacrificial pad pattern
US9716066B2 (en) 2013-06-29 2017-07-25 Intel Corporation Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias
KR102149150B1 (ko) * 2013-10-21 2020-08-28 삼성전자주식회사 전자 장치
US9478509B2 (en) * 2014-03-06 2016-10-25 GlobalFoundries, Inc. Mechanically anchored backside C4 pad
CN103956334B (zh) * 2014-05-07 2016-06-01 华进半导体封装先导技术研发中心有限公司 集成电路中rdl和tsv金属层一次成型方法
US11239138B2 (en) * 2014-06-27 2022-02-01 Taiwan Semiconductor Manufacturing Company Methods of packaging semiconductor devices and packaged semiconductor devices
KR102471533B1 (ko) 2014-08-07 2022-11-28 인텔 코포레이션 패시브 평면형 디바이스를 갖는 rf 회로 장치 및 패시브 평면형 디바이스를 갖는 rf 회로 시스템
TWI566354B (zh) * 2014-08-13 2017-01-11 矽品精密工業股份有限公司 中介板及其製法
CN104332393B (zh) * 2014-10-17 2017-01-25 中国航天科技集团公司第九研究院第七七一研究所 一种制备tsv立体集成rdl电镀掩膜的厚胶工艺
KR102379370B1 (ko) * 2014-12-23 2022-03-28 인텔 코포레이션 비아 차단 층
US9583462B2 (en) 2015-01-22 2017-02-28 Qualcomm Incorporated Damascene re-distribution layer (RDL) in fan out split die application
US9941190B2 (en) 2015-04-03 2018-04-10 Micron Technology, Inc. Semiconductor device having through-silicon-via and methods of forming the same
KR102444823B1 (ko) 2015-08-13 2022-09-20 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그 제조방법
US10043676B2 (en) * 2015-10-15 2018-08-07 Vishay General Semiconductor Llc Local semiconductor wafer thinning
US9806025B2 (en) * 2015-12-29 2017-10-31 Globalfoundries Inc. SOI wafers with buried dielectric layers to prevent Cu diffusion
JP2018157110A (ja) * 2017-03-17 2018-10-04 東芝メモリ株式会社 半導体装置およびその製造方法
US10020223B1 (en) 2017-04-12 2018-07-10 International Business Machines Corporation Reduced tip-to-tip and via pitch at line end
KR102406573B1 (ko) 2017-04-28 2022-06-09 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR102422460B1 (ko) 2017-08-22 2022-07-19 삼성전자주식회사 반도체 소자
US10852344B2 (en) * 2017-12-12 2020-12-01 Micron Technology, Inc. Inductive testing probe apparatus for testing semiconductor die and related systems and methods
KR102542573B1 (ko) 2018-09-13 2023-06-13 삼성전자주식회사 재배선 기판, 이의 제조 방법, 및 이를 포함하는 반도체 패키지
US11171166B2 (en) * 2018-11-20 2021-11-09 Ningbo Semiconductor International Corporation Camera assembly and packaging method thereof, lens module, electronic device
JP2020141001A (ja) * 2019-02-27 2020-09-03 キオクシア株式会社 半導体装置および半導体装置の製造方法
US10978338B1 (en) * 2019-11-13 2021-04-13 Nanya Technology Corporation Semiconductor device and manufacture method thereof
CN111640722B (zh) * 2020-06-11 2022-07-05 厦门通富微电子有限公司 一种芯片封装方法和芯片封装器件
CN111554582B (zh) * 2020-06-11 2022-07-15 厦门通富微电子有限公司 一种芯片封装方法和芯片封装器件
US11862535B2 (en) * 2020-09-16 2024-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate-via with reentrant profile
KR20220129924A (ko) 2021-03-17 2022-09-26 삼성전자주식회사 인터포저, 이의 제조 방법, 및 이를 가지는 반도체 패키지

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6551856B1 (en) * 2000-08-11 2003-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming copper pad redistribution and device formed
CN101794717A (zh) * 2009-01-13 2010-08-04 台湾积体电路制造股份有限公司 堆叠集成芯片及其制造方法
CN102024781A (zh) * 2009-09-22 2011-04-20 台湾积体电路制造股份有限公司 集成电路结构

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6882030B2 (en) * 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
US7129567B2 (en) 2004-08-31 2006-10-31 Micron Technology, Inc. Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements
WO2008030910A1 (en) 2006-09-08 2008-03-13 Lord Corporation Flexible microelectronics adhesive
US8487444B2 (en) 2009-03-06 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional system-in-package architecture
US8872345B2 (en) * 2011-07-07 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Forming grounded through-silicon vias in a semiconductor substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6551856B1 (en) * 2000-08-11 2003-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming copper pad redistribution and device formed
CN101794717A (zh) * 2009-01-13 2010-08-04 台湾积体电路制造股份有限公司 堆叠集成芯片及其制造方法
CN102024781A (zh) * 2009-09-22 2011-04-20 台湾积体电路制造股份有限公司 集成电路结构

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