TWI556335B - 包含組合有貫矽導孔的細間距單嵌背側金屬再分佈線的３ｄ內連線結構 - Google Patents

包含組合有貫矽導孔的細間距單嵌背側金屬再分佈線的３ｄ內連線結構 Download PDF

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TWI556335B
TWI556335B TW101133495A TW101133495A TWI556335B TW I556335 B TWI556335 B TW I556335B TW 101133495 A TW101133495 A TW 101133495A TW 101133495 A TW101133495 A TW 101133495A TW I556335 B TWI556335 B TW I556335B
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layer
array
wafer
back surface
tsv
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TW101133495A
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TW201318085A (zh
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凱文 李
馬克 鮑爾
安卓 楊
克里斯多夫 佩爾圖
希坦 科瑟里
榭蘇 沙特拉茱
馬恆盛
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英特爾股份有限公司
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Description

包含組合有貫矽導孔的細間距單嵌背側金屬再分佈線的3D內連線結構
本發明相關於三維(3D)封裝，且更明確地說，相關於將貫矽導孔(TSV)積集入3D封裝中。
3D封裝正新興為朝向系統單晶片(SOC)及單封裝系統(SIP)之微電子發展的解決方案。特別係具有TSV之3D覆晶結構具有被廣泛採用的潛力。TSV 3D封裝通常包含二或多個垂直堆疊的晶片，具有取代邊緣佈線之貫穿矽基材的導孔，以在各晶片上的電路元件之間產生電性連接。
電子裝置工程聯合委員會(JEDEC)目前正在發展界定用於邏輯對記憶體介面之晶片對晶片著陸銲墊介面的WideIO標準。習知地，TSV的實體位置位於晶片上之著陸銲墊位置的正下方，其消耗許多實際空間。此意謂著所有其他電路係圍繞著TSV位置佈置。
在TSV處理期間，TSV陣列係貫穿薄化裝置晶圓而形成。習知TSV結構將二氧化矽或聚合物任一者使用為在薄化裝置晶圓之背側上的絕緣器材料。此等材料係非密封的，且不在薄化裝置晶圓的背側上提供強健的鈍化層。
在各種實施例中描述3D內連線結構及製造3D內連線 結構的方法。然而，可能實踐特定實施例而無需一或多個此等特定細節，或與其他已知方法及材料組合。在以下描述中，陳述許多特定細節，諸如，特定材料及處理等，以提供對本發明的徹底理解。在其他實例中，未特別詳細地描述已為人熟知的封裝處理及製造技術，以免非必要地混淆本發明。於此說明書各處提及之「實施例」或「一實施例」意指相關於該實施例描述的特定特性、結構、材料、或特徵係包括在本發明的至少一實施例中。因此，出現在此說明書各處的片語「在實施例中」或「在一實施例中」不必然指本發明的相同實施例。此外，該等特定特性、結構、材料、或特徵可能在一或多個實施例中以任何適當方式組合。
使用在本文中的術語「上方」、「至」、「之間」、及「之上」可能指一層相關於其他層的相對位置。在另一層「上方」或接合「至」另一層的一層可能與該另一層直接接觸或可能具有一或多個中間層。多層「之間」的一層可能與該等層直接接觸或可能具有一或多個中間層。相反地，在第二層「上」的第一層與該第二層接觸。
在一實施樣態中，本發明的實施例描述將貫矽導孔(TSV)與間距非常精細之單嵌型背側金屬再分佈層(RDL)組合的3D內連線結構及處理。此特定組合可容許將TSV的實體位置從晶片對晶片著陸銲墊位置斷開，從而提供更大的電路佈置彈性。以此方式，多個軌跡線可繞行在相鄰著陸銲墊的行列之間。例如，多個軌跡線可能繞行 在以10μm-500μm的間距分隔之相鄰著陸銲墊的行列之間。本發明的實施例可容許密封封閉的3D內連線結構及較使用鍍通阻抗法所能完成間距更精細的RDL架構，並容許使用不可能以減蝕刻處理的銅金屬來製造鋁RDL線。
在其他實施樣態中，本發明的實施例描述將背側RDL與薄化裝置晶圓之塊狀半導體(例如，矽)分開的氮化矽或碳化矽鈍化層。氮化矽或碳化矽鈍化層可提供保護薄化裝置晶圓背側以在TSV及RDL處理期間免於微量金屬及濕氣污染的密封阻障層。此外，背側鈍化層材料在單嵌處理中係有用的，在該處理中，該鈍化層材料在氧化物溝槽蝕刻期間也可使用為蝕刻停止層，以形成背側RDL，其容許該氧化物溝槽蝕刻合併大量過蝕刻而不會造成在單嵌處理期間移除大量的鈍化層。再者，背側鈍化層材料，諸如，氮化矽或碳化矽，可能具有顯著低於TSV阻障層材料(諸如，鉭(Ta)、鈦(Ti)、氮化鉭(TaN)、或氮化鈦(TiN))的移除率，使得鈍化層容許將大量過研磨併入TSV阻障層化學機械研磨(CMP)步驟中，並也不會造成大量的鈍化層被移除。也可將加工以移除阻障材料(諸如，Ta、Ti、TaN、TiN)的常見市售阻障層CMP漿加工以成移除氧化物，諸如，二氧化矽。因此，在部分實施例中，當移除TSV之間的TSV阻障層時，可將氮化矽或碳化矽形成的鈍化層使用為研磨停止層從而保護TSV結構的完整性。
因此，本發明的實施例描述將單嵌RDL處理與TSV結 構積集的方法，其中該單嵌處理可容許形成間距非常精細的背側RDL及更大的電路佈置彈性，而將在將TSV阻障層從TSV之間移除的期間使用為CMP停止層、在RDL溝槽蝕刻期間使用為蝕刻停止層、並提供該裝置的強化可靠性效能的密封阻障鈍化層積集入該處理序列中。待理解雖然參考矽裝置晶圓的TSV處理描述實施例，該等實施例也可應用至矽晶圓以外的基材，諸如，化合物III-V族晶圓或II-VI族晶圓。此外，待理解雖然詳細地描述及說明「後導孔」TSV處理(導孔在金屬化結構之後製造)，本發明的實施例並未受如此限制，且本發明的實施例也可能與「先導孔」TSV處理(導孔在微電子裝置形成之前製造)及「中途導孔」TSV處理(導孔在形成微電子裝置及金屬化結構之間製造)相容。例如，也可能將單嵌RDL處理積集入先導孔及中途導孔TSV處理序列中。
參考圖25，在實施例中，3D內連線結構160包括：具有前表面102及背表面104的半導體基材100、貫穿半導體基材100在前102及背104表面之間延伸的導孔(例如，TSV)142、及形成在背表面104上方的單嵌再分佈層(RDL)144。可將鈍化層120設置在背表面104及RDL 144之間，以防止濕氣及微量金屬污染進入半導體基材100。合適的鈍化層材料可能係碳化矽及氮化矽。在部分實施例中，半導體基材100可能係包括複數個上述3D內連線結構之經TSV處理的裝置晶圓。或者，將經TSV處理的裝置晶圓切片，以形成可能或可能不進一步處理以形成複數個晶 片的複數個半導體基材，然後可能將彼等積集為3D封裝結構。因此，在實施例中，該3D內連線結構160係晶片。
參考圖26，在實施例中，3D內連線結構160包括以一系列行列配置在背表面104上方之著陸銲墊152的陣列。例如，該陣列中的行列可具有10μm至500μm的間距。可將一陣列之TSV 142配置在背表面104下，使得該陣列之TSV 142未配置成與著陸銲墊152之陣列完全相同的型樣。在實施例中，該陣列之TSV 142未在著陸銲墊152之陣列的正下方。在此種實施例中，複數個RDL 144可能繞行在著陸銲墊152的該等列中之連接兩列之一至該陣列TSV中之對應數量的TSV 142的該兩列之間。例如，著陸銲墊的該等二列可能以10μm至500μm的間距分隔。以此方式，RDL 144容許在TSV 142之實體位置及電路佈置上的彈性。
參考圖27，在實施例中，3D封裝包括基底基材170，諸如，印刷電路板或層壓基材。將晶片堆疊形成在基底基材上方，其中該晶片堆疊包括形成有3D內連線結構的晶片160。在實施例中，晶片160係邏輯晶片，且一或多個記憶體晶片180堆疊在邏輯晶片160上，邏輯晶片的著陸銲墊陣列(在導電凸塊154的陣列下方)係對準記憶體晶片180之對應陣列之著陸銲墊182，但實施例並未受限於此並可能包括各種晶片對晶片組態。
在實施例中，描述形成包括導孔(例如，TSV)及單嵌RDL之3D內連線結構的方法。可將蝕刻停止層形成在具有從裝置晶圓之背表面延伸至前表面的導孔(例如， TSV)之裝置晶圓的背表面上方，並將介電層形成在蝕刻停止層上方。然後將溝槽開口形成在介電層及蝕刻停止層中，以暴露該導孔，並以導電材料填充溝槽開口的總體積，以形成包括著陸銲墊的RDL。在實施例中，溝槽開口的形成可能以將型樣化光阻層使用為遮罩而電漿蝕刻介電層，並在蝕刻停止層上停止電漿蝕刻的方式實施。然後可使用不顯著蝕刻介電層或下方導孔之絕緣襯墊層的蝕刻化學品蝕刻該蝕刻停止層。隨後，將導電凸塊形成在著陸銲墊上方，其中該填充導孔不在著陸銲墊的正下方。
在實施例中，導孔係以最後導孔處理順序形成。在此種實施例中，在形成導孔之前，可將含碳化矽或氮化矽的鈍化層形成在裝置晶圓的背表面上方。然後將導孔開口形成在裝置晶圓的背表面及前表面之間的裝置晶圓中。將絕緣襯墊層形成在導孔開口的側壁上。將阻障層形成在導孔開口內及鈍化層上方，然後，例如，可藉由電鍍以導電金屬(諸如，銅)填充該導孔的總體積。然後藉由，例如，化學機械研磨從鈍化層上將導孔開口之間的導電金屬覆蓋層及阻障層移除。以此方式，鈍化層不僅可作用以防止濕氣及微量金屬污染進入裝置晶圓，同時也可作用為同容許將大量過研磨加入TSV阻障層CMP步驟中，而不會導致大量的鈍化層被移除的研磨停止層。
現在參考圖1-25，參考該等圖式描述製造3D內連線結構的方法。在圖1中描繪反轉的裝置晶圓100，其可能包括前表面102及背表面104。裝置晶圓100可能具有各種構 造。例如，裝置晶圓可能係單體半導體，包括覆蓋單體半導體的磊晶層，或包括絕緣層覆矽(SOI)結構，但也可使用其他結構。在所說明的特定實施例中，裝置晶圓100包括(SOI)結構，該結構包括覆蓋絕緣體層114的半導體層116及單體基材118。裝置晶圓100可能額外包括摻雜區域或其他摻雜特性圖案，以形成各種微電子裝置，諸如，金屬絕緣體半導體場效電晶體(MOSFET)，電容器、電感器、電阻器、二極體、微機電系統(MEMS)、其他合適的主動或被動裝置、及彼等的組合。
可能將金屬化結構112形成在裝置晶圓100的前表面102上。如圖所描繪的，金屬化結構112包括以導電金屬，諸如，銅、鋁等所形成的多互連層，及層間介電材料，諸如，氧化矽、碳摻雜氧化物、氮化矽等。可將鈍化層113形成在金屬化結構112的上部上方，以提供物理及化學保護。可能將一或多個導電焊墊108(例如，銅、鋁等)設置在鈍化層113中的開口上。
現在參考圖2-3，使用市售暫時接合黏合劑208及裝備將裝置晶圓100接合至暫時承載晶圓200。然後可藉由研磨、化學機械研磨(CMP)、電漿蝕刻、及/或濕蝕刻背表面104將裝置晶圓100薄化。例如，在實施例中，可能將裝置晶圓100薄化至約50-100μm。
在薄化裝置晶圓100之後，可將鈍化層120形成在背表面104上，以提供密封阻障層，如圖4描繪的。用於鈍化層120的合適材料包括碳化矽及氮化矽，因為此等材料可提 供保護薄化裝置晶圓100之背側104免於微量金屬及濕氣污染的密封阻障層。在後續的從TSV之間的鈍化層120上方將阻障層材料CMP移除期間，碳化矽及氮化矽也可能擁有顯著低於後續沈積之TSV阻障層材料，諸如，Ta或Ti，的移除率，如相關於圖12描述的。鈍化層120可能藉由合適方法，諸如化學氣相沈積(CVD)，沈積。鈍化層120可能交替地包括多層，諸如，氮化矽/氧化矽堆疊或碳化矽/氧化矽堆疊，其中將氧化矽形成在氮化矽或碳化矽上方並可在下游的導孔開口蝕刻處理使用為硬遮罩。
現在參考圖5-7，將光阻層塗佈在薄化裝置晶圓上，經曝光及顯影。在顯影後，開口在型樣化光阻層122中在期望導孔(例如，TSV)所在的位置上。然後使用合適方法，諸如，電漿蝕刻貫穿鈍化層120、並貫穿背表面104及前表面102之間的裝置晶圓100、在金屬化結構112內的銅著陸銲墊上停止，蝕刻導孔開口130(例如，TSV開口)。然後移除型樣化光阻層122，並可能將任何殘留蝕刻聚合物或殘留物清除。
然後沈積絕緣襯墊層136，襯墊導孔開口130的底部及側壁，以及在鈍化層120上方的導孔開口之間區域，如圖8描繪的。用於絕緣襯墊層136的合適材料包括，但未受限於，二氧化矽、氮化矽、碳化矽、及各種聚合物。此等材料可能藉由，例如，CVD、原子層沈積(ALD)、及旋轉塗佈法沈積。如圖9描繪的，接著可使用各向異性電漿蝕刻處理將絕緣襯墊層136從導孔開口130的底表面，及從鈍 化層120上方的導孔開口之間的區域移除，而保留絕緣襯墊層136在導孔開口130之側表面上的實質厚度。在此種實施例中，可將絕緣襯墊層136直接形成在由單體矽基材118界定的導孔開口130的側壁上。因此，絕緣襯墊層136在最終之3D內連線結構中的功能係將TSV與周圍的矽基材材料隔絕。
參考圖10-12，然後可將阻障層138及種層沈積在裝置晶圓表面上。例如，阻障層138可能包括鉭、鈦、或鈷。種層可能係，例如，銅。然後將銅140的覆層電鍍在裝置晶圓表面上，以銅完全填充TSV開口130。然後藉由CMP將鈍化層120上方的銅覆蓋層及阻障層移除，如圖12描繪的。所產生的結構包括貫穿裝置晶圓100延伸在前102及背104表面之間的TSV 142。在此種組態中，單金屬填充物140佔據TSV 142的總體積，其可能以阻障層138及種層(例如，用於電鍍)及絕緣襯墊層136襯墊。
在實施例中，在使用第一漿體的第一CMP操作中移除銅140的覆蓋層，然後在使用與第一漿體不同之第二漿體的第二CMP操作中從鈍化層120上方將阻障層138移除。用於阻障層138移除的市售CMP漿體係設計成蝕刻阻障材料，諸如，Ta、Ti、TaN、及TiN，並也典型地設計成蝕刻氧化物。根據本發明的實施例，鈍化層120在移除阻障層138期間的功能可能如同研磨停止層，其容許阻障層138CMP操作合併大量的過研磨而不導致移除大量的鈍化層120。
現在參考圖13-16，將蝕刻停止層121形成在鈍化層120及導孔142上方。用於蝕刻停止層121的合適材料包括氮化矽或碳化矽。然後將介電層123形成在蝕刻停止層121上方。例如，介電層123可能包括二氧化矽。然後將光阻層塗佈在介電層123上方，經曝光及顯影。在顯影後，開口在型樣化光阻層125中在期望具有著陸銲墊之精細間距RDL所在的位置上。然後使用合適技術，諸如，電漿蝕刻，將型樣化光阻層125使用為遮罩，在蝕刻停止層121停止，貫穿介電層123的全部深度，蝕刻溝槽開口134。在實施例中，一旦將介電層123往下清理至蝕刻停止層121，將電漿蝕刻化學作用改變為選擇性地蝕刻蝕刻停止層121，而對溝槽開口134的介電層123側壁及下絕緣襯墊層136無實質影響。根據本發明的實施例，蝕刻停止層121可能在溝槽開口134形成期間保護絕緣襯墊層136免於受損，以保護TSV結構的完整性。在蝕刻處理後，移除型樣化光阻層125並可能清除任何殘留蝕刻聚合物或殘留物。
現在參考圖17-19，接著可將阻障層139及種層沈積在裝置晶圓表面上。例如，阻障層139可能包括，例如，Ta、Ti、TaN、TiN。種層可能係，例如，銅。然後將銅141的覆層電鍍在裝置晶圓表面上，以銅填充溝槽開口134的總體積。然後藉由CMP將介電層123上方的銅覆蓋層及阻障層移除，如圖19描繪的。所產生的RDL 144可能包括著陸銲墊，其中導孔142不在著陸銲墊的正下方，並可以阻障層139及種層(例如，用於電鍍)襯墊。在實施例 中，在使用第一漿體的第一CMP操作中移除銅141的覆蓋層，然後在使用與第一漿體不同之第二漿體的第二CMP操作中將介電層123上方的阻障層139移除。
現在參考圖20-23，將著陸銲墊開口形成在RDL 144之上。將鈍化層146沈積在平坦化表面上方。合適材料包括，但未受限於，可能提供免於微量金屬及濕氣污染的保護，及保護RDL 144免於氧化之密封阻障層的氮化矽。然後將光阻材料塗佈在鈍化層146上方，經曝光並顯影，以形成型樣化光阻層148。在顯影後，開口150在光阻層148中而在RDL 144於晶片對晶片連接所期望之著陸銲墊終止的該等位置。然後使用合適技術，諸如，將型樣化光阻層148使用為遮罩、在著陸銲墊152下方的RDL 144停止的電漿蝕刻，將開口蝕刻貫穿鈍化層146。然後移除光阻層148，並可能將任何殘留蝕刻聚合物或殘留物清除。
現在參考圖24，將導電凸塊154形成在各經暴露RDL 144的著陸銲墊152上方。可能以任何合適的技術實作，以形成導電凸塊154，諸如，但未受限於，焊塊、使用型樣化處理的電鍍、及無電電鍍。在描繪於圖24中的特定實施例中，以與焊劑相容的表面修飾塗佈經暴露RDL 144的著陸銲墊152。用於導電凸塊154的例示表面修飾包括無電電鍍CoP/浸潤Au、無電電鍍CoWP/浸潤Au、無電電鍍NiP/浸潤Au、無電電鍍NiP/無電電鍍Pd/浸潤Au、無電電鍍Sn、無電電鍍NiP/無電電鍍Sn、無電電鍍CoP/無電電鍍Sn、無電電鍍CoWP/無電電鍍Sn、無電電鍍Cu/無電電鍍CoP/浸 潤Au、無電電鍍Cu/無電電鍍CoWP/浸潤Au、無電電鍍Cu/無電電鍍NiP/浸潤Au、無電電鍍Cu/無電電鍍NiP/無電電鍍Pd/浸潤Au、無電電鍍Cu/無電電鍍Sn、無電電鍍Cu/無電電鍍NiP/無電電鍍Sn、無電電鍍Cu/無電電鍍CoP/浸潤Au、無電電鍍Cu/無電電鍍CoWP/無電電鍍Sn。取決於所使用的晶片對晶片焊劑材料(等)及/或晶片對晶片附接法，其他表面修飾也可能適合。在另一實施例中，導電凸塊154可能係C4或以諸如，PbSn、Sn、SnAg、Cu、In、SnAgCu、SnCu、Au等形成的覆晶凸塊。
接著可使用市售晶圓解接合裝備及處理從裝置晶圓100將承載晶圓200及黏合劑208移除，如圖25描繪的。在移除承載晶圓200及黏合劑208時，可將圖25描繪之所產生的複數個3D內連線結構160切片，然後可能或可能不進一步處理以形成晶片，接著可將彼等積集為3D封裝結構。
參考圖26，針對根據本發明的實施例之將第二晶片連接至3D內連線結構，描繪例示之標準化晶片對晶片著陸銲墊介面。如在放大圖中更詳細地描繪的，將著陸銲墊152陣列以一系列行列配置在背表面104上方(見圖25)。將TSV 142陣列配置在該背表面104下方，使得TSV陣列不在著陸銲墊152陣列的正下方。複數個RDL 144繞行在將著陸銲墊152的該等列之二列的一者連接至TSV陣列中之對應數量的TSV 142之著陸銲墊152的該等二列之間。以此方式，將背側著陸銲墊152連接至前側電路(金屬化表面112)的TSV可位於晶片上的任何位置。在已然描述TSV陣列不在 著陸銲墊及/或導電凸塊陣列正下方之本發明的實施例的同時，待理解部分TSV可能在著陸銲墊及/或導電凸塊陣列正下方。本發明的實施例藉由積集單嵌處理提供彈性的TSV位置。結果，不需要TSV陣列的位置在TSV連接至其之著陸銲墊及/或導電凸塊的對應陣列的正下方。
為進一步說明容許電路設計彈性的本發明之實施例的能力，在一範例中，描繪於圖26中的著陸銲墊152陣列可能具有50μm的垂直間距及40μm的水平間距，且著陸銲墊152具有20μm的直徑。在此特定範例中，保留30μm以在二列著陸銲墊152之間繞行六個RDL 144。假設六個RDL線寬及與RDL 144相鄰及在彼等之間的七個間距均相同，各RDL 144可能具有2.3μm的線寬。根據本發明之實施例的單嵌型處理可能特別適合完成此種例示之間距精細的RDL架構，雖然實施例未受如此限制且也可能用於任何間距的RDL架構。
圖27係根據本發明的實施例之實作3D內連線結構之特定實施樣態的3D封裝的說明範例。如圖描繪的，將複數個晶片堆疊在基材170上方，諸如，印刷電路板或層壓基材。例如，晶片160可能包括如本文描述的3D內連線結構。在一實施例中，晶片160係包括如本文描述之3D內連線結構的邏輯晶片且晶片180係記憶體晶片。例如，3D封裝可能包括堆疊在邏輯晶片160上方的一或多個記憶體晶片180。或者，3D封裝可能替代地包括堆疊在至少一記憶體晶片180上方的邏輯晶片160。如圖描繪的，將導電凸塊 154的陣列以及導電凸塊154下方的著陸銲墊152(未圖示)與記憶體晶片180之對應著陸銲墊182陣列對準，並將導電焊墊108與基材170連接。待理解雖然圖27係邏輯晶片160及記憶體晶片180之例示堆疊的說明，本發明的實施例並未受限於此，且晶片可能係任何合適的晶片，諸如，記憶體(例如，DRAM、eFLASH、eRAM等)、插入器、RF、MEMS等。
圖28顯示根據本發明之實施例的電腦系統。在部分實施例中，系統300包括處理器310、記憶體裝置320、記憶體控制器330、圖形控制器340、輸入及輸出(I/O)控制器350、顯示器352、鍵盤354、指標裝置356、及周邊裝置358，彼等可能全部經由匯流排360彼此通訊地耦合。處理器310可能係通用處理器或特定應用積體電路(ASIC)。I/O控制器350可能包括用於有線或無線通訊的通訊模組。記憶體控制器320可能係動態隨機存取記憶體(DRAM)裝置、靜態隨機存取記憶體(SRAM)裝置、快閃記憶體裝置、或此等記憶體裝置的組合。因此，在部分實施例中，系統300中的記憶體裝置320不必包括DRAM裝置。
顯示在系統300中的一或多個組件可能包括在及/或包括一或多個積體電路封裝，諸如，圖27的晶片160或3D封裝。例如，處理器310，或記憶體裝置320、或至少一部分的I/O控制器350，或此等組件的組合可能包括在包括描述在各種實施例中的結構之至少一實施例的積體電路封裝中。
此等元件實施彼等之已為人熟知的習知功能。特別係可能在部分情形中使用記憶體裝置320，以提供用於根據本發明的實施例之形成封裝結構的方法之可執行指令的長期儲存器，且在其他實施例中，可能在處理器310執行期間在較短期基礎上用於儲存根據本發明的實施例之形成封裝結構的方法之可執行指令。此外，可能將該等指令儲存，或另外關聯於與該系統通訊地耦合之機器可存取媒體，諸如，光碟唯讀記憶體(CD-ROM)、數位多樣化光碟(DVD)、及軟碟、載波、及/或其他傳播訊號。在一實施例中，記憶體裝置320可能以用於執行的可執行指令供應處理器310。
系統300可能包括電腦(例如，桌上型電腦、膝上型電腦、手持電腦、伺服器、網路器具、路由器等)、無線通訊裝置(例如，行動電話、無線電話、傳呼器、個人數位助理等)、電腦相關周邊(例如，印表機、掃描器、監視器等)、及娛樂裝置(例如，電視機、收音機、立體音響、卡帶及光碟播放器、卡式錄影機、攝影機、數位相機、MP3(動態影像專家壓縮標準，音訊層面3)播放器、電視遊戲、手錶等)等。
圖29描繪根據本發明之一實施例的計算裝置400。計算裝置400收納板402。板402可能包括許多組件，包括但未受限於處理器404及至少一通訊晶片406。將處理器404實體地及電性地耦合至板402。在部分實施例中，也將至少一通訊晶片406實體地及電性地耦合至板402。在其他實 作中，通訊晶片406係處理器404的一部分。
取決於其應用，計算裝置400可能包括可能或可能不實體地及電性地耦合至板402的其他組件。此等其他組件包括，但未受限於，依電性記憶體(例如，DRAM)、非依電性記憶體(例如，ROM)、快閃記憶體、圖形處理器、數位訊號處理器、加密處理器、晶片組、天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池、音訊編碼解碼器、視訊編碼解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、加速度計、迴轉儀、揚聲器、相機、及大量儲存裝置(諸如，硬碟機、光碟(CD)、及數位多樣化光碟(DVD)等)。
通訊晶片406致能用於將資料傳輸至計算裝置400或自其傳輸資料的無線通訊。術語「無線」及其衍生術語可能用於描述可能透過非實質媒體經由使用調變電磁輻射通訊資料的電路、裝置、系統、方法、技術、通訊頻道等。該術語未暗示該等關聯裝置不包含任何線路，雖然在部分實施例中彼等可能不含。通訊晶片406可能實作任何數量的無線標準或協定，包括但未受限於Wi-Fi(IEEE 802.11家族)、WiMAX(IEEE 802.16家族)、IEEE 802.20、長期演進技術(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙、彼等的衍生物，以及指定為3G、4G、5G、及之後的任何其他無線協定。計算裝置400可能包括複數個通訊晶片406。例如，第一通訊晶片406可能專用於較短範圍的 無線通訊，諸如，Wi-Fi及藍牙，且第二通訊晶片406可能專用於較長範圍的無線通訊，諸如，GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、及其他。
計算裝置400的處理器404包括封裝在處理器404內的積體電路晶粒。在本發明的部分實作中，處理器的積體電路晶粒可能包括在或可能包括一或多個積體電路封裝，諸如，圖27的晶片160或3D封裝。術語「處理器」可能指處理來自暫存器及/或記憶體之電子資料的任何裝置或裝置之一部分，以將該電子資料轉移為可能儲存在暫存器及/或記憶體中的其他電子資料。
通訊晶片406也包括封裝在通訊晶片406內的積體電路晶粒。根據本發明的另一實作，通訊晶片的積體電路晶粒可能包括在或可能包括一或多個積體電路封裝，諸如，圖27的晶片160或3D封裝。
在其他實作中，收納在計算裝置400內的其他組件可能包含積體電路封裝，諸如，圖27的晶片160或3D封裝。此外，例如，可能將收納在計算裝置400內的處理器404、通訊晶片406、及其他組件堆疊在圖27的3D封裝中。
在各種實作中，計算裝置400可能係膝上型電腦、隨身型易網機、筆記型電腦、超輕薄筆記型電腦、智慧型手機、平板電腦、個人數位助理(PDA)、超級行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂控制單元、數位相機、可攜式音樂播放器、或數位視訊錄影機。在其他實作中，計算裝置400可 能係處理資料的任何其他電子裝置。
雖然本發明已用用於結構化特性及/或方法行為的特定語言描述，待理解界定在隨附申請專利範圍中的本發明不必然受限於所描述的該等具體特性或行為。取而代之地將所揭示的具體特性及行為理解為對說明本發明有用之本發明的特別適度的實作。
100‧‧‧半導體基材
102‧‧‧前表面
104‧‧‧背表面
108‧‧‧導電焊墊
112‧‧‧金屬化結構
113、120、146‧‧‧鈍化層
114‧‧‧絕緣器層
116‧‧‧半導體層
118‧‧‧凸塊基材
121‧‧‧蝕刻停止層
122、125、148‧‧‧型樣化光阻層
123‧‧‧介電層
130‧‧‧導孔開口
134‧‧‧溝槽開口
136‧‧‧絕緣襯墊層
138、139‧‧‧阻障層
140、141‧‧‧銅
142‧‧‧導孔
144‧‧‧單嵌再分佈層(RDL)
150‧‧‧開口
152、182‧‧‧著陸銲墊
154‧‧‧導電凸塊
160‧‧‧3D內連線結構
170‧‧‧基底基材
180‧‧‧記憶體晶片
200‧‧‧承載晶圓
208‧‧‧接合黏合劑
300‧‧‧系統
310、404‧‧‧處理器
320‧‧‧記憶體裝置
330‧‧‧記憶體控制器
340‧‧‧圖形控制器
350‧‧‧輸入及輸出(I/O)控制器
352‧‧‧顯示器
354‧‧‧鍵盤
356‧‧‧指標裝置
358‧‧‧周邊裝置
360‧‧‧匯流排
400‧‧‧計算裝置
402‧‧‧板
406‧‧‧通訊晶片
圖1-25係根據本發明的實施例之使用單嵌處理製造3D內連線結構的方法的橫剖面側視圖。
圖26係根據本發明的實施例之3D內連線結構的示意頂視圖。
圖27係根據本發明的實施例之實作TSV的3D封裝的側視圖。
圖28呈現根據本發明之實施例的系統。
圖29呈現根據本發明之實施例的計算裝置。
100‧‧‧半導體基材
102‧‧‧前表面
104‧‧‧背表面
108‧‧‧導電焊墊
112‧‧‧金屬化結構
113、120、146‧‧‧鈍化層
114‧‧‧絕緣器層
116‧‧‧半導體層
118‧‧‧凸塊基材
121‧‧‧蝕刻停止層
123‧‧‧介電層
136‧‧‧絕緣襯墊層
138、139‧‧‧阻障層
142‧‧‧導孔
144‧‧‧單嵌再分佈層(RDL)
154‧‧‧導電凸塊
160‧‧‧3D內連線結構

Claims (17)

  1. 一種3D內連線結構，包含：具有前表面及背表面的半導體基材；該等前及背表面之間延伸且貫穿該半導體基材的導孔；形成在該背表面上方的單嵌再分佈層(RDL)；在該背表面上方配置成一系列行列的著陸銲墊陣列；配置在該背表面下方的貫矽導孔(TSV)陣列，使得該TSV陣列不在該著陸銲墊陣列的正下方；及繞在該等著陸銲墊列的二列之間的複數個RDL，將該等二列的一列連接至TSV陣列中之對應數量的TSV。
  2. 如申請專利範圍第1項的3D內連線結構，更包含設置在該背表面及該等RDL之間的鈍化層。
  3. 如申請專利範圍第2項的3D內連線結構，其中該鈍化層包含碳化矽或氮化矽。
  4. 如申請專利範圍第3項的3D內連線結構，其中該導孔更包含：形成在該半導體基材中的導孔開口之側表面上的絕緣襯墊層；形成在該導孔開口的底表面上，及在形成在該導孔開口的該等側表面上之該絕緣襯墊層上的連續阻障層；及填充該導孔開口之總體積的導電金屬。
  5. 如申請專利範圍第4項的3D內連線結構，其中該單嵌RDL更包含： 形成在介電層中暴露該鈍化層及該導孔的溝槽開口之側表面上的阻障層；及填充該溝槽開口之總體積的導電金屬。
  6. 如申請專利範圍第1項的3D內連線結構，其中該等著陸銲墊的該等二列係以10μm至500μm的間距分隔。
  7. 一種3D封裝，包含：基底基材；及形成在該基底基材上方的晶片堆疊；其中該晶片堆疊包括晶片，該晶片包含：具有前表面及背表面的半導體基材；在該半導體基材之該等前及背表面之間延伸的導孔；及形成在該背表面上方的單嵌再分佈層(RDL)；在該背表面上方配置成一系列行列的著陸銲墊陣列；配置在該背表面下方的貫矽導孔(TSV)陣列，使得該TSV陣列不在該著陸銲墊陣列的正下方；及繞在該等著陸銲墊列的二列之間的複數個RDL，將該等二列的一列連接至TSV陣列中之對應數量的TSV。
  8. 如申請專利範圍第7項的3D封裝，其中該晶片係邏輯晶片。
  9. 如申請專利範圍第8項的3D封裝，更包含系統，該系統包含通訊地耦合至該3D封裝的匯流排。
  10. 如申請專利範圍第7項的3D封裝，其中該著陸銲墊陣列與記憶體晶片的對應著陸銲墊陣列耦合。
  11. 一種形成3D內連線結構的方法，包含：形成蝕刻停止層在裝置晶圓的背表面上方，該裝置晶圓具有從該裝置晶圓的該背表面延伸至前表面的導孔；形成介電層在該蝕刻停止層上方；形成溝槽開口在該介電層及蝕刻停止層中，以暴露該導孔；以導電金屬填充該溝槽開口的總體積，以形成包括著陸銲墊的再分佈層(RDL)，其中該導孔不在該著陸銲墊的正下方；將導電凸塊形成在該著陸銲墊上方；在該背表面上方形成為一系列行列的著陸銲墊陣列；在該背表面下方形成貫矽導孔(TSV)陣列，使得該TSV陣列不在該著陸銲墊陣列的正下方；以及形成繞在該等著陸銲墊列的二列之間的複數個RDL，將該等二列的一列連接至TSV陣列中之對應數量的TSV。
  12. 如申請專利範圍第11項的方法，在形成該蝕刻停止層的步驟之前：形成鈍化層在該裝置晶圓的該背表面上方，其中該鈍化層包含碳化矽或氮化矽；形成導孔開口在該裝置晶圓的該背表面及前表面之間的該裝置晶圓中；形成阻障層在該導孔開口內及該鈍化層上方；以導電金屬填充該導孔開口的總體積；從該鈍化層上方移除該導電金屬及該阻障層的覆蓋 層，以形成該導孔。
  13. 如申請專利範圍第12項的方法，更包含沈積絕緣襯墊層在該導孔開口的側及底表面上。
  14. 如申請專利範圍第13項的方法，更包含從該導孔開口的該底表面各向異性蝕刻該絕緣襯墊層，而在該導孔開口之該等側表面上保持實質厚度。
  15. 如申請專利範圍第14項的方法，其中以導電金屬填充該導孔開口之總體積包含電鍍銅。
  16. 如申請專利範圍第11項的方法，其中形成該溝槽開口包含將型樣化光阻層使用為遮罩，並使用選擇性蝕刻該蝕刻停止層而不實質蝕刻該溝槽開口的該介電層之側壁及絕緣襯墊層的電漿蝕刻化學蝕刻該蝕刻停止層。
  17. 如申請專利範圍第11項的方法，其中該等著陸銲墊的該等二列係以10μm至500μm的間距分隔。
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