CN101794717A - 堆叠集成芯片及其制造方法 - Google Patents

堆叠集成芯片及其制造方法 Download PDF

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Publication number
CN101794717A
CN101794717A CN201010002812A CN201010002812A CN101794717A CN 101794717 A CN101794717 A CN 101794717A CN 201010002812 A CN201010002812 A CN 201010002812A CN 201010002812 A CN201010002812 A CN 201010002812A CN 101794717 A CN101794717 A CN 101794717A
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substrate
insulating cell
layer
etching
opening
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CN101794717B (zh
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陈明发
黄招胜
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

描述了堆叠集成芯片及其制造方法。在一个实施例中，形成半导体芯片的方法包括从第一衬底的顶面形成用于衬底通孔的开口。用绝缘衬垫对开口的侧壁加衬，并用导电填充材料来填充开口。从相对的底面开始蚀刻第一衬底以形成突起，突起被绝缘衬垫所覆盖。在突起周围沉积抗蚀剂层，以露出绝缘衬垫的一部分。蚀刻所露出的绝缘衬垫，以沿着突起形成侧壁隔离物。

Description

堆叠集成芯片及其制造方法
技术领域
本发明总的来说涉及集成芯片，更具体地，涉及堆叠集成芯片及堆叠集成芯片的制造方法。
背景技术
通过在半导体衬底中形成有源区，在衬底上方沉积各种绝缘层、导电层和半导体层以及以顺序步骤对这些层进行图样化来制造半导体器件。半导体器件的上部层或最后形成的层通常包括金属化层。金属化层通常包括具有设置在绝缘材料内的导电线的金属互连件的一层或多层，并且可以提供与下层有源区的连接以及衬底内和衬底上方的连接。集成电路芯片可附接至引线框架，然后被封装在陶瓷或塑料载体中。
然而，随着缩小半导体器件成本的持续减少，已经开发了可选方式，诸如将电路的集成延伸到第三维或半导体衬底堆叠。将两个以上的衬底结合到一起以形成三维结构。堆叠衬底的有源电路通过一个或多个衬底通孔连接。
然而，三维集成对制造来说提出了许多挑战。一种挑战在于三维集成涉及在不形成附加短路径或泄露路径的情况下在堆叠衬底之间形成结合点。
用于连接衬底的衬底通孔通过介电层与衬底绝缘。然而，例如，在结合点形成工艺期间形成的下层衬底与衬底通孔之间的电短路会对加工产量产生有害的影响，因此是不期望的。
因此，所需要的是在不危及加工产量的情况下堆叠半导体衬底的成本有效方法。
发明内容
通过本发明的优选实施例，这些和其他问题总体上都被解决或避免并且总体上实现了技术优势。
本发明的实施例包括堆叠半导体芯片。根据本发明的优选实施例，形成半导体芯片的方法包括：从第一衬底的顶面形成用于衬底通孔的开口；以及用绝缘衬垫对开口的侧壁加衬。该方法还包括：用导电填充材料来填充开口；以及从相对的底面蚀刻第一衬底以形成突起，突起被绝缘衬垫所覆盖。然后，在突起周围沉积抗蚀剂层，以露出绝缘衬垫的一部分。蚀刻所露出的绝缘衬垫，以沿着突起形成侧壁隔离物。
上面已经概述(而不是完全描述)了本发明实施例的特征，以更好地理解以下本发明的详细描述。以下将描述本发明实施例的其它特征和优点，其形成本发明权利要求的主题。本领域的技术人员应该理解，所公开的概念和具体实施例可以被容易地用作修改或设计执行本发明的相同目的的结构或工艺的基础。本领域的技术人员应该意识到，这种等效的构造并不背离在所附权利要求中阐述的本发明的精神和范围。
附图说明
为了更好地理解本发明及其优点，结合附图进行以下描述，其中：
图1(包括图1a至图1m)示出了根据本发明实施例的在制造期间包括衬底通孔的堆叠集成芯片；
图2(包括图2a至图2e)示出了根据本发明实施例的在制造期间包括衬底通孔的堆叠集成芯片；以及
图3(包括图3a和图3b)示出了使用本发明的实施例形成的堆叠衬底电路。
除非另有指定，不同附图中对应的参考标号和符号通常表示对应的部件。绘制附图是为了清晰地示出本实施例的相关方面，并且并不必须按比例绘制。
具体实施方式
下面详细描述本发明优选实施例的制造和使用。然而，应该理解，本发明提供了许多可以在具体环境下实现的许多可应用的发明概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，并不限制本发明的范围。
衬底通孔通过介电层与衬底绝缘。例如，使用焊球将来自一个芯片的衬底通孔结合至另一衬底适当的连接焊盘(landing pad)或下凸块结构。然而，用在结合工艺中的一些导电材料可以在结合点与衬底之间形成导电带，由此将衬底通孔电连接至衬底。在各个实施例中，本发明通过侧壁隔离物(在结合点形成期间仅露出衬底通孔的一部分)的使用而避免了这种电短路，因此，抑制了衬底和结合点之间电带的形成。
图1和图2示出了形成堆叠集成芯片的实施例，而图3示出了堆叠集成芯片。
图1(包括图1a至图1m)示出了根据本发明实施例的在制造期间包括衬底通孔的堆叠集成芯片。
参照图1a，在前端处理期间，在衬底10的顶面附近侧上形成有源器件区域11。衬底10通常为半导体晶片。有源器件区域11或有源电路可包括晶体管、电阻器、电容器、电感器或用于形成集成电路的其他部件。例如，包括晶体管(例如，CMOS晶体管)的有源区域可通过隔离区域(例如，浅沟槽隔离件)彼此隔离。在可选实施例中，有源器件区域11包括双极晶体管。
参照图1a，衬底10的实例包括块状单晶硅衬底(或其上生长或形成在其中的层)、{100}硅晶片上的{110}硅层、绝缘体上硅(SOI)晶片层或绝缘体上锗(GeOI)晶片层。在其他实施例中，诸如硅锗、锗、砷化镓、砷化铟、砷化镓铟、锑化铟等的其他半导体可以被用作晶片。
在衬底10中形成隔离沟槽。可将传统技术用于形成隔离沟槽。例如，可以在衬底10的上方形成诸如氮化硅的硬掩模层(未示出)，并对其进行图样化以露出隔离区域。然后，可以将衬底10的露出部分蚀刻到合适的深度，通常在约200nm和约400nm之间。用隔离沟槽填充隔离沟槽，从而形成浅沟槽隔离件15。沉积栅极电介质，然后形成栅极堆叠件12。栅极堆叠件12包括诸如多晶硅或金属化或硅化物材料的半导体材料。利用注入和退火工艺对源极/漏极延伸部、源极/漏极以及沟道区域进行掺杂，以形成晶体管13。
接下来，在有源器件区域11上方进行金属化件，以与有源器件区域11电接触或互连。金属化件和有源电路一起形成完成的功能性集成电路。换句话说，可通过互连的有源电路来执行芯片的电功能。在逻辑器件中，金属化件包括许多铜层，例如九层以上。在诸如DRAM的存储器件中，金属层的数量可以少一些并且可以为铝。
在前端处理期间形成的部件通过后端连线(BEOL)处理进行互连。在该处理期间，进行与半导体的接触并使用金属线和通孔互连。如上所述，现有的集成电路集合了将芯片中各个部件进行互连的垂直堆叠的金属线和通孔(多层金属化件)的许多层。
现在，参照图1b，在蚀刻阻止衬垫上方形成第一绝缘材料层21。在沉积第一绝缘材料层21之前，在衬底10上方沉积蚀刻阻止衬垫，从而在接触插塞形成期间还保护下层的衬底。例如，沉积氮化物膜(例如，氮化硅)作为蚀刻阻止衬垫。
优选地，绝缘材料层21包括通常在层间电介质(ILD)层的半导体制造中使用的绝缘材料，诸如SiO2、正硅酸乙酯(TEOS)、掺杂氟的TEOS(FTEOS)、掺杂玻璃(BPSG、PSG、BSG)、有机硅酸盐玻璃(OSG)、掺杂氟的硅酸盐玻璃(FSG)、旋涂玻璃(SOG)、SiN、SiON。ILD还可以包括适当的低k或超低k(ULK)材料。例如，尽管可选地，ILD可包括其他尺寸，但ILD可包括约500nm以下的厚度。
在具有衬底接触插塞的区域中，第一绝缘材料层21和蚀刻阻止衬垫可以被图样化和蚀刻。衬底接触插塞22可以由多层结构制成，该多层结构包括第一导电衬垫(例如，CVD氮化钛和掺杂硅的钨)和第一导电材料(例如，钨)。
现在，参照图1c，然后在第一绝缘材料层21上方沉积第二绝缘材料层31。优选地，第二绝缘材料层31包括具有3.6以下的介电常数的低k介电材料，并且可要求例如高达400度的加热处理以去除溶剂。例如，利用掩模，经由光刻法对第二绝缘材料层31进行图样化。在第二绝缘材料层31的上方沉积光刻胶，以及露出、显影和去除光刻胶的一部分，留下用于金属线的图样。去除所露出的第二绝缘材料层31，以在第二绝缘材料层31中形成开口。
优选地，使用共形(conformal)沉积工艺来沉积第二导电衬垫，沿着开口的内壁留下共形衬垫或扩散阻挡层。优选地，第二导电衬垫包括通过等离子体汽相沉积(PVD)沉积的氮化钽。可选地，第二导电衬垫可包括氮化钛、氮化钨、难熔金属或其他可使用例如CVD、PVD工艺或无电电镀共形沉积的阻挡层。第二导电衬垫可包括材料双层，例如包括阻挡层和共形种层，其优选包括铜、铝、其他金属或它们的组合。例如，可使用CVD工艺沉积种层。
例如，使用电镀填充工艺来用第二导电材料32填充开口的剩余部分，以形成第一金属线(MI)，该第一金属线具有处于第二绝缘材料层31内的部分和处于第一绝缘材料层21上方的部分。优选地，第二导电材料32包括铜、铝、其他金属或它们的组合。
在第二绝缘材料层31上方沉积第三绝缘材料层41。对第三绝缘材料层41进行图样化和蚀刻以制造通孔。用诸如铜的第三导电材料42填充通孔，以形成第一通孔层(via level)(V1)。类似地，在第一通孔层(V1)的上方形成更多的金属线层和通孔层。例如，例如，在图1c中，形成包括第二金属线层(M2)、第二通孔层(V2)、第三金属线层(M3)、第三通孔层(V3)和第四金属线层(M4)的第四、第五、第六、第七和第八绝缘材料层51、61、71、81和91。通过重复形成金属线和通孔的工艺，可以如上所述地处理其它金属线层M2、M3、M4和通孔层V2、V3等。
如图1d所示，在最后的金属线(第四金属线层M4)的上方沉积钝化层111。钝化层111是绝缘层，并且通常包括氧化物层或氧化物/氮化物层堆叠件。在其他实施例中，钝化层111可包括具有聚酰亚胺、光电酰亚胺(photoimide)、BCB或其他有机聚合物的氮化硅或氮氧化硅、FTEOS、SiCOH或者它们的组合。在钝化层111的上方沉积可选的绝缘衬垫。在一个实施例中，可选的绝缘衬垫包括氮化物层。在各个实施例中，可选的绝缘衬垫可包括FTEOS、SiO2、SiCOH或其他低k材料。
在钝化层111的上方沉积硬掩模层121(图1d)。在各个实施例中，例如通过旋涂工艺来涂覆硬掩模层121，或者使用化学汽相沉积工艺来涂覆硬掩模层121。在各个实施例中，硬掩模层121包括氮化物、有机聚合物、BCB、聚酰亚胺、光电酰亚胺或无机电介质。
在一些实施例中，硬掩模层121还是感光性的，并可以使用光刻法直接进行曝光。感光硬掩模层121的实例包括可以直接显影的感光聚酰亚胺。在非感光聚酰亚胺的情况下，沉积光刻胶。使用光刻工艺，对硬掩模层121和钝化层111进行图样化，以形成用于形成衬底通孔的图样(图1d)。
使用图样化后的硬掩模层121，如图1e所示，蚀刻金属化层和衬底10，以形成衬底通孔(TSV)开口131。在各个实施例中，可以使用多重蚀刻化学剂，以蚀刻透各个绝缘层(可包括不同的材料)。
再次参照图1e，RF等离子体室中的高密度等离子体工艺可以用于形成TSV开口131。在一个实施例中，高度各向异性蚀刻被用于形成TSV开口131。在其他实施例中，可以使用其他类型的蚀刻工艺，包括使用同步底部蚀刻和侧壁钝化的工艺。
在一个实施例中，使用基于氟的等离子体执行蚀刻步骤。然而，基于氟的蚀刻是各向同性的，从而导致非垂直的沟槽侧壁。因此，通过将聚合物产生气体引入等离子体室来执行沉积步骤。聚合物产生气体将聚合物层沉积在形成临时蚀刻停止层的所露出侧壁上。由于碰撞离子的高能量，没有在沟槽的露出底面上形成聚合物层。沉积在沟槽底面上的聚合物通过碰撞离子的高能量而被分解。在后续的蚀刻和沉积步骤中执行衬底贯穿开口蚀刻工艺。由此，可生成垂直沟槽。例如，氟蚀刻步骤可包括SF6蚀刻剂，而聚合物产生气体可包括C4F8。可以使蚀刻和沉积步骤重复多次(例如，约100次至约500次)，以形成TSV开口131。在其他实施例中，可以使用其他类型的反应离子蚀刻工艺。
TSV开口131的顶部包括约2μm至约20μm的宽度。由此生成的TSV开口131包括范围为约1∶3至约1∶30的高纵横比(宽度与深度的比)开口。
接下来，如图1f所示，TSV开口131通过绝缘衬垫141而加衬，该绝缘衬垫形成在TSV开口131的侧壁上。绝缘衬垫141使有源器件区域11与(将形成的)衬底通孔电绝缘。绝缘衬垫141可包括二氧化硅、氮化硅、氮氧化硅、SiC、SiCN、密集或多孔低k或超低k介电材料、有机材料或聚合物(如聚对二甲苯基、BCB、SiLK等)。在一些实施例中，绝缘衬垫141被各向异性蚀刻以形成侧壁隔离物。
如图1f所示，在绝缘衬垫141上沉积沟槽衬垫142。包括一个或多个金属衬垫的沟槽衬垫142被沉积在绝缘衬垫141上方。沟槽衬垫142至少连续地沉积在绝缘衬垫141的上方，并被理想地共形。沟槽衬垫142可包括单层或多层。在各个实施例中，沟槽衬垫142包含Ta、TaN、W、WN、WCN、WSi、Ti、TiN、Ru、Cu和它们的组合。沟槽衬垫142在一些实施例中被用作阻挡层，用于防止金属扩散到下面的衬底10和绝缘衬垫141中。
使用化学汽相沉积工艺、等离子体增强型CVD工艺、等离子体汽相沉积工艺或它们的组合来形成沟槽衬垫142的金属衬垫，但在其他实施例中也可以使用其他工艺。
沟槽衬垫142包括Ti/TiN层或Ta/TaN层以及铜种层。例如，沉积5至30nm的钛层，然后沉积约10至100nm的TiN层以及50至1000nm的铜种层。
参照图1g，在TSV开口131中沉积导电填充材料145并进行平坦化。在各个实施例中，在沟槽衬垫142上方电镀导电填充材料145。导电填充材料145包括导电材料，诸如铜或可选为铝、钨、银、金或掺杂多晶硅。在各个实施例中，导电填充材料145包括铜。接下来，执行后化学机械抛光(CMP)清洁以去除任何悬浮残留物(slurry residual)。
可选地，平坦化工艺包括CMP。CMP工艺从钝化层111的上方去除导电填充材料145和下面的沟槽衬垫142。在各个实施例中，在绝缘衬垫141和/或钝化层111上停止抛光工艺。随后，在钝化层111的上方形成再分配线。
钝化层111上方的导电填充材料145被图样化以形成结合焊盘(图1h)。参照图1h，在钝化层111的上方沉积沟槽绝缘材料层152并进行平坦化。然后，可以沉积并图样化聚酰亚胺材料156等，以形成凸点下金属化(UMB，under metallization bump)结构155。然后，例如通过在聚酰亚胺材料156上沉积粘合材料层，将载体(未示出)附接至衬底。
参照图1i，例如，通过翻转并研磨、精研、抛光和/或蚀刻工艺，从背侧减薄衬底10。衬底10被蚀刻，从而露出衬底通孔的一部分，以形成突起161。
优选地，使用湿蚀刻工艺以具有衬底10相对于绝缘衬垫141的高选择性。然而，可采用衬底10相对于绝缘衬垫141大于10∶1的选择性，然而优选大于20∶1的蚀刻选择性。这种湿蚀刻化学剂的高选择性使得衬底10与绝缘衬垫141相比被以更快的速率蚀刻。因此，绝缘衬垫141还保护下面的导电填充材料145和沟槽衬垫142防止在湿蚀刻工艺期间被蚀刻，由此形成从衬垫10突出的突起161。在一个实施例中，例如使用包括硝酸、水、醋酸和氢氟酸的湿蚀刻化学剂来蚀刻衬底10。突起从衬底10延伸了第一距离L。在各个实施例中，第一距离L为约2um至约35um。
接下来，参照图1j，例如使用旋涂工艺来涂覆抗蚀剂层171。抗蚀剂层171形成为薄层，并覆盖绝缘衬垫141和沟槽衬垫142的第一部分。可以将抗蚀剂层171的厚度控制为第二距离H。抗蚀剂层171的使用能够精确控制该第二距离H，因此能够精确控制随后形成的TSV侧壁隔离物。选择抗蚀剂层171，从而可以使用适当的湿蚀刻剂来蚀刻绝缘衬垫141的露出部分，而不会显著地蚀刻有机层171。在各个实施例中，抗蚀剂层171包括诸如光刻材料的材料或其他适当的材料(诸如底部抗反射涂层、低k电介质、极低k电介质或多孔绝缘材料)。
再次参照图1i，使用湿蚀刻工艺来蚀刻露出的绝缘衬垫141。在一个实施例中，使用包括缓冲型HF(NH4F:HF)的湿蚀刻化学剂来去除绝缘衬垫141。选择湿蚀刻化学剂，使得绝缘衬垫141被蚀刻而不去除抗蚀剂层171。
如图1k所示，随后去除抗蚀剂层171，以随后形成突起的第一部分161a和突起的第二部分161b。突起的第一部分161a包括绝缘衬垫141，因此形成受保护的TSV侧壁隔离物。受保护的TSV侧壁隔离物在实施例中的优点在于，防止导电填充材料145被未蚀刻的隔离衬垫141所氧化，由此消除了电流泄露的起因。还在随后的工艺期间使突起TSV 50与衬垫10的任何短路最少化。此外，利用蚀刻工艺精确地控制侧壁隔离物的厚度(突起的第一部分161a的高度)，以沉积抗蚀剂层171以及很好地表征抗蚀剂层171的蚀刻率。抗蚀剂层171的厚度主要确定侧壁隔离物的高度，并且确定蚀刻工艺被很好地控制。
转到图1l，可以在该步骤中切割衬底10，尽管在一些实施例中可选地在随后的阶段中切割衬底。例如，使用无电镍/金层或其他金属修整工艺，使突出TSV 50的突起的第二部分161b电镀有浸润层181。浸润层181没有形成在突起的第一部分161a的绝缘衬垫141上。因此，有利避免了浸润层181与衬底10的短路。浸润层181防止下层镍和导电填充材料145的氧化。镍在随后的焊接形成期间被用作润湿剂。因此，主要通过绝缘衬垫141或浸润层181来防止突出TSV 50被氧化。接下来，衬底10涂有下部填充层182。例如，下部填充层182可包括聚合物。存在多种相对于传热特性和机械特性具有不同特性的下部填充材料。所有下部填充材料都在这些实施例的范围内。
参照图1m，使用焊接回流工艺将管芯200结合至切割衬底190的TSV50。通过将管芯200的UMB结构155结合至衬底10的TSV 50的突出部分，焊球191将管芯200结合至衬底10。结合工艺可通过热、热超声加压等来实现。可利用本领域技术人员已知的工艺来进一步处理衬底，或者由此结束工艺。
图2(包括图2a至图2e)示出了根据本发明实施例的在制造期间包括衬底通孔的堆叠集成芯片。
参照图2a，如先前实施例所描述的，突出TSV 50通过首先利用绝缘衬垫141和导电沟槽衬垫142对开口进行加衬来形成并填充有导电填充材料145。
与前述实施例不同的是，衬底通孔仅延伸到第一金属层。例如，在一个实施例中，TSV 50还通过金属化层连接至有源晶体管。在完成最后的金属层之后，沉积钝化层111。
参照图2b，在钝化层111的上方沉积光刻胶，并进行图样化以形成用于导电焊盘的开口。然后，可以沉积和图样化聚酰亚胺材料156等，以形成UMB结构155。通过金属化层将TSV 50连接至UMB结构155。
接下来，参照图2c，翻转并减薄衬底10，以形成具有突起161的TSV50。例如，使用旋涂工艺来涂覆抗蚀剂层171。抗蚀剂层171形成薄层，并覆盖绝缘衬垫141和沟槽衬垫142的第一部分。将抗蚀剂层171的厚度控制为第二距离H。参照图2d，使用湿蚀刻工艺来蚀刻露出的绝缘衬垫141，使得绝缘衬垫141被蚀刻而不去除抗蚀剂层171。
接下来，参照图2e，去除抗蚀剂层171，以形成突起的第一部分161a和突起的第二部分161b。突起的第一部分161a包括绝缘衬垫141，因此形成受保护的TSV侧壁隔离物。衬底10涂有浸润层181，并使用焊球191焊接至管芯200。
虽然在该实施例中，TSV 50从衬底10的底面延伸到第一金属线层M1，但在其他实施例中，TSV 50可延伸到任何金属化层，或者可以仅延伸到衬底10的顶面。
图3(包括图3a和图3b)示出了使用本发明的实施例形成的堆叠衬底电路。参照图3a，堆叠集成芯片100包括第一芯片102、第二芯片104、第三芯片106、第四芯片108和第五芯片110。例如，第一、第二、第三、第四和第五芯片102、104、106、108和110可包括硅或其他半导体材料。此外，诸如第一芯片102的衬底可以由非半导体材料(诸如双马来酰亚胺三嗪(BT)等)组成。第一、第二、第三、第四和第五芯片102、104、106、108和110包括任何适当类型的芯片，包括存储器、逻辑电路、模拟电路或它们的组合。
第一、第二、第三、第四和第五芯片102～110可包括一个或多个导电层。例如，可以在芯片102～110内形成多个金属化层，并且第一、第二、第三、第四和第五芯片102～110可包括多个其他层，诸如多晶硅间氧化物(IPO)或金属间电介质(IMD)层(未示出)。第一、第二、第三、第四和第五芯片102～110还可以包括其他有源部件或电路。此外，堆叠集成芯片100可在其中包括附加芯片(也未示出)。
第一、第二、第三、第四和第五芯片102～110的任意一个或所有都可以包括TSV 50。TSV 50从衬底的第一侧突出。TSV 50提供衬底的第一侧和第二侧之间的电连接。第一、第二、第三、第四和第五芯片102～110中的至少一个TSV 50包括根据在图1和图2中描述的实施例形成的侧壁隔离物。
图3b示出了具有侧壁隔离物的第三芯片106。突出TSV 50包括突起161，该突起包括突起的第一部分161a和突起的第二部分161b。突起的第一部分161a包括绝缘衬垫141，因此形成受保护的TSV侧壁隔离物。突起的第二部分161b与浸润层181接触，并通过焊球191连接至第一芯片102。突起161封装在诸如聚合物材料层的下部填充层182中。
尽管详细描述了本发明及其优点，但应该理解，在不背离所附权利要求限定的本发明的精神和范围的情况下，可以做出各种改变、替换和变化。例如，本领域的技术人员应该理解，可以改变本文描述的许多部件、功能、工艺和材料，但都在本发明的范围之内。
此外，本发明的范围不用于限制在说明书中描述的工艺、机器、制造、物质组成、装置、方法和步骤的具体实施例。本领域的技术人员根据本发明的公开内容可容易理解，可以根据本公开利用现有或后来发展的执行基本上与本文中所描述的对应实施例相同的功能或者基本实现与本文所描述的对应实施例相同的结果的工艺、机器、制造和物质组成、装置、方法或步骤。因此，所附权利要求包括在其范围内，诸如工艺、机器、制造和物质组成、装置、方法或步骤。

Claims (15)

1.一种形成半导体芯片的方法，所述方法包括：
从第一衬底的顶面形成用于衬底通孔的开口；
用绝缘衬垫对所述开口的侧壁加衬；
用导电填充材料来填充所述开口；
从相对的底面开始蚀刻所述第一衬底以形成突起，所述突起被所述绝缘衬垫所覆盖；
在所述突起周围沉积抗蚀剂层，以露出所述绝缘衬垫的一部分；以及
蚀刻所露出的绝缘衬垫，以沿着所述突起形成侧壁隔离物。
2.根据权利要求1所述的方法，其中，所述抗蚀剂的厚度薄于所述突起的高度，以及其中，所述侧壁隔离物沿着所述突起的高度大约与所述抗蚀剂的厚度相同，
或者，其中，所述侧壁隔离物沿着所述突起的高度小于所述突起的高度。
3.根据权利要求1所述的方法，还包括：
在用所述导电填充材料填充所述开口之后，翻转所述衬底；以及
在蚀刻所露出的绝缘衬垫之后，去除所述抗蚀剂层。
4.根据权利要求1所述的方法，其中，所述第一衬底包括半导体晶片，所述半导体晶片包括在顶面上的有源电路，以及其中，所述开口从所述顶面延伸到所述第一衬底内设置的底面；和/或
所述绝缘衬垫包括从由二氧化硅、氮化硅、氮氧化硅、SiC、SiCN、低k介电材料、超低k介电材料及其组合所组成的组中选择的材料，其中，所述导电填充材料包括从由铜、铝、钨、银、金、掺杂多晶硅及其组合所组成的组中选择的材料，以及其中，所述抗蚀剂层包括光刻胶或抗反射涂层材料。
5.根据权利要求1所述的方法，其中，蚀刻所述绝缘衬垫包括：使用湿蚀刻化学剂来去除所述绝缘衬垫，而不去除所述抗蚀剂层。
6.根据权利要求1所述的方法，还包括：
在所述突起的所述导电填充材料上形成浸润层；以及
形成焊球结合点，以将所述第一衬底上的有源电路电连接至第二衬底上的有源电路，
其中，所述浸润层包括使用无电电镀工艺形成的镍/金层。
7.一种形成半导体芯片的方法，所述方法包括：
从第一衬底的顶部形成用于衬底通孔的开口；
用绝缘衬垫对所述开口的侧壁加衬；
用导电填充材料来填充所述开口；
从相对的底部开始蚀刻所述第一衬底，以露出在所述开口的侧壁上设置的绝缘衬垫的一部分；
从所述底部沉积抗蚀剂层，以露出所露出绝缘衬垫的区域；以及
蚀刻所露出绝缘衬垫的区域。
8.根据权利要求7所述的方法，还包括：
在蚀刻所露出绝缘衬垫的区域之后，去除所述抗蚀剂层；
从底部开始在所述导电填充材料上形成浸润层，其中，所述浸润层包括使用无电电镀工艺形成的镍/金层；以及
形成焊球结合点，以将所述第一衬底上的有源电路电连接至第二衬底上的有源电路。
9.根据权利要求7所述的方法，其中，所述开口从所述顶部延伸到所述第一衬底内设置的底面；和/或
所述绝缘衬垫包括从由二氧化硅、氮化硅、氮氧化硅、SiC、SiCN、低k介电材料、超低k介电材料及其组合所组成的组中选择的材料，其中，所述导电填充材料包括从由铜、铝、钨、银、金、掺杂多晶硅及其组合所组成的组中选择的材料，以及其中，所述抗蚀剂层包括光刻胶或抗反射涂层材料。
10.根据权利要求7所述的方法，其中，蚀刻所露出绝缘衬垫的区域包括：使用湿蚀刻化学剂来去除所述绝缘衬垫，而不去除所述抗蚀剂。
11.一种形成半导体芯片的方法，所述方法包括：
从第一衬底的顶面形成用于衬底通孔的开口；
用绝缘衬垫对所述开口的侧壁加衬；
用导电填充材料来填充所述开口；
从相对的底面开始蚀刻所述第一衬底以露出所述绝缘衬垫的一部分；以及
通过使用湿蚀刻工艺去除所述绝缘衬垫的露出部分的剩余部分，在所述绝缘衬垫的露出部分的第一部分上的所述导电填充材料上形成侧壁隔离物。
12.根据权利要求11所述的方法，还包括：在去除所述绝缘衬垫的露出部分的剩余部分之后，去除所述抗蚀剂层。
13.根据权利要求11所述的方法，还包括：
在与所述侧壁隔离物相邻的所述导电填充材料上形成浸润层，其中，所述浸润层包括形成使用无电电镀工艺而形成的镍/金层；以及
形成焊球结合点，以将所述第一衬底上的有源电路电连接至第二衬底上的有源电路。
14.根据权利要求11所述的方法，其中，所述开口从所述顶面延伸到所述第一衬底内设置的底面；和/或
所述绝缘衬垫包括从由二氧化硅、氮化硅、氮氧化硅、SiC、SiCN、低k介电材料、超低k介电材料及其组合所组成的组中选择的材料，其中，所述导电填充材料包括从由铜、铝、钨、银、金、掺杂多晶硅及其组合所组成的组中选择的材料，以及其中，所述抗蚀剂层包括光刻胶或抗反射涂层材料。
15.根据权利要求11所述的方法，其中，蚀刻所露出绝缘衬垫的区域包括：使用湿蚀刻化学剂来去除所述绝缘衬垫，而不去除所述抗蚀剂。
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