CN106816426A - 集成芯片及其制造方法 - Google Patents

集成芯片及其制造方法 Download PDF

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Publication number
CN106816426A
CN106816426A CN201610656949.6A CN201610656949A CN106816426A CN 106816426 A CN106816426 A CN 106816426A CN 201610656949 A CN201610656949 A CN 201610656949A CN 106816426 A CN106816426 A CN 106816426A
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China
Prior art keywords
back side
layer
welding pad
substrate
metal interconnecting
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CN201610656949.6A
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English (en)
Inventor
高敏峰
杨敦年
黄薰莹
刘人诚
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN106816426A publication Critical patent/CN106816426A/zh
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Abstract

本发明涉及集成芯片及其制造方法。集成芯片具有在金属互连层与背面导电焊垫之间的直接物理性连接的背面贯穿基底导通孔。集成芯片具有多个金属互连层设置于基底正面上的层间介电结构中，介电层沿基底背面设置，且导电焊垫设置于介电层之上，背面贯穿基底导通孔从多个金属互连层中的一个延伸穿过基底及介电层至导电焊垫，导电凸块设置于导电焊垫上，导电焊垫具有平坦的下表面从背面贯穿基底导通孔之上延伸至导电凸块之下，直接连接导电焊垫至背面贯穿基底导通孔降低了导电焊垫的尺寸，借此提升导电焊垫的绕线能力。

Description

集成芯片及其制造方法
技术领域
本发明涉及集成芯片，且特别涉及具有背面贯穿基底导通孔(BTSV)的集成芯片及其制造方法。
背景技术
近代的集成芯片包含数百万或数十亿的半导体装置设置于半导体基底(例如硅晶圆)中。半导体装置连接至覆盖在其上的包含多个金属互连层(例如导线及导通孔)的后段制程(back-end-of-the-line,BEOL)金属化堆叠。这些金属互连层将半导体装置彼此电性连接且电性连接至外部构件。金属互连层通常终止在位于后段制程金属化堆叠之上的焊垫。此焊垫可包含一层厚金属层，此厚金属层提供从集成芯片至外部构件(例如集成芯片封装)的导电连接。
发明内容
本发明的目的在于，提供一种具有背面贯穿基底导通孔(BTSV)的集成芯片及其制造方法。
在一些实施例中，本发明涉及集成芯片，集成芯片包括：
多个金属互连层，设置于沿一基底的一正面设置的一层间介电结构中；
一介电层，沿该基底的一背面设置；
一导电焊垫，设置于该介电层之上；
一背面贯穿基底导通孔，从多个所述金属互连层中的一个延伸穿过该基底及该介电层至该导电焊垫；以及
一导电凸块，设置于该导电焊垫之上，其中该导电焊垫具有一平坦的下表面从该背面贯穿基底导通孔之上延伸至该导电凸块之下。
在其他一些实施例中，所述的集成芯片还包括：
一高介电常数介电层，配置来降低该基底的该背面的粗糙度，其中该高介电常数介电层系纵向地设置于该介电层与该基底之间。
在其他一些实施例中，其中该高介电常数介电层具有一厚度范围介于10埃与1000埃之间。
在其他一些实施例中，其中该背面贯穿基底导通孔具有多个平滑的侧壁连续地延伸于多个所述金属互连层中的一个与该导电焊垫之间。
在其他一些实施例中，其中多个所述金属互连层包括一较薄的第一金属互连线及通过该第一金属互连线与该基底分开的一较厚的第二金属互连线，且其中该背面贯穿基底导通孔接触该第一金属互连线。
在其他一些实施例中，所述的集成芯片，还包括：
一保护层，设置于该介电层及该导电焊垫之上；以及
一凸块下金属层，从该保护层之上延伸至该保护层中的一开口内，其中该凸块下金属层系位于该导电焊垫与该导电凸块之间。
在其他一些实施例中，其中该导电焊垫具有以一第一方向延伸的一第一段及以垂直于该第一方向的一第二方向延伸的一第二段。
在其他一些实施例中，其中该背面贯穿基底导通孔接触该导电焊垫的该第一段，且该凸块下金属层接触该导电焊垫的该第二段。
在其他一些实施例中，所述的集成芯片还包括：
一背面贯穿基底导通孔衬垫，沿该背面贯穿基底导通孔的侧壁设置，以分开该背面贯穿基底导通孔与该基底。
在其他一些实施例中，所述的集成芯片还包括：
一或多个额外背面贯穿基底导通孔，设置为平行于该背面贯穿基底导通孔，该背面贯穿基底导通孔介于多个所述金属互连层中的一个与该导电焊垫之间。
在其他一些实施例中，所述的集成芯片还包括：
一缓冲层通过该介电层，与该基底分开，其中该背面贯穿基底导通孔具有背对该基底的一上表面，且该上表面与该介电层的背对该基底的一上表面或该缓冲层的背对该基底的一上表面共平面。
在一些实施例中，本发明涉及集成芯片，集成芯片包括：
多个金属互连层，设置于沿一基底的一正面设置的一层间介电结构中，其中多个所述金属互连层包括一较薄的第一金属互连线及通过该第一金属互连线与该基底分开的一较厚的第二金属互连线；
一高介电常数介电层，设置于该基底的背面上；
一介电层，通过该高介电常数介电层与该基底的该背面分开；
一导电焊垫，设置于该介电层之上；以及
一背面贯穿基底导通孔，延伸于该第一金属互连线与该导电焊垫之间。
在其他一些实施例中，所述的集成芯片还包括：
一保护层，设置于该介电层与该导电焊垫之上；
一凸块下金属层，从该保护层之上延伸至该保护层中的一开口内；以及
一导电凸块，设置于该凸块下金属层之上，其中该导电焊垫具有一平坦的下表面从该背面贯穿基底导通孔之上延伸至该导电凸块之下。
在其他一些实施例中，其中该背面贯穿基底导通孔具有多个锥形的侧壁，连续地延伸于该第一金属互连线与该导电焊垫之间。
在其他一些实施例中，其中该背面贯穿基底导通孔具有多个平滑的侧壁连续地延伸于该第一金属互连线与该导电焊垫之间。
在其他一些实施例中，其中该导电焊垫具有以一第一方向延伸的一第一段及以垂直于该第一方向的一第二方向延伸的一第二段。
在其他一些实施例中，其中该导电焊垫包括铝。
在其他一些实施例中，其中该背面贯穿基底导通孔包括铜、铝或钨。
在其他一些实施例中，其中该背面贯穿基底导通孔具有小于或等于2.5微米的宽度。
在一些实施例中，本发明涉及集成芯片的制造方法，集成芯片的制造方法，包括以下步骤：
形成多个金属互连层，在沿一基底的一正面设置的一层间介电结构中，其中多个所述金属互连层包括一第一金属互连线及通过该第一金属互连线与该基底分开的一更厚的第二金属互连线；
形成一高介电常数介电层于该基底之一背面上；
形成一介电层于该高介电常数介电层之上；
蚀刻该介电层、该高介电常数介电层、该基底及该层间介电结构，以形成一背面贯穿基底导通孔开口延伸至与该第一金属互连线接触的一位置；
沉积一导电材料于该背面贯穿基底导通孔开口之中；
实施一平坦化制程移除该背面贯穿基底导通孔开口外的该导电材料，以形成一背面贯穿基底导通孔；以及
形成一导电焊垫，具有一平坦下表面设置于该背面贯穿基底导通孔上。
本发明的功效在于，直接连接导电焊垫至背面贯穿基底导通孔降低了导电焊垫的尺寸，借此提升导电焊垫的绕线能力。
附图说明
根据以下的详细说明并配合所附附图做完整公开。应注意的是，根据本产业的一般作业，附图中的各种特征部件并未必按照比例绘制。事实上，可能任意的放大或缩小各种特征部件的尺寸，以做清楚的说明。
图1是根据一些实施例绘示具有背面焊垫的集成芯片。
图2是根据一些其它的实施例绘示具有背面焊垫的集成芯片。
图3是根据一些实施例绘示导电焊垫连接至背面贯穿基底导通孔的俯视图。
图4是根据一些实施例绘示具有背面焊垫的三维集成芯片(three-dimensionalintegrated chip,3DIC)。
图5-15是根据一些实施例显示制造具有背面焊垫的集成芯片的方法的剖面图。
图16是根据一些实施例制造具有背面焊垫的集成芯片的方法的流程图。
其中，附图标记说明如下：
100、200、400～集成芯片；
102、502～半导体基底；
102b、502b～半导体基底的背面；
102f、502f～半导体基底的正面；
104～半导体元件；
104g～栅极电极层；
104e～栅极介电层；
104s～源极区；
104d～漏极区；
106～金属互连层；
107a、107b、107c、407、407a、407a'、407b、407b'、407c、407c'～金属线；
108、410a、410b～层间介电结构；
108a、108b、108c、108d～层间介电层；
109a～接触孔；
109b、109c～金属导通孔；
110～背面贯穿基底导通孔；
112～导电焊垫；
112b～导电焊垫的背面；
112f～导电焊垫的正面；
114、204～介电层；
116、210、212～保护层；
118～凸块下金属层；
118a、118b～金属层；
120～导电凸块；
202～高介电常数介电层；
206～缓冲层；
208、1002～背面贯穿基底导通孔衬垫；
302～第一方向；
304～第二方向；
402a～第一半导体芯片；
402b～第二半导体芯片；
404～粘着层；
405～隔离结构；
406a～第一半导体基底；
406b～第二半导体基底；
408a、408b～金属互连层；
409、409a、409a'、409b、409b'、409c、409c'～接触孔/导通孔；
412～贯穿介电导通孔；
902～背面贯穿基底导通孔的开口；
904～蚀刻剂；
906～遮罩层；
1004～导电材料；
1102～线段；
1104～平坦表面；
1302～凸块下金属层的开口；
300～俯视图；
500、600、700、800、900、1000、1100、1200、1300、1400、1500～剖面图；
1600～方法；
1602、1604、1606、1608、1610、1612、1614、1616、1618、1620、1622、1624、1626～动作；
wPad、wBTSV～宽度；
t、t1、t2～厚度。
具体实施方式
本说明书以下的公开内容提供许多不同的实施例或范例，以实施本发明的不同特征。而本说明书以下的公开内容是叙述各个构件及其排列方式的特定范例，以求简化发明的说明。当然，这些特定的范例并非用以限定本发明。例如，本说明书以下的公开内容叙述了将一第一特征部件形成于一第二特征部件之上或上方，即表示其包含了所形成的上述第一特征部件与上述第二特征部件是直接接触的实施例，亦包含了尚可将附加的特征部件形成于上述第一特征部件与上述第二特征部件之间，而使上述第一特征部件与上述第二特征部件可能未直接接触的实施例。另外，本发明的说明中不同范例可能使用重复的参考符号及/或用字。这些重复符号或用字是为了简化与清晰的目的，并非用以限定各个实施例及/或所述外观结构之间的关系。
再者，为了方便描述附图中一元件或特征部件与另一(多)元件或(多)特征部件的关系，可使用空间相关用语，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及类似的用语。除了附图所绘示的方位之外，空间相关用语涵盖使用或操作中的装置的不同方位。所述装置也可被另外定位(例如旋转90度或者位于其他方位)，并对应地解读所使用的空间相关用语的描述。
集成芯片(integrated chip,IC)中的半导体装置是通过包含多个金属互连层(例如导线及导通孔)的后段制程(back-end-of-the-line,BEOL)金属化堆叠的方式连接至外部电路(例如封装基底)。金属互连层的尺寸通常随着离半导体基底的距离的增加而增加，例如具有相对小尺寸区域互连线耦合半导体基底中的半导体装置至较大的互连线。较大的互连线还进一步耦合至沿后段制程(BEOL)金属化堆叠上表面设置的导电焊垫，后段制程(BEOL)金属化堆叠连接集成芯片至外部电路。
导电焊垫以覆晶(flip-chip)封装方式愈来愈紧密地连接至外部电路，覆晶封装使用锡焊凸块(solder bump)建立导电焊垫与封装基底(例如印刷电路板)之间的直接电性接触。具有覆晶封装的集成芯片包含的保护层包括多个开口延伸至底下的最终(例如顶部)金属互连层。重布线层(redistribution layer,RDL)设置于保护层上，重布线层可包含垂直构件(例如重布线导通孔(redistribution via,RV))从最终金属互连层延伸穿过保护层中的开口至侧向构件，侧向构件从最终金属互连层重新分布电性信号至覆盖保护层上的聚酰亚胺垫(polyimide pad)的导电焊垫，借此使得不同封装选择能相容。凸块下金属层(under bump metallurgy,UBM)设置于导电焊垫上，且作为于导电焊垫及锡焊凸块间的可焊性(solderable)介面。当重布线层使得各种不同的焊垫配置可行时，大尺寸的重布线导通孔(例如大于3um)会造成大的导电焊垫有受到限制的绕线能力(routing ability)。
本发明涉及具有背面贯穿基底导通孔的集成芯片及其制造方法，在金属互连层与背面导电焊垫之间有直接物理性连接。在一些实施例中，集成芯片具有多个金属互连层设置于沿基底的正面设置的层间介电结构中，介电层沿基底的背面设置，且导电焊垫设置于介电层之上，背面贯穿基底导通孔(back-side through-substrate-via,BTSV)从这些金属互连层中的一个延伸穿过基底及介电层至导电焊垫，导电凸块设置于导电焊垫上，导电焊垫具有大抵平坦的下表面从背面贯基底导通孔之上延伸至导电凸块之下。通过使用导电焊垫直接连接至背面贯穿基底导通孔，导电焊垫的尺寸可降低，借此提升导电焊垫的绕线能力(routing capability)。
图1是根据一些实施例绘示具有背面焊垫的集成芯片100。
集成芯片100包括具有正面102f和背面102b的半导体基底102，多个半导体元件104(例如晶体管元件)沿半导体基底102的正面102f设置。后段制程(back-end-of-the-line,BEOL)金属化堆叠设置于半导体基底102的正面102f之上，且包括多个金属互连层106设置于层间介电(inter-level dielectric,ILD)结构108中，这些金属互连层106电性耦合至这些半导体元件104，且可随着离半导体基底102的正面102f的距离的增加而增加尺寸(例如从薄的M1层至较厚的Mx层，其中x>1)。
导电焊垫112沿半导体基底102的背面102b设置，导电焊垫112具有正面112f面对半导体基底102及背面112b背对半导体基底102。导电焊垫112的正面112f通过一或多层介电层114与半导体基底102分开，且导电焊垫112的正面112f可包括平坦表面沿着与一或多层介电层114的介面延伸。
背面贯穿基底导通孔(BTSV)110延伸穿过半导体基底102，从在后段制程金属化堆叠中的金属互连层106至导电焊垫112的正面112f，背面贯穿基底导通孔110从半导体基底102的背面102b向外突出穿过一或多层的介电层114。背面贯穿基底导通孔110具有相对小的尺寸(例如小于或等于大约2.5um)，使背面贯穿基底导通孔110连接至设置于后段制程金属化堆叠的顶端金属互连层(例如距离半导体基底102最远的一层)下方的薄金属互连层。
导电焊垫112的背面112b被保护层116覆盖，凸块下金属(UBM)层118延伸穿过保护层116中的开口以接触导电焊垫112的背面112b。在一些实施例中，凸块下金属层118也可沿保护层116的上表面延伸。导电凸块120设置于凸块下金属层118中，且位于通过凸块下金属层118与保护层116分开的位置。导电凸块120配置为提供半导体元件104与外部元件(例如印刷电路板(PCB)、其他集成芯片等等)之间的电性连接。在一些实施例中，凸块下金属层118设置于导电焊垫112之上，且位于从背面贯穿基底导通孔110侧向偏移的位置。
通过直接连接背面贯穿基底导通孔110于金属互连层106与导电焊垫112的正面112f之间，导电焊垫112的宽度可降低(例如由于未使用重布线层)。降低导电焊垫112的宽度可增加导电焊垫112的绕线的灵活度，且提升效能(例如由于半导体元件104与导电焊垫112之间较短的路径)。
图2是根据一些其它的实施例绘示具有背面焊垫的集成芯片200。
集成芯片200包括半导体基底102及覆盖在上面的后段制程金属化堆叠。在一些实施例中，半导体基底102具有介于大约1um与大约10um之间的厚度t，多个半导体元件104可设置于半导体基底102的正面102f中。
后段制程金属化堆叠包括多个金属互连层设置于层间介电(ILD)结构108中。在一些实施例中，这些金属互连层可包括多个金属线107a-107c设置于多个接触孔109a及/或金属导通孔109b-109c之间。这些金属互连线可增加尺寸，从薄的第一金属线107a至厚的金属线107b及/或107c，厚的金属线107b及/或107c通过薄的第一金属线107a与半导体基底102分开。在一些实施例中，第一金属线107a可具有小于大约70nm的厚度。在其他一些实施例中，第一金属线107a可具有小于大约30nm的厚度。在各种实施例中，这些金属互连层可包括导电材料，例如铜、铝、钨或前述的组合。在各种实施例中，层间介电结构108可包括氧化物、超低介电常数(ultra-low k)的介电材料或低介电常数(low-k)的介电材料(例如碳氧化硅(SiCO))中的一或多个。
高介电常数(high-k)介电层202设置于半导体基底102的背面102b上，高介电常数介电层202配置用来降低于制程中被薄化后的半导体基底102的背面102b的粗糙度，通过降低半导体基底102的背面102b的粗糙度，可降低装置漏电(leakage)。高介电常数介电层202面对半导体基底102的面比背对半导体基底102的相反面较为粗糙(例如在垂直的位置具有较大的变异)。在各种实施例中，高介电常数介电层202可包括一或多层。在一些实施例中，高介电常数介电层202具有范围介于大约与大约之间的厚度t2。在一些实施例中，高介电常数介电层202可包括例如氧化铝(Al2O3)、五氧化二钽(Ta2O5)、二氧化钛(TiO2)、二氧化锆(ZrO2)、氧化铪(HfO)、氧化硅铪(HfSiO)、氧化铝铪(HfAlO)及/或氧化钽铪(HfTaO)。
介电层204设置于高介电常数介电层202之上。在各种实施例中，介电层204可包括氧化物(例如二氧化硅(SiO2))。在一些实施例中，缓冲层206可设置于介电层204之上，缓冲层206可包括氮化物(例如SiN、Si3N4)。导电焊垫112设置于介电层204及/或缓冲层206之上，导电焊垫112包括平坦结构沿介电层204及/或缓冲层206的上表面设置。在一些实施例中，导电焊垫112可包括例如铝。
背面贯穿基底导通孔110从后段制程金属化堆叠延伸，穿过半导体基底102、高介电常数介电层202、介电层204及缓冲层206至导电焊垫112的正面112f。在一些实施例中，背面贯穿基底导通孔110可连接于导电焊垫112与薄的第一金属线107a(例如最靠近半导体基底102的正面102f的M1层)之间。在一些实施例中，背面贯穿基底导通孔110可具有与介电层204或缓冲层206的上表面共平面的上表面。在一些实施例中，背面贯穿基底导通孔110可具有锥形的侧壁(tapered sidewalls)延伸于薄的第一金属线107a与导电焊垫112之间。在一些实施例中，锥形的侧壁具有平滑的表面(例如具有固定的斜率)在半导体基底102与高介电常数介电层202之间转变。锥形的侧壁使得背面贯穿基底导通孔110的宽度从半导体基底102的正面102f开始增加至半导体基底102的背面102b。在各种实施例中，背面贯穿基底导通孔110可包括铜、铝、钨或相似的材料。
在一些实施例中，背面贯穿基底导通孔衬垫(BTSV liner)208沿背面贯穿基底导通孔110的侧壁设置。背面贯穿基底导通孔衬垫208将背面贯穿基底导通孔110与半导体基底102分开。在各种实施例中，背面贯穿基底导通孔衬垫208可包括例如氧化物或氮化硅。在一些实施例中，背面贯穿基底导通孔衬垫208也可沿高介电常数介电层202、介电层204及缓冲层206的侧壁延伸。
一或多个保护层210及212(passivation layer)可设置于导电焊垫112之上，一或多个保护层210及212延伸于导电焊垫112之上且沿着导电焊垫112之侧壁。在一些实施例中，保护层210及212可包括介电层(又称保护层210)及聚酰亚胺(polyimide)层(又称保护层212)。凸块下金属层118系设置于导电焊垫112的上表面上，且内衬于聚酰亚胺层(又称保护层212)中的开口内部。凸块下金属层118可包括不同金属层118a和118b的堆叠作为扩散层(diffusion layer)、阻障层(barrier layer)、润湿层(wetting layer)及/或抗氧化层(anti-oxidation layer)。在一些实施例中，凸块下金属层118可包括铜、铜合金、铝、铝合金或类似的材料。在各种实施例中，导电焊垫112具有平坦下表面邻接介电层204及/或缓冲层206，且介于背面贯穿基底导通孔110与凸块下金属层118之间。在一些实施例中，凸块下金属层118可更进一步沿聚酰亚胺层(又称保护层212)之上表面延伸。
导电凸块120设置于凸块下金属层118上。在一些实施例中，导电凸块120为焊料凸块、铜凸块、包含镍(Ni)或金(Au)的金属凸块或前述的组合。在一些实施例中，导电凸块120为焊料凸块，通过放置焊球于凸块下金属层118上且回焊(reflowing)焊球来形成。在一些实施例中，焊料凸块包含无铅(lead-free)预焊(pre-solder)层、锡银(SnAg)或包含锡、铅、银、铜、镍、铋的合金的焊接材料或前述的组合。
图3是根据一些实施例绘示背面贯穿基底导通孔直接接触导电焊垫的俯视图300。
如俯视图300所示，背面贯穿基底导通孔110接触导电焊垫112的第一端点。在一些实施例中，背面贯穿基底导通孔110可包具有圆形的剖面。在其他一些实施例中，背面贯穿基底导通孔110可具有其他形状的剖面，凸块下金属层118接触导电焊垫112的第二端点，且位于从背面贯穿基底导通孔110侧向偏移的位置。在一些实施例中，背面贯穿基底导通孔110可具有宽度wBTSV范围从大约0.3um至大约5um。
在一些实施例中，背面贯穿基底导通孔110被导电焊垫112覆盖，由于背面贯穿基底导通孔110被导电焊垫112覆盖，背面贯穿基底导通孔110的尺寸可影响导电焊垫112的尺寸，例如在一些这样的实施例中，背面贯穿基底导通孔110可具有宽度wBTSV小于或等于大约1.5um，且导电焊垫112可具有宽度wPad小于或等于大约2.5um。在其他一些这样的实施例中，背面贯穿基底导通孔110可具有宽度wBTSV小于或等于大约1um，且导电焊垫112可具有宽度wPad小于或等于大约2.0um。在这样的实施例中，具有宽度wBTSV小于大约2.5um的背面贯穿基底导通孔110产生相对小的导电焊垫宽度wPad，其提供导电焊垫绕线的设计自由度及空间。
在一些实施例中，导电焊垫112可在多个方向延伸，例如导电焊垫112可在第一方向302和垂直于第一方向302的第二方向304延伸。在一些这样的实施例中，背面贯穿基底导通孔110可接触导电焊垫112在第一方向302延伸的一段，而凸块下金属层118可接触导电焊垫112在第二方向304延伸的一段。在其他一些这样的实施例中，背面贯穿基底导通孔110及凸块下金属层118可接触导电焊垫112在第一方向302延伸的多个段，这些段通过导电焊垫112在第二方向304延伸的一或多段分开。
图4是根据一些其它实施例绘示具有背面焊垫的三维集成芯片(three-dimensional integrated chip,3DIC)400。
三维集成芯片(3D-IC)400包括第一半导体芯片(die)402a，其是以设置粘着层404于两者之间的方法耦合，耦合至第二半导体芯片402b。第一半导体芯片402a包括具有多个半导体元件104的第一半导体基底406a。在一些实施例中，这些半导体元件104可通过隔离结构405(例如浅沟槽隔离结构(shallow trench isolation structure))分开。多个第一金属互连层408a设置于第一层间介电结构410a中，其包括一或多个层间介电层披覆于第一半导体芯片402a上。第二半导体芯片402b包括第二半导体基底406b及多个第二金属互连层408b设置于包括一或多个层间介电层的第二层间介电结构410b中。在一些实施例中，粘着层404包括氧化层，使得第一半导体芯片402a沿氧化层间的介面连接至第二半导体芯片402b。
这些金属互连层408a、408b包括金属线407及金属接触及/或导通孔409(包括接触孔及/或导通孔409a、409a'、409b、409b'、409c及409c')。这些第一金属互连层408a包括薄金属线407a及具有比薄金属线407a更大尺寸(例如宽度及/或高度)的厚金属线407b。厚金属线407b通过一或多个薄金属线407a与第一半导体基底406a分开。这些第二金属互连层408b也包括薄金属线407a’及具有比薄金属线407a’更大尺寸的厚金属线407b’。厚金属线407b’通过一或多个薄金属线407a’与第二半导体基底406b分开。
贯穿介电导通孔(through dielectric via,TDV)412从这些第一金属互连层408a延伸穿过第一半导体基底406a及粘着层404至这些第二金属互连层408b中的一个。在一些实施例中，贯穿介电导通孔(TDV)412连接这些第一金属互连层408a中的厚金属线407b至这些第二金属互连层408b中的厚金属线407c’。
背面贯穿基底导通孔110连接至这些第二金属互连层408b的薄金属线407a’(例如薄金属线407a’设置于厚金属线407b’与第二半导体基底406b之间)。背面贯穿基底导通孔110延伸穿过第二半导体基底406b至沿第二半导体基底406b的背面设置的平坦导电焊垫112。平坦导电焊垫112还进一步连接至与导电凸块120连接的凸块下金属层118。在一些实施例中，一个以上的背面贯穿基底导通孔110可平行连接于薄金属线407a’与导电焊垫112之间。
图5-15是根据一些实施例显示制造具有背面焊垫的集成芯片的方法的剖面图500-1500。
如剖面图500所示，提供半导体基底502。半导体基底502可为任何类型的半导体主体(包括硅、硅锗(SiGe)、绝缘层上覆硅(SOI))，例如半导体晶圆及/或一或多个晶片于晶圆上，和任何其他类型的金属层、元件、半导体及/或磊晶层等等与其结合。半导体基底502可包括具有第一掺杂类型(例如n型掺杂或p型掺杂)的本质掺杂的半导体基底。
多个半导体元件104(例如晶体管元件)沿半导体基底502的正面502f形成。在一些实施例中，这些半导电元件104通过形成栅极结构于半导体基底502之上而形成。栅极结构可通过形成栅极介电层104e于半导体基底502上，且接续地形成栅极电极层104g于栅极介电层104e之上而形成。栅极介电层104e及栅极电极层104g依照光微影(photolithography)制程接续地图案化以形成栅极结构。源极区104s与漏极区104d可通过磊晶制程或通过布植(implantation)制程选择性地植入掺杂物质，例如硼(B)或磷(P)至半导体基底502而形成，掺杂物质可接续地通过高温热退火(thermal anneal)驱动进入半导体基底502中。
如剖面图600所示，后段制程金属化堆叠形成于半导体基底502的正面502f之上。后段制程金属化堆叠包括多个金属互连层106形成在位于半导体基底502的正面502f之上的层间介电结构108中，且这些金属互连层106连接至这些半导体元件104。
在一些实施例中，后段制程金属化堆叠通过使用分别的沉积制程沉积独立的层间介电层108a-108d而形成。在沉积后，在这些独立的层间介电层108a-108d中的一个中蚀刻出导通孔洞及/或金属沟槽。导电材料(例如铜、钨及/或铝)沉积于导通孔洞及/或金属沟槽中，以形成金属互连层106。在一些实施例中，可使用沉积制程在导通孔洞中形成晶种层，接着进行后续的电镀制程(例如电镀或无电电镀(electroless plating)制程)，其形成金属材料至填满导通孔洞及/或金属沟槽的厚度。在一些实施例中，可使用化学机械研磨(chemical mechanical polishing,CMP)制程从独立的层间介电层108a-108d的顶表面移除多余的金属材料。在各种实施例中，这些金属互连层可通过双镶嵌(dual damascene)制程(已绘示)或单镶嵌(single damascene)制程(未绘示)形成。
如剖面图700所示，降低半导体基底502的厚度，降低半导体基底502的厚度可让后续形成的背面贯穿基底导通孔(例如形成于图9-11)具有较小的尺寸(例如小于或等于大约2.5um)，其可以减少导电焊垫的尺寸。在一些实施例中，在薄化半导体基底502之前，层间介电结构108可通过粘着材料连接至承载基底(未绘示)，承载基底于薄化及接续的制程中提供支撑。半导体基底502可通过蚀刻制程及/或机械研磨半导体基底502的背面502b来薄化。在一些实施例中，基底的厚度从大约700um的第一厚度t1降低至范围介于大约1um与10um之间的第二厚度t2。
如剖面图800所示，高介电常数介电层202形成于半导体基底102的背面102b之上。在各种实施例中，高介电常数介电层202可包括例如氧化铝(Al2O3)、五氧化二钽(Ta2O5)、二氧化钛(TiO2)、二氧化锆(ZrO2)及/或氧化铪(HfO)。在各种实施例中，高介电常数介电层202可通过沉积制程(例如化学气相沉积(CVD)制程、电浆辅助化学气相沈积(PECVD)制程、原子层沉积(ALD)制程、物理气相沉积(PVD)制程等)形成。高介电常数介电层202降低了半导体基底102的背面102b的粗糙度，借此可改善装置漏电。
介电层204及/或缓冲层206系接续地形成于高介电常数介电层202之上。在一些实施例中，介电层204可包括氧化层，缓冲层206可包括氮化层。介电层204及/或缓冲层206可通过沉积制程(例如CVD、PE-CVD、ALD、PVD等)形成。
如剖面图900所示，形成背面贯穿基底导通孔的开口902。背面贯穿基底导通孔的开口902垂直地延伸穿过介电层204及/或缓冲层206、高介电常数介电层202、半导体基底102及部分的层间介电结构108至接触这些金属互连层106的薄的第一金属线107a的位置。在一些实施例中，背面贯穿基底导通孔的开口902可根据遮罩层906选择性地暴露基底于蚀刻剂904中而形成。在各种实施例中，遮罩层906可包括光阻或氮化物(例如Si3N4、SiN)，其使用光微影制程图案化。在各种实施例中，蚀刻剂904可包括具有蚀刻化学性的干蚀刻剂包括氟物质(例如四氟化碳(CF4)、三氟甲烷(CHF3)、八氟环丁烷(C4F8)等等)或湿蚀刻剂(例如氢氟酸(hydrofluoric acid,HF)或四甲基氢氧化铵(tetramethylammonium hydroxide,TMAH))。
如剖面图1000所示，形成背面贯穿基底导通孔衬垫1002于背面贯穿基底导通孔的开口902中。背面贯穿基底导通孔衬垫1002沿背面贯穿基底导通孔的开口902的下表面及侧壁延伸。在一些实施例中，背面贯穿基底导通孔衬垫1002可被局限于背面贯穿基底导通孔的开口902中，而在其他一些实施例中，背面贯穿基底导通孔衬垫1002可从背面贯穿基底导通孔的开口902向外延伸至介电层204及/或缓冲层206之上。在一些实施例中，背面贯穿基底导通孔衬垫1002可通过沉积制程(例如CVD、PE-CVD、ALD、PVD等等)形成。在其他一些实施例中，背面贯穿基底导通孔衬垫1002可通过热氧化(thermal oxidation)制程形成。在这样的实施例中，背面贯穿基底导通孔衬垫1002可不延伸于介电层204及/或缓冲层206之上(亦即背面贯穿基底导通孔衬垫208的上表面在介电层204及/或缓冲层206的上表面之下)。在一些实施例中，背面贯穿基底导通孔衬垫1002可包括氧化物(例如二氧化硅(SiO2)。
背面贯穿基底导通孔的开口902接着以导电材料1004填充。在各种实施例中，导电材料1004可包括铜、铝、钨或相似的材料。在一些实施例中，导电材料1004可通过沉积制程形成。在一些其它的实施例中，导电材料1004可通过电镀制程(例如电镀及无电电镀制程)形成。导电材料1004填满背面贯穿基底导通孔的开口902且延伸于介电层204及/或缓冲层206的上表面之上。
如剖面图1100所示，沿线段1102实施平坦化制程以移除导电材料(例如图10的1004)及/或覆盖于介电层204及/或缓冲层206上的背面贯穿基底导通孔衬垫(例如图10的1002)。平坦化制程形成了平坦表面1104沿背面贯穿基底导通孔110和介电层204及/或缓冲层206延伸，平坦化制程将背面贯穿基底导通孔110及/或背面贯穿基底导通孔衬垫208局限于背面贯穿基底导通孔的开口902中。在一些实施例中，平坦化制程可包括化学机械研磨(CMP)制程。在其他一些实施例中，平坦化制程可包括例如蚀刻制程及/或研磨制程。
如剖面图1200所示，导电焊垫112形成于平坦表面1104上，导电焊垫112直接形成与背面贯穿基底导通孔110接触，使得背面贯穿基底导通孔110物理性且电性地接触导电焊垫112。导电焊垫112可通过沉积制程及/或电镀制程，且接着进行光微影(lithographic)图案化及蚀刻制程形成。
如剖面图1300所示，形成一或多个保护层210及212于导电焊垫112之上，此一或多个保护层210及212从导电焊垫112之上延伸至介电层204及/或缓冲层206之上。在一些实施例中，此一或多个保护层210及212可包括介电层(又称保护层)及聚酰亚胺层(又称保护层)，此一或多个保护层210及212可通过沉积制程形成，接着进行图案化制程形成凸块下金属层的开口1302延伸穿过此一或多个保护层210及212至导电焊垫112的背面112b。
如剖面图1400所示，凸块下金属层118形成于凸块下金属层的开口1302内。凸块下金属层118为不同金属层118a及118b的堆叠，其作为扩散层、阻障层、润湿层及/或抗氧化层。凸块下金属层118可通过连续的沉积制程形成。
如剖面图1500所示，导电凸块120形成于凸块下金属层118上。在各种实施例中，导电凸块120可包括焊料凸块、铜凸块、包含镍(Ni)或金(Au)的金属凸块或前述的组合。在一些实施例中，集成芯片可被带入接触基底(例如印刷电路板(PCB))或封装的导线架(leadframe)，接着焊球被回焊以形成与基底或导线架的电性连接。在集成芯片电性连接至基底或导线架之后，可移除承载基底及粘着层。
图16是根据一些实施例制造具有背面焊垫的集成芯片的方法的流程图。虽然方法1600的描述与图5至15有关，应当理解的是，方法1600并不限定于这种结构，且可单独视为独立于结构的方法。
所公开的方法1600在下文中描述为一系列步骤或事件，应可理解的是，这些步骤或事件的顺序并不被限定的解释。例如，一些步骤可以依照不同顺序发生及/或与本文中显示及/或描述以外的其它步骤或事件同时进行。此外，并非所有显示的步骤都需要用于实施于本文所描述之一或多个观点或实施例。再者，本文中所描述的一或多个行为皆可以一或多个分开的步骤及/或阶段实现。
在步骤1602，沿半导体基底正面形成一或多个半导体元件。图5绘示一些对应于步骤1602的实施例。
在步骤1604，在沿半导体基底的正面设置的层间介电结构中形成多个金属互连层。图6绘示一些对应于步骤1604的实施例。
在步骤1606，降低半导体基底的厚度。图7绘示一些对应于步骤1606的实施例。
在步骤1608，沿半导体基底的背面形成高介电常数介电层。图8绘示一些对应于步骤1608的实施例。
在步骤1610，形成介电层及/或缓冲层于高介电常数介电层之上。图8绘示一些对应于步骤1610的实施例。
在步骤1612，形成背面贯穿基底导通孔的开口。背面贯穿基底导通孔的开口延伸穿过介电层及/或缓冲层、高介电常数介电层、半导体基底及部分的层间介电结构。背面贯穿基底导通孔可接触设置于基底与厚金属互连线之间的薄金属互连线。图9绘示一些对应于步骤1612的实施例。
在步骤1614，形成背面贯穿基底导通孔衬垫于背面贯穿基底导通孔的开口中。图10绘示一些对应于步骤1614的实施例。
在步骤1616，以导电材料填充背面贯穿基底导通孔的开口。图10绘示一些对应于步骤1616的实施例。
在步骤1618，实施平坦化制程，以形成具有与介电层或缓冲层大抵共平面的上表面的背面贯穿基底导通孔。图11绘示一些对应于步骤1618的实施例。
在步骤1620，形成导电焊垫于背面贯穿基底导通孔的平坦表面上及介电层或缓冲层上。图12绘示一些对应于步骤1620的实施例。
在步骤1622，形成一或多个保护层于导电焊垫及介电层或缓冲层之上。图13绘示一些对应于步骤1622的实施例。
在步骤1624，于保护层内的开口中形成凸块下金属层位于接触导电焊垫的位置上。图14绘示一些对应于步骤1624的实施例。
在步骤1626，形成导电凸块于凸块下金属层上。图15绘示一些对应于步骤1626的实施例。
因此，本发明涉及具有背面贯穿基底导通孔的集成芯片(IC)，其在金属互连层与背面导电焊垫背面之间有直接的物理连接。
在一些实施例中，本发明涉及集成芯片。集成芯片包括多个金属互连层设置于沿基底的正面设置的层间介电结构中，介电层沿基底的背面设置，导电焊垫设置于介电层之上，背面贯穿基底导通孔从该些金属互连层中的一个延伸穿过基底及介电层至导电焊垫，导电凸块设置于导电焊垫之上，导电焊垫具有平坦的下表面从背面贯穿基底导通孔之上延伸至导电凸块之下。
在其他一些实施例中，本发明涉及集成芯片。集成芯片包括多个金属互连层设置于沿基底的正面设置的层间介电结构中，该些金属互连层包括第一金属互连线及通过第一金属互连线与基底分开的更厚的第二金属互连线，高介电常数介电层设置于基底的背面上，介电层通过高介电常数介电层与基底的背面分开，导电焊垫设置于介电层之上，背面贯穿基底导通孔延伸于第一金属互连线与导电焊垫之间。
在其他一些实施例中，本发明涉及集成芯片的制造方法。集成芯片的制造方法包括形成多个金属互连层在沿基底的正面设置的层间介电结构中，该些金属互连层包括第一金属互连线及通过第一金属互连线与基底分开的更厚的第二金属互连线。集成芯片的制造方法更包括形成高介电常数介电层于基底的背面上，以及形成介电层于高介电常数介电层之上。集成芯片的制造方法更包括蚀刻介电层、高介电常数介电层、基底及层间介电结构，以形成背面贯穿基底导通孔的开口，其延伸至与第一金属互连线接触的位置。集成芯片的制造方法更包括沉积导电材料于背面贯穿基底导通孔的开口中，以及实施平坦化制程移除背面贯穿基底导通孔开口外的导电材料，以形成背面贯穿基底导通孔。集成芯片的制造方法更包括形成导电焊垫，其具有平坦的下表面设置于背面贯穿基底导通孔上。
以上概略说明了本发明多个实施例的特征部件，使所属技术领域中具有通常知识者对于本发明的概念可更为容易理解。所属技术领域中具有通常知识者应了解到本说明书可作为其他结构或制程的变更或设计基础，以实现相同于本发明实施例的目的及/或获得相同的优点。所属技术领域中具有通常知识者也可理解与上述等同的结构或制程并未脱离本发明的精神及保护范围内，且可在不脱离本发明的精神及范围内，当可作更动、替代与润饰。

Claims (10)

1.一种集成芯片，包括：
多个金属互连层，设置于沿一基底的一正面设置的一层间介电结构中；
一介电层，沿该基底的一背面设置；
一导电焊垫，设置于该介电层之上；
一背面贯穿基底导通孔，从多个所述金属互连层中的一个延伸穿过该基底及该介电层至该导电焊垫；以及
一导电凸块，设置于该导电焊垫之上，其中该导电焊垫具有一平坦的下表面从该背面贯穿基底导通孔之上延伸至该导电凸块之下。
2.如权利要求1所述的集成芯片，其中多个所述金属互连层包括一较薄的第一金属互连线及通过该第一金属互连线与该基底分开的一较厚的第二金属互连线，且其中该背面贯穿基底导通孔接触该第一金属互连线。
3.如权利要求1所述的集成芯片，还包括：
一保护层，设置于该介电层及该导电焊垫之上；以及
一凸块下金属层，从该保护层之上延伸至该保护层中的一开口内，其中该凸块下金属层系位于该导电焊垫与该导电凸块之间。
4.如权利要求3所述的集成芯片，其中该导电焊垫具有以一第一方向延伸的一第一段及以垂直于该第一方向的一第二方向延伸的一第二段。
5.如权利要求4所述的集成芯片，其中该背面贯穿基底导通孔接触该导电焊垫的该第一段，且该凸块下金属层接触该导电焊垫的该第二段。
6.一种集成芯片，包括：
多个金属互连层，设置于沿一基底的一正面设置的一层间介电结构中，其中多个所述金属互连层包括一较薄的第一金属互连线及通过该第一金属互连线与该基底分开的一较厚的第二金属互连线；
一高介电常数介电层，设置于该基底的背面上；
一介电层，通过该高介电常数介电层与该基底的该背面分开；
一导电焊垫，设置于该介电层之上；以及
一背面贯穿基底导通孔，延伸于该第一金属互连线与该导电焊垫之间。
7.如权利要求6所述的集成芯片，还包括：
一保护层，设置于该介电层与该导电焊垫之上；
一凸块下金属层，从该保护层之上延伸至该保护层中的一开口内；以及
一导电凸块，设置于该凸块下金属层之上，其中该导电焊垫具有一平坦的下表面从该背面贯穿基底导通孔之上延伸至该导电凸块之下。
8.如权利要求6所述的集成芯片，其中该背面贯穿基底导通孔具有多个锥形的侧壁，连续地延伸于该第一金属互连线与该导电焊垫之间。
9.如权利要求6所述的集成芯片，其中该背面贯穿基底导通孔具有小于或等于2.5微米的宽度。
10.一种集成芯片的制造方法，包括以下步骤：
形成多个金属互连层，在沿一基底的一正面设置的一层间介电结构中，其中多个所述金属互连层包括一第一金属互连线及通过该第一金属互连线与该基底分开的一更厚的第二金属互连线；
形成一高介电常数介电层于该基底之一背面上；
形成一介电层于该高介电常数介电层之上；
蚀刻该介电层、该高介电常数介电层、该基底及该层间介电结构，以形成一背面贯穿基底导通孔开口延伸至与该第一金属互连线接触的一位置；
沉积一导电材料于该背面贯穿基底导通孔开口之中；
实施一平坦化制程移除该背面贯穿基底导通孔开口外的该导电材料，以形成一背面贯穿基底导通孔；以及
形成一导电焊垫，具有一平坦下表面设置于该背面贯穿基底导通孔上。
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