TWI756695B - 半導體裝置的互連件佈局 - Google Patents

半導體裝置的互連件佈局 Download PDF

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TWI756695B
TWI756695B TW109117535A TW109117535A TWI756695B TW I756695 B TWI756695 B TW I756695B TW 109117535 A TW109117535 A TW 109117535A TW 109117535 A TW109117535 A TW 109117535A TW I756695 B TWI756695 B TW I756695B
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conductive
substrate
dtc
conductive line
semiconductor device
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TW109117535A
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TW202107662A (zh
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蔡俊雄
沙哈吉 摩爾
林佑明
幸仁 萬
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例係關於一種半導體裝置及其形成方法。該半導體裝置包含一基板、該基板內之一深溝槽電容器(DTC)及該DTC及該基板上方之一互連結構。該互連結構包含與該基板電接觸之一密封環結構、與該DTC電接觸之一第一導電通路及將該密封環結構電耦合至該第一導電通路之一第一導電線。

Description

半導體裝置的互連件佈局
本發明實施例係有關半導體裝置的互連件佈局。
半導體裝置用於諸如(例如)個人電腦、蜂巢式電話、數位攝影機及其他電子設備之各種電子應用中。通常藉由在一半導體基板上方循序沈積材料之絕緣或介電層、導電層及半導體層且使用微影及蝕刻程序圖案化各種材料層以在其上形成電路組件及元件來製造半導體裝置。
半導體產業藉由不斷減小最小構件大小來不斷提高各種電子組件(例如電晶體、二極體、電阻器、電容器等等)之整合密度，其允許更多組件整合至一給定面積中。然而，隨著最小構件大小減小，所使用之各程序中出現額外問題，且應解決此等額外問題。
本發明的一實施例係關於一種半導體裝置，其包括：一基板；一深溝槽電容器(DTC)，其位於該基板內；及一互連結構，其位於該DTC及該基板上方，該互連結構包括與該基板電接觸之一密封環結構、與該DTC電接觸之一第一導電通路及將該密封環結構電耦合至該第一導電通路之一第一導電線。
本發明的一實施例係關於一種半導體裝置，其包括：一基板；一深溝槽電容器(DTC)，其位於該基板內；及一互連結構，其位於該DTC及該基板上方，該互連結構包括與該基板電接觸之一密封環結構、與該DTC電接觸之一第一導電線及將該密封環結構電耦合至該第一導電線之一第二導電線。
本發明的一實施例係關於一種方法，其包括：在一基板中形成一凹槽；在該基板中形成相鄰於該凹槽之一摻雜區域；在該凹槽中形成一深溝槽電容器(DTC)；及在該DTC及該基板上方形成一互連結構，其中形成該互連結構包括形成與該摻雜區域電接觸之一密封環結構、形成與該DTC電接觸之一第一導電通路及在該第一導電通路上方形成一第一導電線，該第一導電線將該密封環結構電耦合至該第一導電通路。
以下揭示提供用於實施本發明實施例之不同特徵之諸多不同實施例或實例。下文將描述組件及配置之特定實例以簡化本揭示。當然，此等僅為實例且不意在限制。例如，在以下描述中，在一第二構件上方或一第二構件上形成一第一構件可包含其中形成直接接觸之該第一構件及該第二構件之實施例，且亦可包含其中額外構件可形成於該第一構件與該第二構件之間使得該第一構件及該第二構件可不直接接觸之實施例。另外，本揭示可在各種實例中重複元件符號及/或字母。此重複係為了簡單及清楚且其本身不指示所討論之各種實施例及/或組態之間的一關係。
此外，為便於描述，空間相對術語(諸如「下面」、「下方」、「下」、「上方」、「上」及其類似者)在本文中可用於描述一元件或構件與另一(些)元件或構件之關係，如圖中所繪示。除圖中所描繪之定向之外，空間相對術語亦意欲涵蓋裝置在使用或操作中之不同定向。可依其他方式(旋轉90度或以其他定向)定向設備且亦可因此解譯本文中所使用之空間相對描述詞。
將相對於一特定背景(即，一半導體裝置之一互連結構佈局)來描述實施例。半導體裝置可為包括深溝槽電容器(DTC)之一積體被動裝置(IPD)。然而，本文中所討論之實施例亦可應用於其他半導體裝置，諸如平面CMOS裝置、FinFET裝置或其類似者。歸因於用於形成凸塊下金屬(UBM)之一沈積步驟期間之電漿發弧，本文中所討論之各種實施例可避免一半導體裝置之各種組件(諸如(例如) DTC)燒壞及短路。此外，本文中所討論之各種實施例允許提高電容器密度及提高半導體裝置良率。
圖1至圖7繪示根據一些實施例之製造一半導體裝置晶圓100之各種中間階段之剖面圖。圖1繪示半導體裝置晶圓100之一邊緣部分之一剖面圖，其中一側壁101係半導體裝置晶圓100之邊緣。在一些實施例中，半導體裝置晶圓100包括一基板103。基板103可包括(例如)摻雜或未摻雜之塊狀矽或一絕緣體上半導體(SOI)基板之一主動層。一SOI基板一般包括形成於一絕緣體層上之一半導體材料(諸如矽)層。絕緣體層可為(例如)一埋藏氧化物(BOX)層或氧化矽層。絕緣體層設置於一基板(諸如一矽或玻璃基板)上。替代地，基板103可包含：另一元素半導體，諸如鍺；一化合物半導體，其包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或碲化銦；一合金半導體，其包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其等之組合。亦可使用其他基板，諸如多層或梯度基板。
在一些實施例中，在基板103中形成一或多個凹槽105 (圖1中由一單一凹槽105繪示)。在一些實施例中，可使用適合光微影及蝕刻方法來圖案化基板103以形成凹槽105。例如，可在基板103上方形成及圖案化一光阻劑(圖中未展示)，且可利用一或多個蝕刻程序(例如一乾式蝕刻程序)來移除其中期望有凹槽105之基板103之部分。在一些實施例中，凹槽105可具有約100 nm至約1000 nm之間的一寬度W1 。在一些實施例中，凹槽105可具有約1000 nm至約5000 nm之間的一深度D1 。在一些實施例中，一比率W1 /D1 係約0.02至約1。如下文將更詳細描述，深溝槽電容器(DTC)形成於凹槽105中。
在一些實施例中，在基板103中形成一或多個摻雜區域107 (圖1中由一單一摻雜區域107繪示)。可使用植入、熱擴散、其等之一組合或其類似者來形成一摻雜區域107。在一些實施例中，藉由在基板103中植入砷(As)或磷(P)來形成摻雜區域107。在一些實施例中，植入物之一劑量係介於約1E13個離子/cm2 至約1E15個離子/cm2 之間。在一些實施例中，植入能係介於約1 KeV至約10 KeV之間。在一些實施例中，摻雜區域107之一寬度W2 係介於約50 nm至約500 nm之間。在一些實施例中，摻雜區域107之一深度D2 係介於約10 nm至約100 nm之間。在一些實施例中，一比率W2 /D2 係介於約0.5至約50之間。在一些實施例中，在形成一或多個凹槽105之後形成一或多個摻雜區域107。在其他實施例中，在形成一或多個凹槽105之前形成一或多個摻雜區域107。如下文將更詳細描述，在基板103與一隨後形成之密封環(SR)結構之間的一界面處形成摻雜區域107。摻雜區域107減小基板103之電阻率且減少或消除基板103與密封環(SR)結構之間的界面處之電荷累積。
參考圖2，在凹槽105 (參閱圖1)中形成一DTC 213。在一些實施例中，在基板103上方且沿凹槽105之側壁及一底部形成一襯層201。在一些實施例中，襯層201可包括一介電材料(諸如氧化矽、SiON、SiCON、其等之一組合或其類似者)且可使用原子層沈積(ALD)、化學汽相沈積(CVD)、其等之一組合或其類似者來形成。在一些實施例中，襯層201具有約5 nm至約100 nm之間的一厚度。在一些實施例中，圖案化襯層201以暴露基板103之一頂面。在一些實施例中，圖案化程序可包括適合光微影及蝕刻方法。在圖2所繪示之實施例中，在完成圖案化程序之後，襯層201完全覆蓋摻雜區域107。在其他實施例中，襯層201可部分覆蓋摻雜區域107。
在一些實施例中，在形成襯層201之後，依一交替方式在凹槽105 (參閱圖1)中形成導電層203A至203D及介電層205A至205D。導電層203A至203D亦可指稱電容器電極203A至203D。在一些實施例中，導電層203A至203D之各者可包括一導電材料(諸如摻雜矽、多晶矽、銅、鎢、鋁或銅合金、鈦、氮化鈦、鉭、氮化鉭、其等之一組合或其類似者)且可使用電鍍、物理汽相沈積(PVD)、ALD、CVD、其等之一組合或其類似者來形成。在一些實施例中，導電層203A至203D之各者具有約10 nm至約100 nm之間的一厚度。在一些實施例中，介電層205A至205D之各者可包括一高K介電材料，諸如氧化鋁、氧化鋯、其等之一組合、其等之一多層或其類似者。在一些實施例中，介電層205A至205D之各者包括一多層，其包含兩層氧化鋯及插入於氧化鋯層之間的一層氧化鋁。在一些實施例中，介電層205A至205D之各者具有約0.3 nm至約10 nm之間的一厚度。
在一些實施例中，在襯層201上方形成導電層203A之後，圖案化導電層203A以暴露襯層201之一頂面之部分。在一些實施例中，圖案化程序可包括適合光微影及蝕刻方法。隨後，沿導電層203A之對置側壁形成間隔物207A。各間隔物207A可包括一介電材料，諸如氧化矽、氮化矽、氮氧化矽、其等之一組合、其等之一多層或其類似者。在一些實施例中，藉由使用ALD、CVD、其等之一組合或其類似者毯覆式沈積一介電材料且各向異性蝕刻介電材料以移除介電材料之水平部分來形成間隔物207A。介電材料之剩餘垂直部分形成間隔物207A。在一些實施例中，各間隔物207A具有約5 nm至約50 nm之間的一寬度。隨後，在導電層203A及間隔物207A上方形成介電層205A。在一些實施例中，圖案化介電層205A以移除延伸超過間隔物207A之介電層205之部分。在一些實施例中，圖案化程序可包括適合光微影及蝕刻方法。
接著，在介電層205A及基板103上方毯覆式形成導電層203B。接著，圖案化導電層203B以暴露介電層205A之一頂面之部分。在一些實施例中，圖案化程序可包括適合光微影及蝕刻方法。隨後，沿導電層203B之對置側壁形成間隔物207B。在一些實施例中，可使用類似於間隔物207A之材料及方法來形成間隔物207B且在此不重複描述。在一些實施例中，各間隔物207B具有約5 nm至約50 nm之間的一寬度。隨後，在導電層203B及間隔物207B上方形成介電層205B。在一些實施例中，圖案化介電層205B以移除延伸超過間隔物207B之介電材料205B之部分。在一些實施例中，圖案化程序可包括適合光微影及蝕刻方法。
接著，重複上文參考形成導電層203B、間隔物207B及介電層205B所描述之程序步驟以在介電層205B上方形成導電層203C、間隔物207C及介電層205C且形成導電層203D、間隔物207D及介電層205D。在一些實施例中，可使用類似於間隔物207A之材料及方法來形成間隔物207C及207D且在此不重複描述。在一些實施例中，各間隔物207C具有約5 nm至約50 nm之間的一寬度。在一些實施例中，各間隔物207D具有約5 nm至約50 nm之間的一寬度。在圖2所繪示之實施例中，DTC 213包括4個電容器電極。在其他實施例中，DTC 213可基於DTC 213之設計要求來包括4個以上或4個以下電容器電極。一般技術者將意識到，用於形成DTC之上述程序僅為形成DTC之一方法，且其他方法亦完全意欲包含於實施例之範疇內。
進一步參考圖2，在基板103中形成DTC 213之後，使用一介電材料209來填充凹槽105 (參閱圖1)之剩餘部分。在一些實施例中，介電材料209可包括氧化物(諸如氧化矽)、氮化物(諸如氮化矽)、其等之一組合、其等之一多層或其類似者。在一些實施例中，圖案化介電材料209以移除延伸超過間隔物207D之介電材料209之部分。在一些實施例中，圖案化程序可包括適合光微影及蝕刻方法。
在一些實施例中，在形成及圖案化介電材料209之後，在DTC 213上方形成一蝕刻停止層(ESL) 211。在一些實施例中，ESL 211可包括一或多個介電材料層。適合介電材料可包含氧化物(諸如氧化矽、氧化鋁或其類似者)、氮化物(諸如SiN或其類似者)、氮氧化物(諸如SiON或其類似者)、碳氧化物(諸如SiOC或其類似者)、碳氮化物(諸如SiCN或其類似者)、碳化物(諸如SiC或其類似者)、其等之組合或其類似者，且可使用旋塗塗覆、CVD、電漿增強CVD (PECVD)、ALD、其等之一組合或其類似者來形成。在一些實施例中，ESL 211具有約3 nm至約30 nm之間的一厚度。在一些實施例中，ESL 211用於促進形成提供至DTC 213之導電層203A至203D之電連接的導電通路。ESL 211亦可指稱一接觸蝕刻停止層(CESL)。
參考圖3，在形成DTC 213之後，在基板103及DTC 213上方形成一互連結構301。在一些實施例中，互連結構301包括複數個介電層及嵌入於複數個介電層中之導電構件。在圖3所繪示之實施例中，互連結構301包括一介電層303A及嵌入於介電層303A內之導電通路307A至307E、一介電層303B及嵌入於介電層303B內之導電線309A至309C、一介電層303C及嵌入於介電層303C內之導電通路311A至311E及一介電層303D及嵌入於介電層303D內之導電線313A至313C。在圖3所繪示之實施例中，互連結構301包括4個介電層及嵌入導電構件。在其他實施例中，互連結構301可基於互連結構301之設計要求來包括4個以上或4個以下介電層及嵌入導電構件。
在一些實施例中，介電層303A至303D可包含一低k介電材料(諸如磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(BPSG)、氟矽酸鹽玻璃(FSG)、SiOxCy、旋塗玻璃、旋塗聚合物、矽碳材料、其等之化合物、其等之複合物、其等之組合或其類似者)，且可藉由任何適合方法(諸如旋塗塗覆、CVD、PECVD、ALD、其等之一組合或其類似者)來形成。可使用任何適合方法(諸如一鑲嵌法或其類似者)來形成導電構件(諸如導電通路307A至307E及311A至311E及導電線309A至309C及313A至313C)。在一些實施例中，用於形成導電構件之步驟包含在各自介電層中形成開口、在開口中沈積一或多個障壁/黏著層(圖中未展示)、在一或多個障壁/黏著層上方沈積晶種層(圖中未展示)及使用一導電材料來填充開口。接著，執行一化學機械拋光(CMP)以移除一或多個障壁/黏著層、晶種層及過填充開口之導電材料之過量材料。
在一些實施例中，一或多個障壁/黏著層可包括鈦、氮化鈦、鉭、氮化鉭、其等之一組合或其類似者，且可使用PVD、CVD、ALD、其等之一組合或其類似者來形成。晶種層可包括銅、鈦、鎳、金、錳、其等之一組合或其類似者，且可藉由電鍍、ALD、CVD、PVD、濺鍍、其等之一組合或其類似者來形成。導電材料可包括銅、鋁、鎢、其等之組合、其等之合金或其類似者，且可使用(例如)藉由電鍍或其他適合方法來形成。
在一些實施例中，互連結構301進一步包括形成於介電層303A至303D之相鄰者之間的蝕刻停止層(ESL) 305A至305C。ESL 305A至305C之一材料經選擇使得ESL 305A至305C之蝕刻率小於介電層303A至303D之對應者之蝕刻率。在一些實施例中，ESL 305A之一蝕刻率小於介電層303B之一蝕刻率。在一些實施例中，ESL 305B之一蝕刻率小於介電層303C之一蝕刻率。在一些實施例中，ESL 305C之一蝕刻率小於介電層303D之一蝕刻率。在一些實施例中，ESL 305A至305C之各者可包括類似於上文參考圖2所描述之ESL 211之材料且在此不重複描述。
在一些實施例中，導電通路307A延伸穿過介電層303A、ESL 211及襯層201且實體接觸摻雜區域107。導電通路307A將摻雜區域107電耦合至導電線309A。導電通路307B延伸穿過介電層303A、ESL 211及介電層205A且實體接觸導電層203A。導電通路307B將導電層203A電耦合至導電線309A。導電通路307C延伸穿過介電層303A、ESL 211及介電層205C且實體接觸導電層203C。導電通路307C將導電層203C電耦合至導電線309A。導電通路307D延伸穿過介電層303A、ESL 211、介電材料209及介電層205D且實體接觸導電層203D。導電通路307D將導電層203D電耦合至導電線309B。導電通路307E延伸穿過介電層303A、ESL 211、介電材料209、介電層205B至205D、導電層203C及203D且實體接觸導電層203B。導電通路307E將導電層203B電耦合至導電線309C。在圖3所繪示之實施例中，導電通路307A至307E部分延伸至各自導電層203A至203D之各自者中。在其他實施例中，導電通路307A至307E之一或多者可完全延伸穿過導電層203A至203D之各自者。
在一些實施例中，導電通路311A延伸穿過介電層303C及ESL 305B且將導電線313A電耦合至導電線309A。導電通路311B及311C延伸穿過介電層303C及ESL 305B且將導電線313B電耦合至導電線309A。導電通路311D延伸穿過介電層303C及ESL 305B且將導電線313C電耦合至導電線309B。導電通路311E延伸穿過介電層303C及ESL 305B且將導電線313C電耦合至導電線309C。
進一步參考圖3，在一些實施例中，半導體裝置晶圓100之邊緣101附近之互連結構301之一些導電構件形成一密封環結構315。在圖3所繪示之實施例中，密封環結構315包括導電通路307A及311A、導電線313A及導電線309A之一部分。在此等實施例中，導電線309A將密封環結構315電耦合至互連結構301之其餘部分。在一些實施例中，藉由使導電線309A形成為共用於密封環結構315與互連結構301之其餘部分之間的一單一連續結構來減少遮罩之數目及用於形成導電線之遮罩程序之數目。在一些實施例中，密封環結構315沿半導體裝置晶圓100之邊緣101延伸且在一平面圖中環繞半導體裝置晶圓100之一內部部分。
參考圖4，在互連結構301上方形成接觸墊401A及401B。接觸墊401A與導電線313B電接觸。接觸墊401B與導電線313C電接觸。在一些實施例中，接觸墊401A及401B可包括一導電材料，諸如鋁、銅、鎢、銀、金、其等之一組合或其類似者。在一些實施例中，可使用(例如) PVD、ALD、電化學電鍍、無電電鍍、其等之一組合或其類似者來在互連結構301上方形成一導電材料。隨後，圖案化導電材料以形成接觸墊401A及401B。在一些實施例中，可使用適合光微影及蝕刻方法來圖案化導電材料。
在一些實施例中，在互連結構301及接觸墊401A及401B上方形成一鈍化層403。在一些實施例中，鈍化層403可包括一或多層不可光圖案化絕緣材料、一或多層可光圖案化絕緣材料、其等之一組合或其類似者。不可光圖案化絕緣材料可包括氮化矽、氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷矽酸鹽玻璃(BPSG)、其等之一組合或其類似者，且可使用CVD、PVD、ALD、一旋塗塗覆程序、其等之一組合或其類似者來形成。可光圖案化絕緣材料可包括聚苯並噁唑(PBO)、聚醯亞胺(PI)、苯並環丁烯(BCB)、其等之一組合或其類似者，且可使用一旋塗塗覆程序或其類似者來形成。在一些實施例中，鈍化層403具有約5 nm至約50 nm之間的一厚度。
在一些實施例中，在鈍化層403中形成開口405A及405B以分別暴露接觸墊401A及401B之部分。在一些實施例中，可使用適合光微影及蝕刻方法來圖案化鈍化層403。在一些實施例中，開口405A及405B具有約500 nm至約5000 nm之間的一寬度。
圖5及圖6繪示分別在接觸墊401A及401B上方形成凸塊下金屬(UBM) 601A及601B。在一些實施例中，UBM 601A及601B之各者可包含多個導電材料層，諸如一鈦層、一銅層及一鎳層。然而，一般技術者將意識到，存在適合於形成UBM 601A及601B之材料及層之諸多適合配置，諸如鉻/鉻銅合金/銅/金之一配置、鈦/鈦鎢/銅之一配置或銅/鎳/金之一配置。可用於UBM 601A及601B之任何適合材料或材料層完全意欲包含於本申請案之範疇內。
參考圖5，在鈍化層403上方形成一遮罩層501。在一些實施例中，遮罩層501包括一光阻劑或其類似者。在一些實施例中，圖案化遮罩層501以在遮罩層501中形成開口503A及503B。在其中遮罩層501包括一光阻劑之一些實施例中，圖案化程序可包含適合光微影方法。開口503A暴露鈍化層403中之開口405A。開口503B暴露鈍化層403中之開口405B。在一些實施例中，開口503A及503B具有約1000 nm至約5000 nm之間的一寬度。
在一些實施例中，在遮罩層501中形成開口503A及503B之後，在遮罩層501及包括開口503A及503B及開口405A及405B之組合開口之側壁及底部上方形成一導電層505。在一些實施例中，導電層505包括鈦、銅、鎳、鉻、金、鎢、其等之合金、其等之多層或其類似者，且可使用PVD、ALD、CVD、電化學電鍍、無電電鍍、其等之一組合或其類似者來形成。在一些實施例中，導電層505具有約5 nm至約100 nm之間的一厚度。
參考圖6，在形成導電層505之後，移除遮罩層501及形成於其上之導電層505之部分。導電層505之剩餘部分分別形成接觸墊401A及401B上方之UBM 601A及601B。在其中遮罩層501包括一光阻劑之一些實施例中，移除程序可包含一灰化程序及接著一濕式清潔程序。
參考圖7，連接器701A及701B分別形成於UBM 601A及601B上方且電耦合至UBM 601A及601B。在一些實施例中，連接器701A及701B之各者可為一焊球、一受控倒疊晶片連接(C4)凸塊、一球柵陣列(BGA)球、一微凸塊、一無電鍍鎳-無電鍍鈀浸金技術(ENEPIG)形成之凸塊、一銅柱、其等之一組合或其類似者。在其中連接器701A及701B由焊接材料形成之一些實施例中，可執行一回焊程序以將焊接材料塑形成所要凸塊形狀。在一些實施例中，在形成連接器701A及701B之後，切割半導體裝置晶圓100以形成個別半導體裝置。切割程序可包含鋸切、一雷射燒蝕方法、一蝕刻程序、其等之一組合或其類似者。隨後，可測試個別半導體裝置之各者以識別良裸晶粒(KGD)用於進一步處理。
圖8繪示根據一些實施例之一沈積設備800之一剖面圖。在一些實施例中，沈積設備800用於在半導體裝置晶圓100上方沈積導電層505，如上文參考圖5所描述。在一些實施例中，沈積設備800係執行一直流(DC)磁控濺鍍程序之一PVD設備。在一些實施例中，沈積設備800包含一室801，其係一真空室。在一些實施例中，一泵803耦合至室801以調諧室801內之一壓力。在一些實施例中，在沈積程序期間，一程序壓力可介於約1 mTorr至約100 mTorr之間。一卡盤805安置於室801中。卡盤805經組態以在將導電層505沈積於半導體裝置晶圓100上方時固持半導體裝置晶圓100。在一些實施例中，卡盤805可為一靜電卡盤、一真空卡盤或其類似者。在一些實施例中，卡盤805可組態為一陽極且亦可指稱一陽極805。一陰影邊緣環807安置於室801中，在卡盤805上方，且圍繞半導體裝置晶圓100。在一些實施例中，陰影邊緣環807在沈積程序期間保護卡盤805。
在一些實施例中，一陰極809安置於卡盤805上方，使得半導體裝置晶圓100插入於陰極809與卡盤805之間。在一些實施例中，陰極809包括一磁性陣列811。在一些實施例中，磁性陣列811包括一或多個磁體。磁性陣列811在室801內產生圖8中由磁力線813指示之一磁場。一標靶材料層815安置於陰極809上，使得標靶材料層815插入於陰極809與半導體裝置晶圓100之間。標靶材料層815包括在沈積程序期間形成導電層505之一材料。
在一些實施例中，一電壓源817耦合至陰極809且產生陰極809與陽極805之間的一所要電壓。在一些實施例中，電壓源817係一DC電壓源。在一些實施例中，電壓源817產生陰極809與陽極805之間的一負電壓，使得負電壓係介於約50 V至約350 V之間，諸如約300 V。在一些實施例中，電壓源817具有約0.5 kW至約50 kW之間的一功率，諸如約1 kW。
在一些實施例中，一進氣口819提供適合程序氣體至室801。在一些實施例中，適合程序氣體包含惰性氣體，諸如He、Ne、Ar、Kr、Xe、Ra、其等之一組合或其類似者。在一些實施例中，由電壓源817產生之電壓加速之電子(圖中未展示)與程序氣體之原子碰撞以在室801內電離原子且產生電漿821。電漿821包括程序氣體之離子823。在一些實施例中，磁性陣列811使電漿821陷留於陰極809之一下表面附近以形成高密度電漿區域825。高密度電漿區域825提高離子823之濺鍍效率。在沈積程序期間，正電離子823朝向標靶材料層815加速且與標靶材料層815碰撞。碰撞射出標靶材料之原子827，其接著沈積於半導體裝置晶圓100上以形成導電層505。
進一步參考圖5及圖8，在沈積導電層505期間，電荷可累積於陰影邊緣環807上且可產生陰影邊緣環807與半導體裝置晶圓100之間的一電位差。在一些實例中，歸因於半導體裝置晶圓100之邊緣101與陰影邊緣環807之間的不當間距，一電弧829形成於半導體裝置晶圓100之邊緣101與陰影邊緣環807之間且一大電流脈衝流動通過半導體裝置晶圓100。
進一步參考圖5，在電弧放電期間，電流脈衝具有通過半導體裝置晶圓100之互連結構301的一路徑507。在圖5所繪示之實施例中，路徑507延伸通過導電層505、接觸墊401A、導電線313B、導電通路311B及311C、導電線309A及導電通路307A。沿著路徑507，電流脈衝流動至摻雜區域107且接著至基板103。藉由形成摻雜區域107，在導電通路307A與基板103之間的界面處減小基板103之電阻率且無大量電荷累積於導電通路307A與基板103之間的界面處。因此，藉由形成摻雜區域107來形成一低電阻率路徑以使電流脈衝流動至基板103中。
藉由使用導電線309A來將密封環結構315電耦合至互連結構301之其餘部分，無大量電流流動通過導電通路307B及307C而至DTC 213。因此，無大量電荷累積於DTC 213之導電層203A與導電通路307B之間的一界面處且不產生跨導電層203A及襯層201之顯著電壓降。因此，避免歸因於DTC 213之大電壓降及短路而燒壞導電層203A及襯層201。此外，無大量電荷累積於DTC 213之導電層203C與導電通路307C之間的一界面處且不產生跨導電層203C及介電層205B之顯著電壓降。因此，避免歸因於DTC 213之大電壓降及短路而燒壞導電層203C及介電層205B。
圖9繪示根據一些實施例之一半導體裝置晶圓900之一剖面圖。在一些實施例中，半導體裝置晶圓900類似於圖7中所繪示之半導體裝置晶圓100，其中相同構件由相同元件符號標記，且在此不重複相同構件之描述。在一些實施例中，可使用類似於上文參考圖1至圖7所描述之程序步驟的程序步驟來形成半導體裝置晶圓900且在此不重複描述。半導體裝置晶圓900之互連結構901具有不同於半導體裝置晶圓100之互連結構301的一佈局。互連結構901包括分別插入於導電通路307A至307C與導電通路311A至311C之間的3個斷接導電線903A至903C來代替互連結構301中插入於導電通路307A至307C與導電通路311A至311C之間的單一連續導電線309A。此外，互連結構901包括一單一連續導電線905A來代替互連結構301中之2個斷接導電線313A及313B。因此，導電線905A將密封環結構907電耦合至互連結構901之其餘部分。
在一些實施例中，在形成UBM 601A及601B (如上文參考圖5、圖6及圖8所描述)期間，歸因於沈積導電層505期間之電弧放電，一電流脈衝沿一路徑909流動通過半導體裝置晶圓900。在圖9所繪示之實施例中，路徑909延伸通過導電層505、接觸墊401A、導電線905A、導電通路311A、導電線903A及導電通路307A。沿著路徑909，電路脈衝流動至摻雜區域107且接著至基板103。藉由形成摻雜區域107，在導電通路307A與基板103之間的界面處減小基板103之電阻率且無大量電荷累積於導電通路307A與基板103之間的界面處。因此，藉由形成摻雜區域107來形成一低電阻率路徑以使電路脈衝流動至基板103中。
藉由使用導電線905A來將密封環結構907電耦合至互連結構901之其餘部分，無大量電流流動通過導電通路307B及307C而至DTC 213。因此，無大量電荷累積於DTC 213之導電層203A與導電通路307B之間的一界面處且不產生跨導電層203A及襯層201之顯著電壓降。因此，避免歸因於DTC 213之大電壓降及短路而燒壞導電層203A及襯層201。此外，無大量電荷累積於DTC 213之導電層203C與導電通路307C之間的一界面處且不產生跨導電層203C及介電層205B之顯著電壓降。因此，避免歸因於DTC 213之大電壓降及短路而燒壞導電層203C及介電層205B。
圖10繪示根據一些實施例之一半導體裝置晶圓1000之一剖面圖。在一些實施例中，半導體裝置晶圓1000類似於圖7中所繪示之半導體裝置晶圓100，其中相同構件由相同元件符號標記，且在此不重複相同構件之描述。在一些實施例中，可使用類似於上文參考圖1至圖7所描述之程序步驟的程序步驟來形成半導體裝置晶圓1000且在此不重複描述。半導體裝置1000之互連結構1001具有不同於半導體裝置晶圓100之互連結構301的一佈局。互連結構1001包括一單一連續導電線1003A來代替互連結構301中之2個斷接導電線313A及313B。因此，導電線1003A及309A將密封環結構1005電耦合至互連結構1001之其餘部分。
在一些實施例中，在形成UBM 601A及601B (如上文參考圖5、圖6及圖8所描述)期間，歸因於沈積導電層505期間之電弧放電，一電流脈衝沿一路徑1007流動通過半導體裝置晶圓1000。在圖10所繪示之實施例中，路徑1007延伸通過導電層505、接觸墊401A、導電線1003A、導電通路311A至311C、導電線309A及導電通路307A。沿著路徑1007，電路脈衝流動至摻雜區域107且接著至基板103。藉由形成摻雜區域107，在導電通路307A與基板103之間的界面處減小基板103之電阻率且無大量電荷累積於導電通路307A與基板103之間的界面處。因此，藉由形成摻雜區域107來形成一低電阻率路徑以使電路脈衝流動至基板103中。
藉由使用導電線1003A及309A來將密封環結構1005電耦合至互連結構1001之其餘部分，無大量電流流動通過導電通路307B及307C而至DTC 213。因此，無大量電荷累積於DTC 213之導電層203A與導電通路307B之間的一界面處且不產生跨導電層203A及襯層201之顯著電壓降。因此，避免歸因於DTC 213之大電壓降及短路而燒壞導電層203A及襯層201。此外，無大量電荷累積於DTC 213之導電層203C與導電通路307C之間的一界面處且不產生跨導電層203C及介電層205B之顯著電壓降。因此，避免歸因於DTC 213之大電壓降及短路而燒壞導電層203C及介電層205B。
進一步參考圖7、圖9及圖10，已在用於保護DTC免受形成UBM期間之電弧放電的互連結構之佈局之背景中描述所繪示之實施例。一般技術者將意識到，互連結構301、901及1001之上述佈局可用於保護其他類型之裝置免受形成UBM期間之電弧放電。在一些實施例中，可在基板中或基板上形成諸如平面CMOS裝置、FinFET裝置或其類似者之裝置來代替DTC。在此等實施例中，互連結構301、901及1001之佈局可保護一電晶體裝置(諸如一FinFET裝置或一平面電晶體裝置)之源極/汲極區域及/或一閘極堆疊免受電弧放電。
圖11係繪示根據一些實施例之形成一半導體裝置之一方法1100的一流程圖。方法1100開始於步驟1101，其中在基板(諸如圖2中所繪示之基板103)上方形成一裝置(諸如圖2中所繪示之DTC 213)，如上文參考圖1及圖2所描述。在步驟1103中，在基板及裝置上方形成一互連結構(諸如圖3中所繪示之互連結構301)，如上文參考圖3所描述。在步驟1105中，在互連結構上方形成接觸墊(諸如圖4中所繪示之接觸墊401A及401B)，如上文參考圖4所描述。在步驟1107中，在接觸墊上方形成凸塊下金屬(諸如圖6中所繪示之UBM 601A及601B)，如上文參考圖5及圖6所描述。在步驟1109中，在凸塊下金屬上方形成連接器(諸如圖7中所繪示之連接器701A及701B)，如上文參考圖7所描述。
在一實施例中，一種半導體裝置包含：一基板；一深溝槽電容器(DTC)，其位於該基板內；及一互連結構，其位於該DTC及該基板上方，該互連結構包含：一密封環結構，其與該基板電接觸；一第一導電通路，其與該DTC電接觸；及一第一導電線，其將該密封環結構電耦合至該第一導電通路。在一實施例中，該半導體裝置進一步包含該基板中之一摻雜區域，該摻雜區域與該密封環結構電接觸。在一實施例中，該密封環結構包含：一第二導電通路，該第二導電通路與該摻雜區域及該第一導電線實體接觸；及一第二導電線，其位於該第二導電通路上方，該第二導電線位於該第一導電線上方。在一實施例中，該密封環結構包含：一第二導電通路，其與該摻雜區域實體接觸；及一第二導電線，其位於該第二導電通路上方，該第二導電線位於該第一導電線下方。在一實施例中，該互連結構進一步包含該第一導電線上方之一第二導電線，該第二導電線將該密封環結構電耦合至該第一導電通路。在一實施例中，該互連結構進一步包含與該DTC電接觸之一第二導電通路。在一實施例中，該第一導電線將該密封環結構電耦合至該第二導電通路。
在另一實施例中，一種半導體裝置包含：一基板；一深溝槽電容器(DTC)，其位於該基板內；及一互連結構，其位於該DTC及該基板上方，該互連結構包含：一密封環結構，其與該基板電接觸；一第一導電線，其與該DTC電接觸；及一第二導電線，其將該密封環結構電耦合至該第一導電線。在一實施例中，該第二導電線插入於該第一導電線與該DTC之間。在一實施例中，該第一導電線插入於該第二導電線與該DTC之間。在一實施例中，該互連結構進一步包含將該第一導電線電耦合至該第二導電線之一第一導電通路。在一實施例中，該半導體裝置進一步包含該基板中之一摻雜區域，該摻雜區域與該密封環結構實體接觸。在一實施例中，該密封環結構包含：一第一導電通路，該第一導電通路與該摻雜區域實體接觸；及一第二導電通路，其位於該第一導電通路上方，該第二導電通路與該第一導電線實體接觸。在一實施例中，該密封環結構包含：一第一導電通路，該第一導電通路與該摻雜區域實體接觸；及一第二導電通路，其位於該第一導電通路上方，該第二導電通路與該第二導電線實體接觸。
在又一實施例中，一種方法包含：在一基板中形成一凹槽；在該基板中形成相鄰於該凹槽之一摻雜區域；在該凹槽中形成一深溝槽電容器(DTC)；及在DTC及該基板上方形成一互連結構，其中形成該互連結構包含：形成與該摻雜區域電接觸之一密封環結構；形成與該DTC電接觸之一第一導電通路；及在該第一導電通路上方形成一第一導電線，該第一導電線將該密封環結構電耦合至該第一導電通路。在一實施例中，形成該互連結構進一步包含在該第一導電線上方形成一第二導電線。在一實施例中，形成該互連結構進一步包含在該第一導電通路與該第一導電線之間形成一第二導電線。在一實施例中，形成該互連結構進一步包含形成與該DTC電接觸之一第二導電通路。在一實施例中，在該凹槽中形成該DTC包含依一交替方式在該凹槽中形成複數個導電層及複數個介電層。在一實施例中，在該基板中形成該摻雜區域包含對該基板執行一植入程序。
上文概述若干實施例之特徵，使得熟習技術者可較佳理解本揭示之態樣。熟習技術者應瞭解，其可易於將本揭示用作設計或修改其他程序及結構之一基礎以實施相同目的及/或達成本文中所引入之實施例之相同優點。熟習技術者亦應意識到，此等等效構造不應背離本揭示之精神及範疇，且其可在不背離本揭示之精神及範疇之情況下對本文作出各種改變、替代及更改。
100:半導體裝置晶圓 101:側壁/邊緣 103:基板 105:凹槽 107:摻雜區域 201:襯層 203A至203D:導電層/電容器電極 205A至205D:介電層 207A:間隔物 207B:間隔物 207C:間隔物 207D:間隔物 209:介電材料 211:蝕刻停止層(ESL) 213:深溝槽電容器(DTC) 301:互連結構 303A至303D:介電層 305A至305C:ESL 307A至307E:導電通路 309A至309C:導電線 311A至311E:導電通路 313A至313C:導電線 315:密封環結構 401A:接觸墊 401B:接觸墊 403:鈍化層 405A:開口 405B:開口 403:鈍化層 501:遮罩層 503A:開口 503B:開口 505:導電層 507:路徑 601A:凸塊下金屬(UBM) 601B:UBM 701A:連接器 701B:連接器 800:沈積設備 801:室 803:泵 805:卡盤/陽極 807:陰影邊緣環 809:陰極 811:磁性陣列 813:磁力線 815:標靶材料層 817:電壓源 819:進氣口 821:電漿 823:離子 825:高密度電漿區域 827:原子 829:電弧 900:半導體裝置晶圓 901:互連結構 903A至903C:導電線 905A:導電線 907:密封環結構 909:路徑 1000:半導體裝置晶圓 1001:互連結構 1003A:導電線 1005:密封環結構 1007:路徑 1100:方法 1101:步驟 1103:步驟 1105:步驟 1107:步驟 1109:步驟 D1:深度 D2:深度 W1:寬度 W2:寬度
自結合附圖解讀之以下詳細描述最佳理解本揭示之態樣。應注意，根據行業標準做法，各種構件未按比例繪製。事實上，為使討論清楚，可任意增大或減小各種構件之尺寸。
圖1至圖7繪示根據一些實施例之製造一半導體裝置晶圓之各種中間階段之剖面圖。
圖8繪示根據一些實施例之一沈積設備之一剖面圖。
圖9繪示根據一些實施例之一半導體裝置晶圓之一剖面圖。
圖10繪示根據一些實施例之一半導體裝置晶圓之一剖面圖。
圖11係繪示根據一些實施例之形成一半導體裝置之一方法的一流程圖。
100:半導體裝置晶圓
101:側壁/邊緣
103:基板
107:摻雜區域
201:襯層
203A至203D:導電層/電容器電極
205A至205D:介電層
211:蝕刻停止層(ESL)
213:深溝槽電容器(DTC)
301:互連結構
303A至303D:介電層
305A至305C:ESL
307A至307E:導電通路
309A至309C:導電線
311A至311E:導電通路
313A至313C:導電線
315:密封環結構
401A:接觸墊
401B:接觸墊
403:鈍化層
601A:凸塊下金屬(UBM)
601B:UBM
701A:連接器
701B:連接器

Claims (10)

  1. 一種半導體裝置，其包括：一基板；一深溝槽電容器(DTC)，其位於該基板內；及一互連結構，其位於該DTC及該基板上方，該互連結構包括：一密封環結構，其與該基板電接觸；一第一導電通路，其與該DTC電接觸；及一第一導電線，其將該密封環結構電耦合至該第一導電通路，其中該第一導電線之一部分為該密封環結構的一部分。
  2. 如請求項1之半導體裝置，其進一步包括該基板中之一摻雜區域，該摻雜區域與該密封環結構電接觸。
  3. 如請求項1之半導體裝置，其中該互連結構進一步包括與該DTC電接觸之一第二導電通路。
  4. 一種半導體裝置，其包括：一基板；一深溝槽電容器(DTC)，其位於該基板內；一互連結構，其位於該DTC及該基板上方，該互連結構包括：一密封環結構，其與該基板電接觸；一第一導電線，其與該DTC電接觸；及 一第二導電線，其將該密封環結構電耦合至該第一導電線；及一接觸墊，其位於該互連結構上方，該接觸墊經該密封環結構電耦合至該基板，其中該接觸墊與該第一導電線或該第二導電線物理接觸。
  5. 如請求項4之半導體裝置，其中該第二導電線插入於該第一導電線與該DTC之間。
  6. 如請求項4之半導體裝置，其中該第一導電線插入於該第二導電線與該DTC之間。
  7. 如請求項4之半導體裝置，其中該互連結構進一步包括將該第一導電線電耦合至該第二導電線之一第一導電通路。
  8. 如請求項4之半導體裝置，其進一步包括該基板中之一摻雜區域，該摻雜區域與該密封環結構實體接觸。
  9. 一種形成半導體裝置之方法，其包括：在一基板中形成一凹槽；在該基板中形成相鄰於該凹槽之一摻雜區域；在該凹槽中形成一深溝槽電容器(DTC)；及在該DTC及該基板上方形成一互連結構，其中形成該互連結構包括：形成與該摻雜區域電接觸之一密封環結構； 形成與該DTC電接觸之一第一導電通路；及在該第一導電通路上方形成一第一導電線，該第一導電線將該密封環結構電耦合至該第一導電通路，其中該第一導電線之一部分為該密封環結構的一部分。
  10. 如請求項9之方法，其中形成該互連結構進一步包括在該第一導電線上方形成一第二導電線。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3093590B1 (fr) 2019-03-06 2023-08-25 St Microelectronics Rousset Procédé de fabrication d’un élément capacitif, et circuit intégré correspondant.
US11791332B2 (en) * 2021-02-26 2023-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked semiconductor device and method
US20220415799A1 (en) * 2021-06-23 2022-12-29 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
CN117276274A (zh) * 2023-11-10 2023-12-22 荣耀终端有限公司 半导体器件及电路板

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040108587A1 (en) * 2002-12-09 2004-06-10 Chudzik Michael Patrick High density chip carrier with integrated passive devices
TW201242013A (en) * 2011-01-07 2012-10-16 Eastman Kodak Co Transistor including multiple reentrant profiles
TW201246387A (en) * 2011-01-28 2012-11-16 Renesas Electronics Corp Semiconductor device and manufacturing method therefor
US9023688B1 (en) * 2013-06-09 2015-05-05 Monolithic 3D Inc. Method of processing a semiconductor device
US20160020267A1 (en) * 2012-11-26 2016-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Low impedance high density deep trench capacitor
US20160379999A1 (en) * 2015-06-24 2016-12-29 Globalfoundries Inc. High performance heat shields with reduced capacitance
TW201729388A (zh) * 2015-12-26 2017-08-16 英特爾公司 晶片上之整合式被動裝置
TW201814912A (zh) * 2016-09-27 2018-04-16 美商格芯（美國）集成電路科技有限公司 具有降低電容可變性的半導體設備中的電容結構
US20180122781A1 (en) * 2016-05-17 2018-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method of Manufacture
TW201834174A (zh) * 2016-11-15 2018-09-16 日月光半導體製造股份有限公司 包括互連結構之半導體系統及裝置封裝
TW201838127A (zh) * 2017-03-30 2018-10-16 台灣積體電路製造股份有限公司 封裝結構

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6537849B1 (en) * 2001-08-22 2003-03-25 Taiwan Semiconductor Manufacturing Company Seal ring structure for radio frequency integrated circuits
US7053453B2 (en) * 2004-04-27 2006-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate contact and method of forming the same
JP4689244B2 (ja) * 2004-11-16 2011-05-25 ルネサスエレクトロニクス株式会社 半導体装置
US7898056B1 (en) * 2008-12-09 2011-03-01 Alvand Technology, Inc. Seal ring for reducing noise coupling within a system-on-a-chip (SoC)
US8492816B2 (en) * 2010-01-11 2013-07-23 International Business Machines Corporation Deep trench decoupling capacitor
US8283754B2 (en) * 2010-08-13 2012-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Seal ring structure with metal pad
US8810001B2 (en) * 2011-06-13 2014-08-19 Mediatek Inc. Seal ring structure with capacitor
US9923101B2 (en) * 2012-09-13 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure
US9240406B2 (en) * 2014-04-21 2016-01-19 Globalfoundries Inc. Precision trench capacitor
US9236326B2 (en) 2014-04-25 2016-01-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and fabricating method thereof
US9997520B2 (en) 2015-07-31 2018-06-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with capacitor and method for forming the same
US9780046B2 (en) * 2015-11-13 2017-10-03 Taiwan Semiconductor Manufacturing Company, Ltd. Seal rings structures in semiconductor device interconnect layers and methods of forming the same
JP6811664B2 (ja) * 2017-03-24 2021-01-13 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040108587A1 (en) * 2002-12-09 2004-06-10 Chudzik Michael Patrick High density chip carrier with integrated passive devices
TW201242013A (en) * 2011-01-07 2012-10-16 Eastman Kodak Co Transistor including multiple reentrant profiles
TW201246387A (en) * 2011-01-28 2012-11-16 Renesas Electronics Corp Semiconductor device and manufacturing method therefor
TW201612980A (en) * 2011-01-28 2016-04-01 Renesas Electronics Corp Manufacturing method for semiconductor device
US20160020267A1 (en) * 2012-11-26 2016-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Low impedance high density deep trench capacitor
US9023688B1 (en) * 2013-06-09 2015-05-05 Monolithic 3D Inc. Method of processing a semiconductor device
US20160379999A1 (en) * 2015-06-24 2016-12-29 Globalfoundries Inc. High performance heat shields with reduced capacitance
TW201729388A (zh) * 2015-12-26 2017-08-16 英特爾公司 晶片上之整合式被動裝置
US20180122781A1 (en) * 2016-05-17 2018-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method of Manufacture
TW201814912A (zh) * 2016-09-27 2018-04-16 美商格芯（美國）集成電路科技有限公司 具有降低電容可變性的半導體設備中的電容結構
TW201834174A (zh) * 2016-11-15 2018-09-16 日月光半導體製造股份有限公司 包括互連結構之半導體系統及裝置封裝
TW201838127A (zh) * 2017-03-30 2018-10-16 台灣積體電路製造股份有限公司 封裝結構

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