TWI628758B - 積體晶片及其製造方法 - Google Patents

積體晶片及其製造方法 Download PDF

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Publication number
TWI628758B
TWI628758B TW105132029A TW105132029A TWI628758B TW I628758 B TWI628758 B TW I628758B TW 105132029 A TW105132029 A TW 105132029A TW 105132029 A TW105132029 A TW 105132029A TW I628758 B TWI628758 B TW I628758B
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Taiwan
Prior art keywords
substrate
layer
dielectric layer
back surface
metal interconnection
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TW105132029A
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TW201729364A (zh
Inventor
高敏峰
楊敦年
黃薰瑩
劉人誠
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台灣積體電路製造股份有限公司
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Abstract

在一些實施例中，本揭露係有關於具有在金屬互連層與背面導電焊墊之間有直接物理性連接的背面貫穿基底導通孔的積體晶片，積體晶片具有多個金屬互連層設置於基底正面上的層間介電結構中，介電層沿基底背面設置，且導電焊墊設置於介電層之上，背面貫穿基底導通孔從多個金屬互連層中的一個延伸穿過基底及介電層至導電焊墊，導電凸塊設置於導電焊墊上，導電焊墊具有平坦的下表面從背面貫基底導通孔之上延伸至導電凸塊之下，直接連接導電焊墊至背面貫穿基底導通孔降低了導電焊墊的尺寸，藉此提升導電焊墊的繞線能力。

Description

積體晶片及其製造方法
本揭露係有關於積體晶片，且特別是有關於具有背面貫穿基底導通孔(BTSV)的積體晶片及其製造方法。
近代之積體晶片包含數百萬或數十億的半導體裝置設置於半導體基底(例如矽晶圓)中。半導體裝置連接至覆蓋在其上之包含複數個金屬互連層(例如導線及導通孔)的後段製程(back-end-of-the-line,BEOL)金屬化堆疊。這些金屬互連層將半導體裝置彼此電性連接且電性連接至外部構件。金屬互連層通常終止在位於後段製程金屬化堆疊之上的焊墊。此焊墊可包含一層厚金屬層，此厚金屬層提供從積體晶片至外部構件(例如積體晶片封裝)的導電連接。
在一些實施例中，本揭露係有關於積體晶片。積體晶片包括複數個金屬互連層設置於沿基底之正面設置的層間介電結構中，介電層沿基底之背面設置，導電焊墊設置於介電層之上，背面貫穿基底導通孔(back-side through-substrate-via,BTSV)從該些金屬互連層中的一個延伸穿過基底及介電層至導電焊墊，導電凸塊設置於導電焊墊之上，導電焊墊具有平坦的下表面從背面貫穿基底導通孔之上延 伸至導電凸塊之下。
在其他一些實施例中，本揭露係有關於積體晶片。積體晶片包括複數個金屬互連層設置於沿基底之正面設置的層間介電結構中，該些金屬互連層包括第一金屬互連線及藉由第一金屬互連線與基底分開的更厚的第二金屬互連線，高介電常數介電層設置於基底之背面上，介電層藉由高介電常數介電層與基底之背面分開，導電焊墊設置於介電層之上，背面貫穿基底導通孔延伸於第一金屬互連線與導電焊墊之間。
在其他一些實施例中，本揭露係有關於積體晶片的製造方法。積體晶片的製造方法包括形成複數個金屬互連層在沿基底之正面設置的層間介電結構中，該些金屬互連層包括第一金屬互連線及藉由第一金屬互連線與基底分開的更厚的第二金屬互連線。積體晶片的製造方法更包括形成高介電常數介電層於基底之背面上，以及形成介電層於高介電常數介電層之上。積體晶片的製造方法更包括蝕刻介電層、高介電常數介電層、基底及層間介電結構，以形成背面貫穿基底導通孔之開口，其延伸至與第一金屬互連線接觸的位置。積體晶片的製造方法更包括沉積導電材料於背面貫穿基底導通孔之開口中，以及實施平坦化製程移除背面貫穿基底導通孔之開口外的導電材料，以形成背面貫穿基底導通孔。積體晶片的製造方法更包括形成導電焊墊，其具有平坦的下表面設置於背面貫穿基底導通孔上。
100、200、400‧‧‧積體晶片
102、502‧‧‧半導體基底
102b、502b‧‧‧半導體基底之背面
102f、502f‧‧‧半導體基底之正面
104‧‧‧半導體元件
104g‧‧‧閘極電極層
104e‧‧‧閘極介電層
104s‧‧‧源極區
104d‧‧‧汲極區
106‧‧‧金屬互連層
107a、107b、107c、407、407a、407a'、407b、407b'、407c、407c'‧‧‧金屬線
108、410a、410b‧‧‧層間介電結構
108a、108b、108c、108d‧‧‧層間介電層
109a‧‧‧接觸窗
109b、109c‧‧‧金屬導通孔
110‧‧‧背面貫穿基底導通孔
112‧‧‧導電焊墊
112b‧‧‧導電焊墊之背面
112f‧‧‧導電焊墊之正面
114、204‧‧‧介電層
116、210、212‧‧‧保護層
118‧‧‧凸塊下金屬層
118a、118b‧‧‧金屬層
120‧‧‧導電凸塊
202‧‧‧高介電常數介電層
206‧‧‧緩衝層
208、1002‧‧‧背面貫穿基底導通孔襯墊
302‧‧‧第一方向
304‧‧‧第二方向
402a‧‧‧第一半導體晶片
402b‧‧‧第二半導體晶片
404‧‧‧黏著層
405‧‧‧隔離結構
406a‧‧‧第一半導體基底
406b‧‧‧第二半導體基底
408a、408b‧‧‧金屬互連層
409、409a、409a'、409b、409b'、409c、409c'‧‧‧接觸窗/導通孔
412‧‧‧貫穿介電導通孔
902‧‧‧背面貫穿基底導通孔的開口
904‧‧‧蝕刻劑
906‧‧‧遮罩層
1004‧‧‧導電材料
1102‧‧‧線段
1104‧‧‧平坦表面
1302‧‧‧凸塊下金屬層的開口
300‧‧‧上視圖
500、600、700、800、900、1000、1100、1200、1300、1400、1500‧‧‧剖面圖
1600‧‧‧方法
1602、1604、1606、1608、1610、1612、1614、1616、1618、1620、1622、1624、1626‧‧‧動作
wPad、wBTSV‧‧‧寬度
t、t1、t2‧‧‧厚度
根據以下的詳細說明並配合所附圖式做完整揭 露。應注意的是，根據本產業的一般作業，圖示中的各種特徵部件並未必按照比例繪製。事實上，可能任意的放大或縮小各種特徵部件的尺寸，以做清楚的說明。
第1圖係根據一些實施例繪示具有背面焊墊的積體晶片。
第2圖係根據一些其它的實施例繪示具有背面焊墊的積體晶片。
第3圖係根據一些實施例繪示導電焊墊連接至背面貫穿基底導通孔的上視圖。
第4圖係根據一些實施例繪示具有背面焊墊的三維積體晶片(three-dimensional integrated chip,3DIC)。
第5-15圖係根據一些實施例顯示製造具有背面焊墊的積體晶片的方法之剖面圖。
第16圖係根據一些實施例製造具有背面焊墊的積體晶片的方法之流程圖。
本說明書以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本發明。例如，本說明書以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方，即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦包含了尚可將附加的特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與上述第二特徵部件可能 未直接接觸的實施例。另外，本發明的說明中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或特徵部件與另一(複數)元件或(複數)特徵部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語。除了圖式所繪示的方位之外，空間相關用語涵蓋使用或操作中的裝置的不同方位。所述裝置也可被另外定位(例如旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。
積體晶片(integrated chip,IC)中的半導體裝置係藉由包含複數個金屬互連層(例如導線及導通孔)的後段製程(back-end-of-the-line,BEOL)金屬化堆疊的方式連接至外部電路(例如封裝基底)。金屬互連層之尺寸通常隨著離半導體基底之距離的增加而增加，例如具有相對小尺寸區域互連線耦合半導體基底中的半導體裝置至較大的互連線。較大的互連線係更進一步耦合至沿後段製程(BEOL)金屬化堆疊上表面設置的導電焊墊，後段製程(BEOL)金屬化堆疊連接積體晶片至外部電路。
導電焊墊以覆晶(flip-chip)封裝方式愈來愈緊密地連接至外部電路，覆晶封裝使用錫焊凸塊(solder bump)建立導電焊墊與封裝基底(例如印刷電路板)之間的直接電性接觸。具有覆晶封裝的積體晶片包含的保護層包括複數個開口延伸至 底下的最終(例如頂部)金屬互連層。重佈線層(redistribution layer,RDL)設置於保護層上，重佈線層可包含垂直構件(例如重佈線導通孔(redistribution via,RV))從最終金屬互連層延伸穿過保護層中的開口至側向構件，側向構件從最終金屬互連層重新分佈電性訊號至覆蓋保護層上的聚醯亞胺墊(polyimide pad)的導電焊墊，藉此使得不同封裝選擇能相容。凸塊下金屬層(under bump metallurgy,UBM)設置於導電焊墊上，且作為於導電焊墊及錫焊凸塊間的可焊性(solderable)介面。當重佈線層使得各種不同的焊墊配置可行時，大尺寸的重佈線導通孔(例如大於3um)會造成大的導電焊墊有受到限制的繞線能力(routing ability)。
本揭露係有關於具有背面貫穿基底導通孔的積體晶片及其製造方法，在金屬互連層與背面導電焊墊之間有直接物理性連接。在一些實施例中，積體晶片具有複數個金屬互連層設置於沿基底之正面設置的層間介電結構中，介電層沿基底之背面設置，且導電焊墊設置於介電層之上，背面貫穿基底導通孔(back-side through-substrate-via,BTSV)從這些金屬互連層中的一個延伸穿過基底及介電層至導電焊墊，導電凸塊設置於導電焊墊上，導電焊墊具有大抵平坦的下表面從背面貫基底導通孔之上延伸至導電凸塊之下。藉由使用導電焊墊直接連接至背面貫穿基底導通孔，導電焊墊的尺寸可降低，藉此提升導電焊墊的繞線能力(routing capability)。
第1圖係根據一些實施例繪示具有背面焊墊的積體晶片100。
積體晶片100包括具有正面102f和背面102b的半導體基底102，複數個半導體元件104(例如電晶體元件)沿半導體基底102之正面102f設置。後段製程(back-end-of-the-line,BEOL)金屬化堆疊設置於半導體基底102的正面102f之上，且包括複數個金屬互連層106設置於層間介電(inter-level dielectric,ILD)結構108中，這些金屬互連層106係電性耦合至這些半導體元件104，且可隨著離半導體基底102之正面102f之距離的增加而增加尺寸(例如從薄的M1層至較厚的Mx層，其中x>1)。
導電焊墊112係沿半導體基底102之背面102b設置，導電焊墊112具有正面112f面對半導體基底102，及背面112b背對半導體基底102。導電焊墊112之正面112f係藉由一或多層介電層114與半導體基底102分開，且導電焊墊112之正面112f可包括平坦表面沿著與一或多層介電層114的介面延伸。
背面貫穿基底導通孔(BTSV)110延伸穿過半導體基底102，從在後段製程金屬化堆疊中的金屬互連層106至導電焊墊112之正面112f，背面貫穿基底導通孔110從半導體基底102之背面102b向外突出穿過一或多層的介電層114。背面貫穿基底導通孔110具有相對小的尺寸(例如小於或等於大約2.5um)，使背面貫穿基底導通孔110連接至設置於後段製程金屬化堆疊之頂端金屬互連層(例如距離半導體基底102最遠的一層)下方的薄金屬互連層。
導電焊墊112之背面112b被保護層116覆蓋，凸塊下金屬(UBM)層118延伸穿過保護層116中的開口以接觸導電焊墊112之背面112b。在一些實施例中，凸塊下金屬層118也可 沿保護層116的上表面延伸。導電凸塊120設置於凸塊下金屬層118中，且位於藉由凸塊下金屬層118與保護層116分開的位置。導電凸塊120配置為提供半導體元件104與外部元件(例如印刷电路板(PCB)、其他積體晶片等等)之間的電性連接。在一些實施例中，凸塊下金屬層118設置於導電焊墊112之上，且位於從背面貫穿基底導通孔110側向偏移的位置。
藉由直接連接背面貫穿基底導通孔110於金屬互連層106與導電焊墊112的正面112f之間，導電焊墊112的寬度可降低(例如由於未使用重佈線層)。降低導電焊墊112的寬度可增加導電焊墊112之繞線的靈活度，且提升效能(例如由於半導體元件104與導電焊墊112之間較短的路徑)。
第2圖係根據一些其它的實施例繪示具有背面焊墊的積體晶片200。
積體晶片200包括半導體基底102及覆蓋在上面的後段製程金屬化堆疊。在一些實施例中，半導體基底102具有介於大約1um與大約10um之間的厚度t，複數個半導體元件104可設置於半導體基底102之正面102f中。
後段製程金屬化堆疊包括複數個金屬互連層設置於層間介電(ILD)結構108中。在一些實施例中，這些金屬互連層可包括複數個金屬線107a-107c設置於複數個接觸窗109a及/或金屬導通孔109b-109c之間。這些金屬互連線可增加尺寸，從薄的第一金屬線107a至厚的金屬線107b及/或107c，厚的金屬線107b及/或107c藉由薄的第一金屬線107a與半導體基底102分開。在一些實施例中，第一金屬線107a可具有小於大約70nm 的厚度。在其他一些實施例中，第一金屬線107a可具有小於大約30nm的厚度。在各種實施例中，這些金屬互連層可包括導電材料，例如銅、鋁、鎢或前述的組合。在各種實施例中，層間介電結構108可包括氧化物、超低介電常數(ultra-low k)的介電材料或低介電常數(low-k)的介電材料(例如碳氧化矽(SiCO))中的一或多個。
高介電常數(high-k)介電層202設置於半導體基底102之背面102b上，高介電常數介電層202係配置來降低於製程中被薄化後的半導體基底102之背面102b的粗糙度，藉由降低半導體基底102之背面102b的粗糙度，可降低裝置漏電(leakage)。高介電常數介電層202面對半導體基底102的面比背對半導體基底102的相反面較為粗糙(例如在垂直的位置具有較大的變異)。在各種實施例中，高介電常數介電層202可包括一或多層。在一些實施例中，高介電常數介電層202具有範圍介於大約10Å與大約1000Å之間的厚度t2。在一些實施例中，高介電常數介電層202可包括例如氧化鋁(Al2O3)、五氧化二鉭(Ta2O5)、二氧化鈦(TiO2)、二氧化鋯(ZrO2)、氧化鉿(HfO)、氧化矽鉿(HfSiO)、氧化鋁鉿(HfAlO)及/或氧化鉭鉿(HfTaO)。
介電層204設置於高介電常數介電層202之上。在各種實施例中，介電層204可包括氧化物(例如二氧化矽(SiO2))。在一些實施例中，緩衝層206可設置於介電層204之上，緩衝層206可包括氮化物(例如SiN、Si3N4)。導電焊墊112設置於介電層204及/或緩衝層206之上，導電焊墊112包括平坦結構沿介電層204及/或緩衝層206之上表面設置。在一些實施 例中，導電焊墊112可包括例如鋁。
背面貫穿基底導通孔110從後段製程金屬化堆疊延伸，穿過半導體基底102、高介電常數介電層202、介電層204及緩衝層206至導電焊墊112之正面112f。在一些實施例中，背面貫穿基底導通孔110可連接於導電焊墊112與薄的第一金屬線107a(例如最靠近半導體基底102之正面102f的M1層)之間。在一些實施例中，背面貫穿基底導通孔110可具有與介電層204或緩衝層206之上表面共平面的上表面。在一些實施例中，背面貫穿基底導通孔110可具有錐形的側壁(tapered sidewalls)延伸於薄的第一金屬線107a與導電焊墊112之間。在一些實施例中，錐形的側壁具有平滑的表面(例如具有固定的斜率)在半導體基底102與高介電常數介電層202之間轉變。錐形的側壁使得背面貫穿基底導通孔110的寬度從半導體基底102之正面102f開始增加至半導體基底102之背面102b。在各種實施例中，背面貫穿基底導通孔110可包括銅、鋁、鎢或相似的材料。
在一些實施例中，背面貫穿基底導通孔襯墊(BTSV liner)208係沿背面貫穿基底導通孔110之側壁設置。背面貫穿基底導通孔襯墊208將背面貫穿基底導通孔110與半導體基底102分開。在各種實施例中，背面貫穿基底導通孔襯墊208可包括例如氧化物或氮化矽。在一些實施例中，背面貫穿基底導通孔襯墊208也可沿高介電常數介電層202、介電層204及緩衝層206的側壁延伸。
一或多個保護層210及212(passivation layer)可設置於導電焊墊112之上，此一或多個保護層210及212延伸於導 電焊墊112之上且沿著導電焊墊112之側壁。在一些實施例中，保護層210及212可包括介電層(又稱保護層210)及聚醯亞胺(polyimide)層(又稱保護層212)。凸塊下金屬層118係設置於導電焊墊112之上表面上，且內襯於聚醯亞胺層(又稱保護層212)中的開口內部。凸塊下金屬層118可包括不同金屬層118a和118b的堆疊作為擴散層(diffusion layer)、阻障層(barrier layer)、潤濕層(wetting layer)及/或抗氧化層(anti-oxidation layer)。在一些實施例中，凸塊下金屬層118可包括銅、銅合金、鋁、鋁合金或類似的材料。在各種實施例中，導電焊墊112具有平坦下表面鄰接介電層204及/或緩衝層206，且介於背面貫穿基底導通孔110與凸塊下金屬層118之間。在一些實施例中，凸塊下金屬層118可更進一步沿聚醯亞胺層(又稱保護層212)之上表面延伸。
導電凸塊120係設置於凸塊下金屬層118上。在一些實施例中，導電凸塊120為焊料凸塊、銅凸塊、包含鎳(Ni)或金(Au)之金屬凸塊或前述的組合。在一些實施例中，導電凸塊120為焊料凸塊，藉由放置焊球於凸塊下金屬層118上且回焊(reflowing)焊球來形成。在一些實施例中，焊料凸塊包含無鉛(lead-free)預焊(pre-solder)層、錫銀(SnAg)或包含錫、鉛、銀、銅、鎳、鉍之合金的焊接材料或前述的組合。
第3圖係根據一些實施例繪示背面貫穿基底導通孔直接接觸導電焊墊的上視圖300。
如上視圖300所示，背面貫穿基底導通孔110接觸導電焊墊112之第一端點。在一些實施例中，背面貫穿基底導 通孔110可包具有圓形的剖面。在其他一些實施例中，背面貫穿基底導通孔110可具有其他形狀的剖面，凸塊下金屬層118接觸導電焊墊112之第二端點，且位於從背面貫穿基底導通孔110側向偏移的位置。在一些實施例中，背面貫穿基底導通孔110可具有寬度wBTSV範圍從大約0.3um至大約5um。
在一些實施例中，背面貫穿基底導通孔110被導電焊墊112覆蓋，由於背面貫穿基底導通孔110被導電焊墊112覆蓋，背面貫穿基底導通孔110的尺寸可影響導電焊墊112的尺寸，例如在一些這樣的實施例中，背面貫穿基底導通孔110可具有寬度wBTSV小於或等於大約1.5um，且導電焊墊112可具有寬度wPad小於或等於大約2.5um。在其他一些這樣的實施例中，背面貫穿基底導通孔110可具有寬度wBTSV小於或等於大約1um，且導電焊墊112可具有寬度wPad小於或等於大約2.0um。在這樣的實施例中，具有寬度wBTSV小於大約2.5um的背面貫穿基底導通孔110產生相對小的導電焊墊寬度wPad，其提供導電焊墊繞線的設計自由度及空間。
在一些實施例中，導電焊墊112可在多個方向延伸，例如導電焊墊112可在第一方向302和垂直於第一方向302的第二方向304延伸。在一些這樣的實施例中，背面貫穿基底導通孔110可接觸導電焊墊112y在第一方向302延伸的一段，而凸塊下金屬層118可接觸導電焊墊112在第二方向304延伸的一段。在其他一些這樣的實施例中，背面貫穿基底導通孔110及凸塊下金屬層118可接觸導電焊墊112在第一方向302延伸的多個段，這些段藉由導電焊墊112在第二方向304延伸的一或多段 分開。
第4圖係根據一些其它實施例繪示具有背面焊墊的三維積體晶片(three-dimensional integrated chip,3DIC)400。
三維積體晶片(3D-IC)400包括第一半導體晶片(die)402a，其係以設置黏著層404於兩者之間的方法耦合。耦合至第二半導體晶片402b。第一半導體晶片402a包括具有複數個半導體元件104的第一半導體基底406a。在一些實施例中，這些半導體元件104可藉由隔離結構405(例如淺溝槽隔離結構(shallow trench isolation structure))分開。複數個第一金屬互連層408a設置於第一層間介電結構410a中，其包括一或多個層間介電層披覆於第一半導體基底406a上。第二半導體晶片402b包括第二半導體基底406b及複數個第二金屬互連層408b設置於包括一或多個層間介電層的第二層間介電結構410b中。在一些實施例中，黏著層404包括氧化層，使得第一半導體晶片402a沿氧化層間的介面連接至第二半導體晶片402b。
這些金屬互連層408a和408b包括金屬線407及金屬接觸窗及/或導通孔409(包括接觸窗及/或導通孔409a、409a'、409b、409b'、409c及409c')。這些第一金屬互連層408a包括薄金屬線407a及具有比薄金屬線407a更大尺寸(例如寬度及/或高度)的厚金屬線407b。厚金屬線407b藉由一或多個薄金屬線407a與第一半導體基底406a分開。這些第二金屬互連層408b也包括薄金屬線407a’及具有比薄金屬線407a’更大尺寸的厚金屬線407b’。厚金屬線407b’藉由一或多個薄金屬線407a’與第二半導體基底406b分開。
貫穿介電導通孔(through dielectric via,TDV)412從這些第一金屬互連層408a延伸穿過第一半導體基底406a及黏著層404至這些第二金屬互連層408b中的一個。在一些實施例中，貫穿介電導通孔(TDV)412連接這些第一金屬互連層408a中的厚金屬線407b至這些第二金屬互連層408b中的厚金屬線407c’。
背面貫穿基底導通孔110連接至這些第二金屬互連層408b之薄金屬線407a’(例如薄金屬線407a’設置於厚金屬線407b’與第二半導體基底406b之間)。背面貫穿基底導通孔110延伸穿過第二半導體基底406b至沿第二半導體基底406b之背面設置的平坦導電焊墊112。平坦導電焊墊112更進一步連接至與導電凸塊120連接的凸塊下金屬層118。在一些實施例中，一個以上的背面貫穿基底導通孔110可平行連接於薄金屬線407a’與導電焊墊112之間。
第5-15圖係根據一些實施例顯示製造具有背面焊墊的積體晶片的方法之剖面圖500-1500。
如剖面圖500所示，提供半導體基底502。半導體基底502可為任何類型之半導體主體(包括矽、矽鍺(SiGe)、絕緣層上覆矽(SOI))，例如半導體晶圓及/或一或多個晶片於晶圓上，和任何其他類型的金屬層、元件、半導體及/或磊晶層等等與其結合。半導體基底502可包括具有第一摻雜類型(例如n型摻雜或p型摻雜)之本質摻雜的半導體基底。
複數個半導體元件104(例如電晶體元件)沿半導體基底502之正面502f形成。在一些實施例中，這些半導電元件 104藉由形成閘極結構於半導體基底502之上而形成。閘極結構可藉由形成閘極介電層104e於半導體基底502上，且接續地形成閘極電極層104g於閘極介電層104e之上而形成。閘極介電層104e及閘極電極層104g依照光微影(photolithography)製程接續地圖案化以形成閘極結構。源極區104s與汲極區104d可藉由磊晶製程或藉由佈植(implantation)製程選擇性地植入摻雜物質，例如硼(B)或磷(P)至半導體基底502而形成，摻雜物質可接續地藉由高溫熱退火(thermal anneal)驅動進入半導體基底502中。
如剖面圖600所示，後段製程金屬化堆疊形成於半導體基底502的正面502f之上。後段製程金屬化堆疊包括複數個金屬互連層106形成在位於半導體基底502的正面502f之上的層間介電結構108中，且這些金屬互連層106係連接至這些半導體元件104。
在一些實施例中，後段製程金屬化堆疊係藉由使用分別的沉積製程沉積獨立的層間介電層108a-108d而形成。在沉積後，在這些獨立的層間介電層108a-108d中的一個中蝕刻出導通孔洞及/或金屬溝槽。導電材料(例如銅、鎢及/或鋁)沉積於導通孔洞及/或金屬溝槽中，以形成金屬互連層106。在一些實施例中，可使用沉積製程在導通孔洞中形成晶種層，接著進行後續的電鍍製程(例如電鍍或無電電鍍(electroless plating)製程)，其形成金屬材料至填滿導通孔洞及/或金屬溝槽的厚度。在一些實施例中，可使用化學機械研磨(chemical mechanical polishing,CMP)製程從獨立的層間介電層 108a-108d之頂表面移除多餘的金屬材料。在各種實施例中，這些金屬互連層可藉由雙鑲崁(dual damascene)製程(已繪示)或單鑲崁(single damascene)製程(未繪示)形成。
如剖面圖700所示，降低半導體基底502之厚度，降低半導體基底502之厚度可讓後續形成的背面貫穿基底導通孔(例如形成於第9-11圖)具有較小的尺寸(例如小於或等於大約2.5um)，其可以減少導電焊墊的尺寸。在一些實施例中，在薄化半導體基底502之前，層間介電結構108可藉由黏著材料連接至承載基底(未繪示)，承載基底於薄化及接續的製程中提供支撐。半導體基底502可藉由蝕刻製程及/或機械研磨半導體基底502之背面502b來薄化。在一些實施例中，基底的厚度係從大約700um的第一厚度t1降低至範圍介於大約1um與10um之間的第二厚度t2。
如剖面圖800所示，高介電常數介電層202形成於半導體基底102的背面102b之上。在各種實施例中，高介電常數介電層202可包括例如氧化鋁(Al2O3)、五氧化二鉭(Ta2O5)、二氧化鈦(TiO2)、二氧化鋯(ZrO2)及/或氧化鉿(HfO)。在各種實施例中，高介電常數介電層202可藉由沉積製程(例如化學氣相沉積(CVD)製程、電漿輔助化學氣相沈積(PECVD)製程、原子層沉積(ALD)製程、物理氣相沉積(PVD)製程等)形成。高介電常數介電層202降低了半導體基底102之背面102b的粗糙度，藉此可改善裝置漏電。
介電層204及/或緩衝層206係接續地形成於高介電常數介電層202之上。在一些實施例中，介電層204可包括氧化 層，緩衝層206可包括氮化層。介電層204及/或緩衝層206可藉由沉積製程(例如CVD、PE-CVD、ALD、PVD等)形成。
如剖面圖900所示，形成背面貫穿基底導通孔的開口902。背面貫穿基底導通孔的開口902垂直地延伸穿過介電層204及/或緩衝層206、高介電常數介電層202、半導體基底102及部分的層間介電結構108至接觸這些金屬互連層106之薄的第一金屬線107a的位置。在一些實施例中，背面貫穿基底導通孔的開口902可根據遮罩層906選擇性地暴露基底於蝕刻劑904中而形成。在各種實施例中，遮罩層906可包括光阻或氮化物(例如Si3N4、SiN)，其使用光微影製程圖案化。在各種實施例中，蝕刻劑904可包括具有蝕刻化學性的乾蝕刻劑包括氟物質(例如四氟化碳(CF4)、三氟甲烷(CHF3)、八氟環丁烷(C4F8)等等)或濕蝕刻劑(例如氫氟酸(hydrofluoric acid,HF)或四甲基氫氧化銨(tetramethylammonium hydroxide,TMAH))。
如剖面圖1000所示，形成背面貫穿基底導通孔襯墊1002於背面貫穿基底導通孔的開口902中。背面貫穿基底導通孔襯墊1002沿背面貫穿基底導通孔的開口902之下表面及側壁延伸。在一些實施例中，背面貫穿基底導通孔襯墊1002可被侷限於背面貫穿基底導通孔的開口902中，而在其他一些實施例中，背面貫穿基底導通孔襯墊1002可從背面貫穿基底導通孔的開口902向外延伸至介電層204及/或緩衝層206之上。在一些實施例中，背面貫穿基底導通孔襯墊1002可藉由沉積製程(例如CVD、PE-CVD、ALD、PVD等等)形成。在其他一些實施例中，背面貫穿基底導通孔襯墊1002可藉由熱氧化(thermal oxidation)製程形成。在這樣的實施例中，背面貫穿基底導通孔襯墊1002可不延伸於介電層204及/或緩衝層206之上(亦即背面貫穿基底導通孔襯墊208的上表面在介電層204及/或緩衝層206的上表面之下)。在一些實施例中，背面貫穿基底導通孔襯墊1002可包括氧化物(例如二氧化矽(SiO2)。
背面貫穿基底導通孔的開口902接著以導電材料1004填充。在各種實施例中，導電材料1004可包括銅、鋁、鎢或相似的材料。在一些實施例中，導電材料1004可藉由沉積製程形成。在一些其它的實施例中，導電材料1004可藉由電鍍製程(例如電鍍及無電電鍍製程)形成。導電材料1004填滿背面貫穿基底導通孔的開口902且延伸於介電層204及/或緩衝層206的上表面之上。
如剖面圖1100所示，沿線段1102實施平坦化製程以移除導電材料(例如第10圖之1004)及/或覆蓋於介電層204及/或緩衝層206上的背面貫穿基底導通孔襯墊(例如第10圖之1002)。平坦化製程形成了平坦表面1104沿背面貫穿基底導通孔110和介電層204及/或緩衝層206延伸，平坦化製程將背面貫穿基底導通孔110及/或背面貫穿基底導通孔襯墊208侷限於背面貫穿基底導通孔的開口902中。在一些實施例中，平坦化製程可包括化學機械研磨(CMP)製程。在其他一些實施例中，平坦化製程可包括例如蝕刻製程及/或研磨製程。
如剖面圖1200所示，導電焊墊112係形成於平坦表面1104上，導電焊墊112係直接形成與背面貫穿基底導通孔110接觸，使得背面貫穿基底導通孔110物理性且電性地接觸導電 焊墊112。導電焊墊112可藉由沉積製程及/或電鍍製程，且接著進行光微影(lithographic)圖案化及蝕刻製程形成。
如剖面圖1300所示，形成一或多個保護層210及212於導電焊墊112之上，此一或多個保護層210及212從導電焊墊112之上延伸至介電層204及/或緩衝層206之上。在一些實施例中，此一或多個保護層210及212可包括介電層(又稱保護層210)及聚醯亞胺層(又稱保護層212)，此一或多個保護層210及212可藉由沉積製程形成，接著進行圖案化製程形成凸塊下金屬層的開口1302延伸穿過此一或多個保護層210及212至導電焊墊112的背面112b。
如剖面圖1400所示，凸塊下金屬層118形成於凸塊下金屬層的開口1302內。凸塊下金屬層118為不同金屬層118a及118b的堆疊，其作為擴散層、阻障層、潤濕層及/或抗氧化層。凸塊下金屬層118可藉由連續的沉積製程形成。
如剖面圖1500所示，導電凸塊120形成於凸塊下金屬層118上。在各種實施例中，導電凸塊120可包括焊料凸塊、銅凸塊、包含鎳(Ni)或金(Au)的金屬凸塊或前述的組合。在一些實施例中，積體晶片可被帶入接觸基底(例如印刷電路板(PCB))或封裝的導線架(lead frame)，接著焊球被回焊以形成與基底或導線架的電性連接。在積體晶片電性連接至基底或導線架之後，可移除承載基底及黏著層。
第16圖係根據一些實施例製造具有背面焊墊的積體晶片的方法之流程圖。雖然方法1600的描述與第5至15圖有關，應當理解的是，方法1600並不限定於這種結構，且可單獨 視為獨立於結構之方法。
所揭露之方法1600在下文中描述為一系列動作或事件，應可理解的是，這些的動作或事件的順序並不被限定的解釋。例如，一些動作可以依照不同順序發生及/或與本文中顯示及/或描述以外的其它動作或事件同時進行。此外，並非所有顯示的動作都需要用於實施於本文所描述之一或多個觀點或實施例。再者，本中所描述的一或多個行為皆可以一或多個分開的動作及/或階段實現。
在動作1602，沿半導體基底正面形成一或多個半導體元件。第5圖繪示一些對應於動作1602的實施例。
在動作1604，在沿半導體基底之正面設置的層間介電結構中形成複數個金屬互連層。第6圖繪示一些對應於動作1604的實施例。
在動作1606，降低半導體基底之厚度。第7圖繪示一些對應於動作1606的實施例。
在動作1608，沿半導體基底之背面形成高介電常數介電層。第8圖繪示一些對應於動作1608的實施例。
在動作1610，形成介電層及/或緩衝層於高介電常數介電層之上。第8圖繪示一些對應於動作1610的實施例。
在動作1612，形成背面貫穿基底導通孔的開口。背面貫穿基底導通孔的開口延伸穿過介電層及/或緩衝層、高介電常數介電層、半導體基底及部分的層間介電結構。背面貫穿基底導通孔可接觸設置於基底與厚金屬互連線之間的薄金屬互連線。第9圖繪示一些對應於動作1612的實施例。
在動作1614，形成背面貫穿基底導通孔襯墊於背面貫穿基底導通孔的開口中。第10圖繪示一些對應於動作1614的實施例。
在動作1616，以導電材料填充背面貫穿基底導通孔的開口。第10圖繪示一些對應於動作1616的實施例。
在動作1618，實施平坦化製程，以形成具有與介電層或緩衝層大抵共平面之上表面的背面貫穿基底導通孔。第11圖繪示一些對應於動作1618的實施例。
在動作1620，形成導電焊墊於背面貫穿基底導通孔之平坦表面上及介電層或緩衝層上。第12圖繪示一些對應於動作1620的實施例。
在動作1622，形成一或多個保護層於導電焊墊及介電層或緩衝層之上。第13圖繪示一些對應於動作1622的實施例。
在動作1624，於保護層內的開口中形成凸塊下金屬層位於接觸導電焊墊的位置上。第14圖繪示一些對應於動作1624的實施例。
在動作1626，形成導電凸塊於凸塊下金屬層上。第15圖繪示一些對應於動作1626的實施例。
因此，本揭露係有關於具有背面貫穿基底導通孔之積體晶片(IC)，其在金屬互連層與背面導電焊墊背面之間有直接的物理連接。
在一些實施例中，本揭露係有關於積體晶片。積體晶片包括複數個金屬互連層設置於沿基底之正面設置的層 間介電結構中，介電層沿基底之背面設置，導電焊墊設置於介電層之上，背面貫穿基底導通孔從該些金屬互連層中的一個延伸穿過基底及介電層至導電焊墊，導電凸塊設置於導電焊墊之上，導電焊墊具有平坦的下表面從背面貫穿基底導通孔之上延伸至導電凸塊之下。
在其他一些實施例中，本揭露係有關於積體晶片。積體晶片包括複數個金屬互連層設置於沿基底之正面設置的層間介電結構中，該些金屬互連層包括第一金屬互連線及藉由第一金屬互連線與基底分開的更厚的第二金屬互連線，高介電常數介電層設置於基底之背面上，介電層藉由高介電常數介電層與基底之背面分開，導電焊墊設置於介電層之上，背面貫穿基底導通孔延伸於第一金屬互連線與導電焊墊之間。
在其他一些實施例中，本揭露係有關於積體晶片的製造方法。積體晶片的製造方法包括形成複數個金屬互連層在沿基底之正面設置的層間介電結構中，該些金屬互連層包括第一金屬互連線及藉由第一金屬互連線與基底分開的更厚的第二金屬互連線。積體晶片的製造方法更包括形成高介電常數介電層於基底之背面上，以及形成介電層於高介電常數介電層之上。積體晶片的製造方法更包括蝕刻介電層、高介電常數介電層、基底及層間介電結構，以形成背面貫穿基底導通孔之開口，其延伸至與第一金屬互連線接觸的位置。積體晶片的製造方法更包括沉積導電材料於背面貫穿基底導通孔之開口中，以及實施平坦化製程移除背面貫穿基底導通孔開口外的導電材料，以形成背面貫穿基底導通孔。積體晶片的製造方法更包括 形成導電焊墊，其具有平坦的下表面設置於背面貫穿基底導通孔上。
以上概略說明了本揭露數個實施例的特徵部件，使所屬技術領域中具有通常知識者對於本揭露的概念可更為容易理解。所屬技術領域中具有通常知識者應瞭解到本說明書可作為其他結構或製程的變更或設計基礎，以實現相同於本揭露實施例的目的及/或獲得相同的優點。所屬技術領域中具有通常知識者也可理解與上述等同的結構或製程並未脫離本揭露之精神及保護範圍內，且可在不脫離本揭露之精神及範圍內，當可作更動、替代與潤飾。

Claims (14)

  1. 一種積體晶片，包括：複數個金屬互連層，設置於沿一基底之一正面設置的一層間介電結構中；一介電層，沿該基底之一背面設置；一導電焊墊，設置於該介電層之上；一背面貫穿基底導通孔，從該些金屬互連層中的一個延伸穿過該基底及該介電層至該導電焊墊；以及一導電凸塊，設置於該導電焊墊之上且與該背面貫穿基底導通孔面向該導電凸塊之方向的一最外側側壁在水平方向上錯開，其中該導電焊墊具有一平坦的下表面從該背面貫穿基底導通孔之上延伸至該導電凸塊之下。
  2. 如申請專利範圍第1項所述之積體晶片，更包括：一高介電常數介電層配置來降低該基底之該背面的粗糙度，其中該高介電常數介電層係縱向地設置於該介電層與該基底之間。
  3. 如申請專利範圍第1項所述之積體晶片，其中該背面貫穿基底導通孔具有複數個平滑的側壁連續地延伸於該些金屬互連層中的一個與該導電焊墊之間。
  4. 如申請專利範圍第1項所述之積體晶片，其中該些金屬互連層包括一第一金屬互連線及藉由該第一金屬互連線與該基底分開的一更厚的第二金屬互連線，且其中該背面貫穿基底導通孔接觸該第一金屬互連線。
  5. 如申請專利範圍第1項所述之積體晶片，更包括：一保護層設置於該介電層及該導電焊墊之上；以及一凸塊下金屬層從該保護層之上延伸至該保護層中的一開口內，其中該凸塊下金屬層係位於該導電焊墊與該導電凸塊之間。
  6. 如申請專利範圍第5項所述之積體晶片，其中該導電焊墊具有以一第一方向延伸的一第一段及以垂直於該第一方向的一第二方向延伸的一第二段，且其中該背面貫穿基底導通孔接觸該導電焊墊之該第一段，且該凸塊下金屬層接觸該導電焊墊之該第二段。
  7. 如申請專利範圍第1項所述之積體晶片，更包括：一背面貫穿基底導通孔襯墊沿該背面貫穿基底導通孔之側壁設置，以分開該背面貫穿基底導通孔與該基底。
  8. 如申請專利範圍第1項所述之積體晶片，更包括：一或多個額外背面貫穿基底導通孔設置為平行於該背面貫穿基底導通孔，該背面貫穿基底導通孔介於該些金屬互連層中的一個與該導電焊墊之間。
  9. 如申請專利範圍第1項所述之積體晶片，更包括：一緩衝層藉由該介電層與該基底分開，其中該背面貫穿基底導通孔具有背對該基底的一上表面，且該上表面與該介電層之背對該基底的一上表面或該緩衝層之背對該基底的一上表面共平面。
  10. 一種積體晶片，包括：複數個金屬互連層，設置於沿一基底之一正面設置的一層間介電結構中，其中該些金屬互連層包括一第一金屬互連線及藉由該第一金屬互連線與該基底分開的一更厚的第二金屬互連線；一高介電常數介電層，設置於該基底之背面上；一介電層，藉由該高介電常數介電層與該基底之該背面分開；一導電焊墊，設置於該介電層之上；以及一背面貫穿基底導通孔，延伸於該第一金屬互連線與該導電焊墊之間，其中該背面貫穿基底導通孔具有面向該第一金屬互連線之一第一表面和面向該導電焊墊之一第二表面，且該第一表面具有小於該第二表面之寬度。
  11. 如申請專利範圍第10項所述之積體晶片，更包括：一保護層設置於該介電層與該導電焊墊之上；一凸塊下金屬層從該保護層之上延伸至該保護層中的一開口內；以及一導電凸塊設置於該凸塊下金屬層之上，其中該導電焊墊具有一平坦的下表面從該背面貫穿基底導通孔之上延伸至該導電凸塊之下。
  12. 如申請專利範圍第10項所述之積體晶片，其中該背面貫穿基底導通孔具有複數個錐形的側壁連續地延伸於該第一金屬互連線與該導電焊墊之間。
  13. 如申請專利範圍第10項所述之積體晶片，其中該背面貫穿基底導通孔具有小於或等於2.5微米的寬度。
  14. 一種積體晶片的製造方法，包括：形成複數個金屬互連層在沿一基底之一正面設置的一層間介電結構中，其中該些金屬互連層包括一第一金屬互連線及藉由該第一金屬互連線與該基底分開的一更厚的第二金屬互連線；形成一高介電常數介電層於該基底之一背面上；形成一介電層於該高介電常數介電層之上；蝕刻該介電層、該高介電常數介電層、該基底及該層間介電結構，以形成一背面貫穿基底導通孔開口延伸至與該第一金屬互連線接觸的一位置；在形成該些金屬互連層後，沉積一導電材料於該背面貫穿基底導通孔開口之中；實施一平坦化製程移除該背面貫穿基底導通孔開口外的該導電材料，以形成一背面貫穿基底導通孔；以及形成一導電焊墊，具有一平坦下表面設置於該背面貫穿基底導通孔上。
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