CN112447530A - 芯片封装结构及其形成方法 - Google Patents

芯片封装结构及其形成方法 Download PDF

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Publication number
CN112447530A
CN112447530A CN202010869951.8A CN202010869951A CN112447530A CN 112447530 A CN112447530 A CN 112447530A CN 202010869951 A CN202010869951 A CN 202010869951A CN 112447530 A CN112447530 A CN 112447530A
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layer
pad
conductive
containing layer
chip
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陈昱寰
许国经
陈承先
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US16/893,467 external-priority patent/US11335634B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN112447530A publication Critical patent/CN112447530A/zh
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Abstract

提供芯片封装结构及其形成方法。此方法包含提供布线基底。此方法包含在第一焊垫上方依序形成含镍层和含金层。此方法包含形成导电保护层覆盖含镍层上方的含金层。此方法包含经由导电凸块和围绕导电凸块的助焊剂层将芯片接合至布线基底。导电凸块在第二焊垫和芯片之间。此方法包含在导电保护层覆盖含镍层的同时移除助焊剂层。

Description

芯片封装结构及其形成方法
技术领域
本发明实施例涉及半导体制造技术,特别涉及芯片封装结构及其形成方法。
背景技术
半导体装置用于各种电子应用中,例如个人电脑、手机、数码相机和其他电子设备。半导体装置的制造通常通过在半导体基底上方依序沉积绝缘层或介电层、导电层和半导体层,并使用光学微影工艺和蚀刻工艺将这些不同材料层图案化,以在半导体基底上形成电路组件和元件。
通常在半导体晶圆上制造许多集成电路。可以在晶圆级上处理和封装晶圆的晶粒,并且已开发了用于晶圆级封装的各种技术。
发明内容
根据一些实施例提供芯片封装结构的形成方法。此方法包含提供布线基底。布线基底包含基底、第一焊垫、第二焊垫和绝缘层。第一焊垫和第二焊垫分别在基底的第一表面和第二表面上方。绝缘层在第一表面上方并部分地覆盖第一焊垫,并且第一焊垫比第二焊垫宽。此方法包含在第一焊垫上方依序形成含镍层和含金层。此方法包含形成导电保护层覆盖含镍层上方的含金层。导电保护层、含金层和含镍层由不同的材料制成,并且绝缘层的第一顶表面与第一焊垫的第二顶表面之间的第一距离大于导电保护层的第三顶表面与第二顶表面之间的第二距离。此方法包含经由第一导电凸块和围绕第一导电凸块的第一助焊剂层将芯片接合至布线基底。第一导电凸块在第二焊垫和芯片之间并连接第二焊垫和芯片。此方法包含在导电保护层覆盖含镍层的同时移除第一助焊剂层。
根据另一些实施例提供芯片封装结构的形成方法。此方法包含提供布线基底。布线基底包含基底、第一焊垫、第二焊垫和绝缘层,第一焊垫和第二焊垫分别在基底的第一表面和第二表面上方,并且绝缘层在第一表面和第一焊垫上方且具有开口,开口部分地暴露出第一焊垫。此方法包含在开口中依序形成含镍层和含金层。此方法包含在含金层上方形成导电保护层,其中导电保护层的第一孔隙率小于含金层的第二孔隙率。此方法包含在导电保护层形成于含金层上方之后,经由第一导电凸块将芯片接合至布线基底的第二焊垫。此方法包含在将芯片接合至第二焊垫之后,在导电保护层上方形成导电结构。此方法包含使导电结构和导电保护层回焊,以将导电结构和导电保护层熔融并混合在一起,借此形成第二导电凸块。
根据又另一些实施例提供芯片封装结构。此芯片封装结构包含第一布线基底,第一布线基底包含基底、第一焊垫、第二焊垫和绝缘层,第一焊垫和第二焊垫分别位于基底的第一表面和第二表面上方,绝缘层在第一表面上方且部分地覆盖第一焊垫,并且第一焊垫比第二焊垫宽。此芯片封装结构包含在第一焊垫上方的含镍层。此芯片封装结构包含在含镍层上方的导电保护层。导电保护层包含锡,并且第一焊垫上方的导电保护层和绝缘层围绕凹槽。此芯片封装结构包含在基底的第二表面上方的芯片。此芯片封装结构包含在第二焊垫和芯片之间的导电凸块。
附图说明
通过以下的详细描述配合说明书附图,可以更加理解本发明实施例的内容。需强调的是,根据产业上的标准惯例,许多部件并未按照比例绘制。事实上,为了能清楚地讨论,各种部件的尺寸可能被任意地增加或减少。
图1A~图1M是根据一些实施例的用于形成芯片封装结构的工艺的各个阶段的剖面示意图。
图2A~图2B是根据一些实施例的用于形成芯片封装结构的工艺的各个阶段的剖面示意图。
图3是根据一些实施例的芯片封装结构的剖面示意图。
图4A~图4H是根据一些实施例的用于形成芯片封装结构的工艺的各个阶段的剖面示意图。
图5A~图5B是根据一些实施例的用于形成芯片封装结构的工艺的各个阶段的剖面示意图。
图6是根据一些实施例的芯片封装结构的剖面示意图。
图7是根据一些实施例的芯片封装结构的剖面示意图。
图8是根据一些实施例的芯片封装结构的剖面示意图。
图9是根据一些实施例的芯片封装结构的剖面示意图。
附图标记说明:
100,200,270,290,300,400,490,510,520,600,700,800,900:芯片封装结构
110,280,280a:布线基底
111:基底
111a,111b,178a:表面
112:贯穿基底导孔
113a,113b,114a,114b,284:布线层
115a,115b,288:焊垫
115b1,118a1,118b1,122a,132,262:顶表面
116a,116b,286:导电导孔
117a,117b,118a,118b,282:绝缘层
122:含镍层
124:含钯层
126:含金层
130:导电保护层
134:弯曲的顶表面
140,450:载体基底
150:导电层
160,190:助焊剂材料层
170:芯片
172:半导体基底
172a:前表面
172b:后表面
174:介电层
176:导电垫
178:互连层
180,210,260,410,480:导电凸块
220,420,460:助焊剂层
230,G:载体基底
240:底部填充层
250,440:模制层
260a:导电结构
289:弹性接触结构
430,470:装置
610,710,730:粘着层
620:散热盖
720:散热环
740:散热板
A:切割线
C:金属间化合物层
D1,D2,D3,D4:距离
E:槽
F:除焊溶液
P1,P2:开口
R1:凹槽
T1,T2,T3,T3’,T4,T5:厚度
W1,W2,W3,W4:宽度
具体实施方式
以下内容提供许多不同实施例或范例,用于实施本发明实施例的不同部件。组件和配置的具体范例描述如下,以简化本发明实施例。当然,这些仅仅是范例,并非用于限定本发明实施例。举例来说,叙述中若提及第一部件形成于第二部件上或上方,可能包含形成第一部件和第二部件直接接触的实施例,也可能包含额外的部件形成于第一部件和第二部件之间,使得第一部件和第二部件不直接接触的实施例。另外,本发明实施例在不同范例中可重复使用参考标号及/或字母。此重复是为了简化和清楚的目的,并非代表所讨论的不同实施例及/或组态之间有特定的关系。
此外,本文可能使用空间相对用语,例如“下方”、“之下”、“下”、“上方”、“上”及类似的用词,这些空间相对用语是为了便于描述如图所示的一个(些)元件或部件与另一个(些)元件或部件之间的关系。这些空间相对用语用于涵盖使用中或操作中的装置的不同方位,以及附图中所描述的方位。当装置被转向不同方位时(旋转90度或其他方位),则在此所使用的空间相对形容词也将依转向后的方位来解释。应理解的是,可以在方法之前、期间和之后提供额外的操作,并且对于方法的其他实施例,可以替换或消除所描述的一些操作。
描述本发明实施例中的一些实施例。可以在这些实施例中描述的阶段之前、期间及/或之后提供额外的操作。对于不同的实施例,可以替换或消除所描述的一些阶段。可以将额外的部件添加到半导体装置结构中。对于不同的实施例,可以替换或消除以下描述的一些部件。虽然以采用特定顺序进行的操作讨论一些实施例,但可以采用其他逻辑顺序来进行这些操作。
图1A~图1M是根据一些实施例的用于形成芯片封装结构的工艺的各个阶段的剖面示意图。根据一些实施例,如图1A所示,提供布线基底110。根据一些实施例,布线基底110包含基底111、贯穿基底导孔(或镀覆通孔(plated through holes,PTH))112、布线层113a、113b、114a和114b、焊垫115a和115b、导电导孔116a和116b以及绝缘层117a、117b、118a和118b。
根据一些实施例,基底111具有表面111a和111b。根据一些实施例,表面111a与表面111b相对。在一些实施例中,基底111由绝缘材料制成,例如纤维材料、聚合物材料或玻璃材料。举例来说,纤维材料包含玻璃纤维材料。
在一些其他实施例中,根据一些实施例,基底111由半导体材料或导电材料制成。举例来说,半导体材料包含硅或锗。举例来说,导电材料包含金属材料。
根据一些实施例,贯穿基底导孔112穿过基底111。根据一些实施例,分别在表面111a和111b上方形成布线层113a和113b。根据一些实施例,贯穿基底导孔112将布线层113a电连接到布线层113b。
根据一些实施例,如果基底111由半导体材料或导电材料制成,则在基底111与贯穿基底导孔112之间以及基底111与布线层113a和113b之间形成绝缘层(未示出),使基底111与贯穿基底导孔112以及布线层113a和113b电绝缘。
根据一些实施例,在表面111a上方形成布线层114a、焊垫115a、导电导孔116a以及绝缘层117a和118a。根据一些实施例,布线层114a和导电导孔116a在绝缘层117a中。根据一些实施例,焊垫115a在绝缘层117a上方。根据一些实施例,导电导孔116a在布线层113a和114a之间以及布线层114a和焊垫115a之间电连接。
根据一些实施例,在绝缘层117a和焊垫115a上方形成绝缘层118a。根据一些实施例,绝缘层118a具有开口P1。根据一些实施例,多个开口P1分别暴露出其下方的多个焊垫115a。根据一些实施例,绝缘层118a部分地覆盖焊垫115a。
根据一些实施例,在表面111b上方形成布线层114b、焊垫115b、导电导孔116b以及绝缘层117b和118b。根据一些实施例,布线层114b和导电导孔116b在绝缘层117b中。根据一些实施例,焊垫115b在绝缘层117b上方。根据一些实施例,导电导孔116b在布线层113b和114b之间以及布线层114b和焊垫115b之间电连接。
根据一些实施例,在绝缘层117b和焊垫115b上方形成绝缘层118b。根据一些实施例,绝缘层118b具有开口P2。根据一些实施例,多个开口P2分别暴露出多个焊垫115b。根据一些实施例,绝缘层118b部分地覆盖焊垫115b。
在一些实施例中,焊垫115b比焊垫115a宽。亦即,根据一些实施例,焊垫115b的宽度W1大于焊垫115a的宽度W2。根据一些实施例,焊垫115b用于与布线基底(例如印刷电路板)接合。根据一些实施例,焊垫115a用于与芯片接合。根据一些实施例,宽度W1在约200μm至约600μm的范围。根据一些实施例,宽度W2在约20μm至约110μm的范围。在一些实施例中,开口P2的(最大)宽度W3大于开口P1的(最大)宽度W4。
根据一些实施例,贯穿基底导孔112、布线层113a、113b、114a和114b、焊垫115a和115b以及导电导孔116a和116b由导电材料制成,例如金属材料或其合金。金属材料包含铝、铜或钨。
根据一些实施例,如图1B所示,在焊垫115b的顶表面115b1上方形成含镍层122。根据一些实施例,含镍层122覆盖顶表面115b1的整个露出部分,此露出部分由开口P2暴露出来。根据一些实施例,含镍层122在开口P2中。根据一些实施例,含镍层122由镍或其合金制成。根据一些实施例,含镍层122的形成使用镀覆工艺,例如无电镀(electroless plating)工艺。
根据一些实施例,如图1B所示,在含镍层122上方形成含钯层124。根据一些实施例,含钯层124在开口P2中。根据一些实施例,含钯层124具有在约0.02μm至约0.1μm的范围的厚度T1。根据一些实施例,含钯层124由钯或其合金制成。根据一些实施例,含钯层124的形成使用镀覆工艺,例如无电镀工艺。
根据一些实施例,如图1B所示,在含钯层124上方形成含金层126。根据一些实施例,含金层126在开口P2中。根据一些实施例,含金层126具有在约0.02μm至约0.1μm的范围的厚度T2。根据一些实施例,含金层126由金或其合金制成。根据一些实施例,含金层126的形成使用镀覆工艺,例如浸镀(immersion plating)工艺。
根据一些实施例,如图1B所示,在含金层126上方形成导电保护层130。在一些实施例中,导电保护层130的孔隙率低于含钯层124的孔隙率并且低于含金层126的孔隙率。亦即,根据一些实施例,导电保护层130具有比含钯层124和含金层126更致密的结构。
在一些实施例中,导电保护层130的厚度T3大于含钯层124的厚度T1和含金层126的厚度T2之和。在一些实施例中,导电保护层130比焊垫115b上方的绝缘层118b薄。
根据一些实施例,厚度T3在约1μm至约25μm的范围。根据一些实施例,厚度T3在约1μm至约10μm的范围。根据一些实施例,导电保护层130覆盖含镍层122的整个顶表面122a。
如果不形成导电保护层130,则含镍层122中的镍原子可能会受到后续除焊(deflux)工艺中使用的除焊溶液的影响,并且可能会迁移穿过含钯层124和含金层126并被氧化。由于导电保护层130比含钯层124和含金层126更致密且更厚,导电保护层130可以将含镍层122与除焊溶液隔开。因此,导电保护层130可以改善焊垫115b和导电凸块之间的粘着性,导电凸块随后形成并连接在焊垫115b和芯片之间。导电保护层130的形成可以增强导电凸块。
由于导电保护层130可以对含镍层122提供更强的保护,可以使用对于助焊剂(flux)层具有更强移除能力的除焊溶液来更澈底地移除助焊剂层。因此,可以提升助焊剂层的移除工艺的产率。
在一些实施例中,绝缘层118b的顶表面118b1与焊垫115b的顶表面115b1之间的距离D1大于导电保护层130的顶表面132与焊垫115b的顶表面115b1之间的距离D2。亦即,根据一些实施例,顶表面132低于顶表面118b1。
根据一些实施例,导电保护层130、含金层126、含钯层124和含镍层122由不同的材料制成。根据一些实施例,导电保护层130由金属材料(例如锡)或其合金(例如锡合金)制成。根据一些实施例,导电保护层130的形成使用印刷工艺或无电镀工艺。
根据一些实施例,如图1C所示,在导电保护层130上进行回焊工艺。在回焊工艺期间,将含金层126和含钯层124溶解在导电保护层130中,并在导电保护层130和含镍层122之间形成金属间化合物层C。根据一些实施例,金属间化合物层C可以改善导电保护层130和含镍层122之间的粘着性。
根据一些实施例,金属间化合物层C在结构上比导电保护层130、含金层126和含钯层124更致密。在一些实施例中,金属间化合物层C的厚度T4大于含钯层124的厚度T1和含金层126的厚度T2之和(如图1B所示)。因此,根据一些实施例,金属间化合物层C为含镍层122提供比含钯层124和含金层126更强的保护。结果,金属间化合物层C和导电保护层130可以在后续工艺期间一起保护含镍层122免于受到损坏。
根据一些实施例,金属间化合物层C由导电保护层130和含镍层122的材料制成。根据一些实施例,金属间化合物层C包含化合物材料。举例来说,化合物材料包含锡和镍,例如Ni3Sn4
根据一些实施例,在回焊工艺之后,导电保护层130具有(最大)厚度T3’。根据一些实施例,厚度T3’大于含钯层124的厚度T1和含金层126的厚度T2之和(如图1B所示)。根据一些实施例,厚度T3’大于厚度T3(如图1B所示)。
根据一些实施例,厚度T3’在约1μm至约25μm的范围。根据一些实施例,厚度T3’在约1μm至约10μm的范围。在一些实施例中,(回焊的)导电保护层130比焊垫115b上方的绝缘层118b薄。
根据一些实施例,导电保护层130具有弯曲的顶表面134。在一些实施例中,绝缘层118b的顶表面118b1与焊垫115b的顶表面115b1之间的距离D1大于弯曲的顶表面134与顶表面115b1之间的(最大)距离D3。
在一些实施例中,焊垫115b上方的导电保护层130和绝缘层118b围绕凹槽R1。根据一些实施例,在焊垫115b的一上方的整个导电保护层130在对应的开口P2中。亦即,根据一些实施例,导电保护层130没有延伸超出相应的开口P2,这避免导电保护层130在随后的工艺中接触载体基底。
用于避免导电保护层130在后续工艺中接触载体基底的设计包含导电保护层130比焊垫115b上方的绝缘层118b薄(如图1B所示)、顶表面132低于顶表面118b1(如图1B所示)、以及绝缘层118b的顶表面118b1与焊垫115b的顶表面115b1之间的距离D1大于弯曲的顶表面134和顶表面115b1之间的(最大)距离D3(如图1C所示)。在一些其他实施例中(未示出),根据设计需求,弯曲的顶表面134(或顶表面132)高于顶表面118b1。
根据一些实施例,如图1D所示,将布线基底110上下翻转并设置在载体基底140上方。根据一些实施例,载体基底140被配置为在随后的工艺步骤期间提供暂时的机械和结构支撑。根据一些实施例,载体基底140包含玻璃、氧化硅、氧化铝、金属、前述的组合或类似的材料。根据一些实施例,载体基底140包含金属框。
根据一些实施例,如图1D所示,在焊垫115a上方形成导电层150。根据一些实施例,导电层150包含焊球。根据一些实施例,导电层150由导电材料制成,例如金属(例如锡)或其合金(例如锡合金)。根据一些实施例,导电层150的形成包含在焊垫115a上方形成焊接材料层(未示出);以及使焊接材料层回焊以形成导电层150。
根据一些实施例,如图1E所示,在导电层150上方进行热压缩工艺以使导电层150的顶表面152变平。根据一些实施例,如图1F所示,在导电层150和绝缘层118a的顶表面118a1上方形成助焊剂材料层160。助焊剂材料层160用于在随后的芯片接合工艺中确保导电层150和芯片上方的导电凸块之间的接合,借此提升芯片接合工艺的产率。
在一些实施例中,助焊剂材料层160包含酒石酸(tartaric acid)、树脂、胺及/或溶剂。在一些实施例中,胺是烷基取代的胺(alkyl substituted amine)、乙醇胺(ethanolamine)、乙氧基化胺(ethoxylated amine)或丙氧基化胺(propoxylated amine)。在一些实施例中,使用界面活性剂,有时称为调流剂(flow modifier)。具体的界面活性剂取决于与助焊剂材料层160的相容性。在一些实施例中,界面活性剂是阴离子的,例如长链烷基羧酸,例如月桂酸(lauric acids)、硬脂酸(stearic acids)或类似的材料。根据一些实施例,使用浸渍(dipping)工艺或喷涂(jetting)工艺形成助焊剂材料层160。
根据一些实施例,如图1G所示,提供芯片170。根据一些实施例,芯片170包含半导体基底172、介电层174、导电垫176和互连层178。
根据一些实施例,半导体基底172具有前表面172a和与前表面172a相对的后表面172b。在一些实施例中,在前表面172a上方或邻近前表面172a的半导体基底172中形成主动元件(例如晶体管、二极管或类似的元件)及/或无源元件(例如电阻器、电容器、电感器或类似的元件)。
在一些实施例中,半导体基底172至少由元素半导体材料制成,包含单晶、多晶或非晶结构的硅或锗。在一些其他实施例中,半导体基底172由化合物半导体(例如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟)、合金半导体(例如SiGe或GaAsP)或前述的组合制成。半导体基底172还可以包含多层半导体、绝缘体上覆半导体(semiconductor on insulator,SOI)(例如绝缘体上覆硅或绝缘体上覆锗)或前述的组合。
根据一些实施例,介电层174形成在前表面172a上方。介电层174由聚合物材料制成,例如聚苯并
Figure BDA0002650747940000101
唑(polybenzoxazole,PBO)层、聚酰亚胺(polyimide)层、苯环丁烯(benzocyclobutene,BCB)层、环氧树脂(epoxy)层、感光材料层或其他合适的材料。
根据一些实施例,导电垫176形成在介电层174中。根据一些实施例,导电垫176电连接到在半导体基底172中/上方形成的装置(未示出)。根据一些实施例,导电垫176由导电材料制成,例如铜(Cu)、铜合金、铝(Al)、铝合金、钨(W)、钨合金、钛(Ti)、钛合金、钽(Ta)或钽合金。
根据一些实施例,互连层178形成在介电层174上方。根据一些实施例,互连层178包含介电层(未示出)和在介电层中的导电互连结构(未示出)。
根据一些实施例,如图1G所示,在互连层178上方形成导电凸块180。根据一些实施例,互连层178的导电互连结构电连接到导电凸块180和导电垫176。
根据一些实施例,导电凸块180由导电材料制成,例如锡(Sn)或其合金。在一些其他实施例中,导电凸块180由铜(Cu)、铜合金、铝(Al)、铝合金、钨(W)、钨合金、钛(Ti)、钛合金、钽(Ta)或钽合金制成。
根据一些实施例,如图1G所示,在导电凸块180和互连层178的表面178a上方形成助焊剂材料层190。助焊剂材料层190用于在随后的芯片接合工艺中确保导电凸块180与导电层150之间的接合(如图1F所示),借此提升芯片接合工艺的产率。
在一些实施例中,助焊剂材料层190包含酒石酸、树脂、胺及/或溶剂。在一些实施例中,胺是烷基取代的胺、乙醇胺、乙氧基化胺或丙氧基化胺。在一些实施例中,使用界面活性剂,有时称为调流剂。具体的界面活性剂取决于与助焊剂材料层190的相容性。在一些实施例中,界面活性剂是阴离子的,例如长链烷基羧酸,例如月桂酸、硬脂酸或类似的材料。根据一些实施例,使用浸渍工艺或喷涂工艺来形成助焊剂材料层190。
根据一些实施例,如图1H所示,芯片170经由导电凸块210和助焊剂层220接合至布线基底110。根据一些实施例,助焊剂层220围绕导电凸块210。
根据一些实施例,导电凸块210在焊垫115a和芯片170之间并连接焊垫115a和芯片170。根据一些实施例,导电凸块210由导电层150和导电凸块180形成。根据一些实施例,助焊剂层220由助焊剂材料层160和190形成。
根据一些实施例,导电保护层130比导电凸块210薄。亦即,根据一些实施例,导电保护层130的(最大)厚度T3’小于导电凸块210的厚度T5。
根据一些实施例,如图1I所示,移除助焊剂层220。根据一些实施例,助焊剂层220的移除工艺包含浸渍工艺或喷涂工艺。举例来说,根据一些实施例,在浸渍工艺中,将布线基底110浸入容纳在槽E中的除焊溶液F中。根据一些实施例,助焊剂层220可以溶解在除焊溶液F中。
根据一些实施例,导电保护层130和金属间化合物层C将含镍层122与除焊溶液F隔开。根据一些实施例,导电保护层130直接接触除焊溶液F。
根据一些实施例,除焊溶液F包含水性液体(例如去离子水)和溶剂,例如氢氟碳化物(hydrofluorocarbons,HFC’s)、氢氟氯碳化物(hydrochlorofluorocarbons,HCFC’s)、氟氯碳化物(chlorofluorocarbons)、醇、萜烯(terpenes)及前述的组合。
根据一些实施例,如图1J所示,布线基底110设置在载体基底230上方。根据一些实施例,载体基底230被配置为在随后的工艺步骤期间提供暂时的机械和结构支撑。根据一些实施例,载体基底230包含玻璃、氧化硅、氧化铝、金属、前述的组合等。根据一些实施例,载体基底230包含金属框。
根据一些实施例,如图1J所示,在芯片170和布线基底110之间形成底部填充层240。根据一些实施例,底部填充层240包含绝缘材料,例如聚合物材料。
根据一些实施例,如图1J所示,在布线基底110、芯片170和底部填充层240上方形成模制(molding)层250。根据一些实施例,模制层250封装芯片170。根据一些实施例,模制层250围绕芯片170、导电凸块210和底部填充层240。根据一些实施例,模制层250由绝缘材料制成,例如聚合物材料。
根据一些实施例,如图1K所示,将布线基底110上下翻转并设置在载体基底G上方。根据一些实施例,载体基底G被配置为在随后的工艺步骤期间提供暂时的机械和结构支撑。根据一些实施例,载体基底G包含玻璃、氧化硅、氧化铝、金属、前述的组合或类似的材料。根据一些实施例,载体基底G包含金属框。
根据一些实施例,如图1K所示,在导电保护层130上方形成导电结构260a。根据一些实施例,导电结构260a由导电材料制成,例如金属(例如Sn)或前述的合金。在一些实施例中,导电结构260a和导电保护层130由相同的导电材料制成,例如锡或锡合金。
根据一些实施例,如图1K和图1L所示,对导电结构260a和导电保护层130进行回焊工艺,以将导电结构260a和导电保护层130熔融并混合在一起,以形成导电凸块260。
在一些实施例中,导电凸块260的顶表面262与焊垫115b的顶表面115b1之间的距离D4大于绝缘层118b的顶表面118b1与顶表面115b1之间的距离D1。根据一些实施例,导电凸块260比导电凸块210更宽且更厚。因此,根据一些实施例,在后续工艺中,导电凸块260能够与具有比芯片170的焊垫更大的焊垫的布线基底接合。
根据一些实施例,如图1L所示,在布线基底110上方沿着切割线A进行切割工艺,以切割穿过布线基底110和模制层250以形成芯片封装结构270。
根据一些实施例,如图1M所示,芯片封装结构270经由导电凸块260接合至布线基底280。布线基底280包含印刷电路板或其他合适的布线基底。根据一些实施例,布线基底280包含绝缘层282、布线层284、导电导孔286和焊垫288。
根据一些实施例,布线层284和导电导孔286在绝缘层282中。根据一些实施例,焊垫288在绝缘层282上方。根据一些实施例,导电导孔286在布线层284之间以及在布线层284和焊垫288之间电连接。
根据一些实施例,布线层284、导电导孔286和焊垫288由导电材料制成,例如金属材料或前述的合金。金属材料包含铝、铜或钨。
根据一些实施例,在此步骤中,大致形成了芯片封装结构(或板级(board-level)封装结构)100。根据一些实施例,芯片封装结构100包含芯片封装结构270、导电凸块260和布线基底280。根据一些实施例,芯片封装结构100是球栅阵列(ball grid array,BGA)封装结构。
图2A至图2B是根据一些实施例的用于形成芯片封装结构的工艺的各个阶段的剖面示意图。根据一些实施例,如图2A所示,在图1J的步骤之后,在布线基底110上方沿着切割线A进行切割工艺,以切割穿过布线基底110和模制层250以形成芯片封装结构290。
根据一些实施例,如图2B所示,提供布线基底280a。根据一些实施例,布线基底280a类似于图1M的布线基底280,除了布线基底280a还包含弹性接触结构289。根据一些实施例,弹性接触结构289被安装到焊垫288。
根据一些实施例,如图2B所示,芯片封装结构290经由导电保护层130和弹性接触结构289接合至布线基底280a。根据一些实施例,弹性接触结构289直接接触导电保护层130。根据一些实施例,弹性接触结构289是弹性金属条。
根据一些实施例,在此步骤中,大致形成了芯片封装结构(或板级封装结构)200。根据一些实施例,芯片封装结构200包含芯片封装结构290和布线基底280a。根据一些实施例,芯片封装结构200是平面网格阵列(land grid array,LGA)封装结构。
图3是根据一些实施例的芯片封装结构(或板级封装结构)300的剖面示意图。根据一些实施例,如图3所示,芯片封装结构300类似于图2B的芯片封装结构200,除了芯片封装结构300的弹性接触结构289穿入导电保护层130。导电保护层130可以将弹性接触结构289固定到焊垫115b,以提升芯片封装结构300的产率。根据一些实施例,芯片封装结构300是平面网格阵列(LGA)封装结构。
图4A~图4H是根据一些实施例的用于形成芯片封装结构的工艺的各个阶段的剖面示意图。根据一些实施例,如图4A所示,在图1I的步骤之后,将布线基底110设置在载体基底230上方。根据一些实施例,如图4A所示,导电层150的一部分未接合至芯片170。
根据一些实施例,如图4A所示,在芯片170和布线基底110之间形成底部填充层240。根据一些实施例,如图4A所示,在导电层150的一部分和绝缘层118a的顶表面118a1上方形成助焊剂层420。
在一些实施例中,助焊剂层420包含酒石酸、树脂、胺及/或溶剂。在一些实施例中,胺是烷基取代的胺、乙醇胺、乙氧基化胺或丙氧基化胺。在一些实施例中,使用界面活性剂,有时称为调流剂。具体的界面活性剂取决于与助焊剂层420的相容性。在一些实施例中,界面活性剂是阴离子的,例如长链烷基羧酸,例如月桂酸、硬脂酸或类似的材料。根据一些实施例,使用浸渍工艺或喷涂工艺来形成助焊剂层420。
根据一些实施例,如图4B所示,装置430经由导电凸块410接合至布线基底110。根据一些实施例,导电凸块410由导电层150的一部分部分地形成。根据一些实施例,装置430包含主动装置或例如电阻器、电容器或电感器的被动装置。
根据一些实施例,如图4C所示,使用除焊工艺移除助焊剂层420。根据一些实施例,如图4C所示,在布线基底110、芯片170、底部填充层240、装置430和导电凸块410上方形成模制层440。根据一些实施例,模制层440封装芯片170和装置430。
根据一些实施例,模制层440围绕芯片170、导电凸块210、底部填充层240、装置430和导电凸块410。根据一些实施例,模制层440由绝缘材料制成,例如聚合物材料。
根据一些实施例,如图4D所示,将布线基底110上下翻转并设置在载体基底450上方。根据一些实施例,载体基底450被配置为在随后的工艺步骤期间提供暂时的机械和结构支撑。根据一些实施例,载体基底450包含玻璃、氧化硅、氧化铝、金属、前述的组合或类似的材料。根据一些实施例,载体基底450包含金属框。
根据一些实施例,如图4D所示,在导电保护层130的一部分上方形成助焊剂层460。在一些实施例中,助焊剂层460包含酒石酸、树脂、胺及/或溶剂。在一些实施例中,胺是烷基取代的胺、乙醇胺、乙氧基化胺或丙氧基化胺。
在一些实施例中,使用界面活性剂,有时称为调流剂。具体的界面活性剂取决于与助焊剂层460的相容性。在一些实施例中,界面活性剂是阴离子的,例如长链烷基羧酸,例如月桂酸、硬脂酸或类似的材料。根据一些实施例,使用浸渍工艺或喷涂工艺来形成助焊剂层460。
根据一些实施例,如图4E所示,装置470经由导电凸块480接合至布线基底110。根据一些实施例,导电凸块480由导电保护层130的一部分部分地形成。根据一些实施例,装置470包含主动装置或例如电阻器、电容器或电感器的被动装置。
根据一些实施例,如图4F所示,使用除焊工艺移除助焊剂层460。根据一些实施例,如图4G所示,进行图1K~图1L的步骤以形成导电凸块260并形成芯片封装结构(或板级封装结构)400。根据一些实施例,如图4H所示,进行图1M的步骤以经由导电凸块260将芯片封装结构400接合至布线基底280。
根据一些实施例,在此步骤中,大致形成了芯片封装结构490。根据一些实施例,芯片封装结构490包含芯片封装结构400、导电凸块260和布线基底280。根据一些实施例,芯片封装结构490是球栅阵列(BGA)封装结构。
图5A~图5B是根据一些实施例的用于形成芯片封装结构的工艺的各个阶段的剖面示意图。根据一些实施例,如图5A所示,在图4F的步骤之后,在布线基底110上方沿着切割线A进行切割工艺,以切割穿过布线基底110和模制层440以形成芯片封装结构510。
根据一些实施例,如图5B所示,芯片封装结构510经由导电保护层130和弹性接触结构289接合至布线基底280a。根据一些实施例,弹性接触结构289直接接触导电保护层130。根据一些实施例,弹性接触结构289是弹性金属条。根据一些实施例,弹性接触结构289穿入导电保护层130。
根据一些实施例,在步骤中,大致形成了芯片封装结构(或板级封装结构)520。根据一些实施例,芯片封装结构520包含芯片封装结构510和布线基底280a。根据一些实施例,芯片封装结构520是平面网格阵列(LGA)封装结构。
图6是根据一些实施例的芯片封装结构600的剖面示意图。根据一些实施例,如图6所示,芯片封装结构600类似于图1M的芯片封装结构100,除了芯片封装结构600还具有粘着层610和散热盖620。根据一些实施例,芯片封装结构600没有芯片封装结构100的模制层250。
根据一些实施例,粘着层610形成在布线基底110上方。根据一些实施例,粘着层610围绕芯片170和底部填充层240。根据一些实施例,粘着层610具有环形形状。根据一些实施例,散热盖620设置在芯片170和粘着层610上方。
根据一些实施例,粘着层610由聚合物制成,例如环氧树脂或聚硅氧(silicone)。根据一些实施例,使用分配(dispensing)工艺来形成粘着层610。根据一些实施例,散热盖620由高导热率的材料制成,例如金属材料(铝或铜)、合金材料(例如不锈钢)或铝碳化硅(AlSiC)。
图7是根据一些实施例的芯片封装结构700的剖面示意图。根据一些实施例,如图7所示,芯片封装结构700类似于图1M的芯片封装结构100,除了芯片封装结构700还具有粘着层710、散热环720、粘着层730和散热板740。根据一些实施例,芯片封装结构700没有芯片封装结构100的模制层250。
根据一些实施例,粘着层710形成在布线基底110上方。根据一些实施例,粘着层710围绕芯片170和底部填充层240。根据一些实施例,粘着层710具有环形形状。根据一些实施例,散热环720设置在粘着层710上。
根据一些实施例,粘着层730形成在散热环720上。根据一些实施例,粘着层730具有环形形状。根据一些实施例,散热板740设置在粘着层730和芯片170上方。
根据一些实施例,粘着层710和730由聚合物制成,例如环氧树脂或聚硅氧。根据一些实施例,使用分配工艺来形成粘着层710和730。
根据一些实施例,散热环720和散热板740由高导热率的材料制成,例如金属材料(铝或铜)、合金材料(例如不锈钢)或铝碳化硅(AlSiC)。
图8是根据一些实施例的芯片封装结构800的剖面示意图。根据一些实施例,如图8所示,芯片封装结构800类似于图3的芯片封装结构300,除了芯片封装结构800还具有粘着层610和散热盖620。
根据一些实施例,芯片封装结构800没有芯片封装结构300的模制层250。根据一些实施例,弹性接触结构289穿过导电保护层130。根据一些实施例,弹性接触结构289直接接触金属间化合物层C。
根据一些实施例,粘着层610形成在布线基底110上方。根据一些实施例,粘着层610围绕芯片170和底部填充层240。根据一些实施例,粘着层610具有环形形状。根据一些实施例,散热盖620设置在芯片170和粘着层610上方。
根据一些实施例,粘着层610由聚合物制成,例如环氧树脂或聚硅氧。根据一些实施例,使用分配工艺来形成粘着层610。根据一些实施例,散热盖620由高导热率的材料制成,例如金属材料(铝或铜)、合金材料(例如不锈钢)或铝碳化硅(AlSiC)。
图9是根据一些实施例的芯片封装结构900的剖面示意图。根据一些实施例,如图9所示,芯片封装结构900类似于图3的芯片封装结构300,除了芯片封装结构900还具有粘着层710、散热环720、粘着层730和散热板740。根据一些实施例,芯片封装结构900没有芯片封装结构300的模制层250。
根据一些实施例,粘着层710形成在布线基底110上方。根据一些实施例,粘着层710围绕芯片170和底部填充层240。根据一些实施例,粘着层710具有环形形状。根据一些实施例,散热环720设置在粘着层710上方。
根据一些实施例,粘着层730形成在散热环720上方。根据一些实施例,粘着层730具有环形形状。根据一些实施例,散热板740设置在粘着层730和芯片170上方。
根据一些实施例,粘着层710和730由聚合物制成,例如环氧树脂或聚硅氧。根据一些实施例,使用分配工艺来形成粘着层710和730。
根据一些实施例,散热环720和散热板740由高导热率的材料制成,例如金属材料(铝或铜)、合金材料(例如不锈钢)或铝碳化硅(AlSiC)。
用于形成芯片封装结构200、300、490、520、600、700、800和900的工艺和材料可以与前述用于形成芯片封装结构100的那些工艺相似或相同。
根据一些实施例,提供芯片封装结构及其形成方法。(用于形成芯片封装结构的)方法在回焊工艺之前在焊垫上方的含镍层上方形成导电保护层,以保护含镍层在回焊工艺期间不被氧化。因此,改善焊垫与随后在焊垫与芯片之间形成的导电凸块之间的粘着性。结果,提升芯片封装结构的产率。
根据一些实施例,提供芯片封装结构的形成方法。此方法包含提供布线基底。布线基底包含基底、第一焊垫、第二焊垫和绝缘层。第一焊垫和第二焊垫分别在基底的第一表面和第二表面上方。绝缘层在第一表面上方并部分地覆盖第一焊垫,并且第一焊垫比第二焊垫宽。此方法包含在第一焊垫上方依序形成含镍层和含金层。此方法包含形成导电保护层覆盖含镍层上方的含金层。导电保护层、含金层和含镍层由不同的材料制成,并且绝缘层的第一顶表面与第一焊垫的第二顶表面之间的第一距离大于导电保护层的第三顶表面与第一焊垫的第二顶表面之间的第二距离。此方法包含经由导电凸块和围绕导电凸块的助焊剂层将芯片接合至布线基底。导电凸块在第二焊垫和芯片之间。此方法包含在导电保护层覆盖含镍层的同时移除助焊剂层。
在一些实施例中,此方法还包含:在将芯片接合至布线基底之前,回焊导电保护层,其中含金层溶解在导电保护层中,并且在导电保护层和含镍层之间形成金属间化合物层。
在一些实施例中,在回焊导电保护层之后,导电保护层具有弯曲的顶表面。
在一些实施例中,导电保护层覆盖含镍层的第四顶表面整个。
在一些实施例中,此方法还包含:在形成含金层于第一焊垫上方之前,在含镍层上方形成含钯层,其中含金层形成在含钯层上方。
在一些实施例中,绝缘层具有开口暴露出第一焊垫的一部分,含镍层、含钯层和含金层在开口中且覆盖所述部分,并且导电保护层整个在开口中。
在一些实施例中,此方法还包含:在将芯片接合至布线基底之前,在第二焊垫上方形成导电层,其中第一导电凸块的一部分由导电层形成。
在一些实施例中,布线基底还包含在第一表面上方的第三焊垫,含镍层、含金层和导电保护层更形成在第三焊垫上方,此方法还包含:在移除第一助焊剂层之后,经由第二导电凸块和围绕第二导电凸块的第二助焊剂层将装置接合至第三焊垫,其中第二导电凸块由第三焊垫上方的导电保护层部分地形成;以及移除第二助焊剂层。
在一些实施例中,第一助焊剂层的移除包含使用除焊溶液以移除第一助焊剂层,并且导电保护层将含镍层与除焊溶液隔开。
在一些实施例中,导电保护层比含金层致密。
根据一些实施例,提供用于形成芯片封装结构的方法。此方法包含提供布线基底。布线基底包含基底、第一焊垫、第二焊垫和绝缘层,第一焊垫和第二焊垫分别在基底的第一表面和第二表面上方,并且绝缘层在第一表面和第一焊垫上方且具有开口,开口部分地暴露出第一焊垫。此方法包含在开口中依序形成含镍层和含金层。此方法包含在含金层上方形成导电保护层,其中导电保护层的第一孔隙率小于含金层的第二孔隙率,并且导电保护层比第一焊垫上方的绝缘层薄。此方法包含在导电保护层形成于含金层上方之后,经由第一导电凸块将芯片接合至布线基底的第二焊垫。此方法包含在将芯片接合至第二焊垫之后,在导电保护层上方形成导电结构。此方法包含使导电结构和导电保护层回焊,以将导电结构和导电保护层熔融并混合在一起,借此形成第二导电凸块。
在一些实施例中,导电保护层比第一焊垫上方的绝缘层薄。
在一些实施例中,导电结构和导电保护层由相同材料制成。
在一些实施例中,导电保护层比含金层厚。
在一些实施例中,第一焊垫比第二焊垫宽,并且第二导电凸块比第一导电凸块更宽且更厚。
根据一些实施例,提供芯片封装结构。此芯片封装结构包含第一布线基底,第一布线基底包含基底、第一焊垫、第二焊垫和绝缘层,第一焊垫和第二焊垫分别位于基底的第一表面和第二表面上方,绝缘层在第一表面上方且部分地覆盖第一焊垫,并且第一焊垫比第二焊垫宽。此芯片封装结构包含在第一焊垫上方的含镍层。此芯片封装结构包含在含镍层上方的导电保护层。导电保护层包含锡,并且第一焊垫上方的导电保护层和绝缘层围绕凹槽。此芯片封装结构包含在基底的第二表面上方的芯片。此芯片封装结构包含在第二焊垫和芯片之间的导电凸块。
在一些实施例中,此芯片封装结构还包含:第二布线基底,其中第一布线基底在第二布线基底上方,第二布线基底包含第二基底和安装到第二基底的弹性接触结构,并且弹性接触结构直接接触导电保护层。
在一些实施例中,弹性接触结构是弹性金属条。
在一些实施例中,弹性接触结构穿入导电保护层。
在一些实施例中,此芯片封装结构还包含:在导电保护层和含镍层之间的金属间化合物层,其中金属化合物层包含锡和镍。
以上概述数个实施例的部件,使得本技术领域中技术人员可以更加理解本发明实施例的面向。本技术领域中技术人员应该理解,他们能以本发明实施例为基础,设计或修改其他工艺和结构,以达到与在此介绍的实施例相同的目的及/或优点。本技术领域中技术人员也应该理解到,此类等效的结构并未悖离本发明实施例的构思与范围,且他们能在不违背本发明实施例的构思和范围下,做各式各样的改变、取代和调整。

Claims (10)

1.一种芯片封装结构的形成方法,包含:
提供一布线基底,包括一基底、一第一焊垫、一第二焊垫和一绝缘层,其中该第一焊垫和该第二焊垫分别在该基底的一第一表面和一第二表面上方,该绝缘层在该第一表面上方并部分地覆盖该第一焊垫,并且该第一焊垫比该第二焊垫宽;
在该第一焊垫上方依序形成一含镍层和一含金层;
形成一导电保护层覆盖该含镍层上方的该含金层,其中该导电保护层、该含金层和该含镍层由不同的材料制成,并且该绝缘层的一第一顶表面与该第一焊垫的一第二顶表面之间的一第一距离大于该导电保护层的一第三顶表面与该第二顶表面之间的一第二距离;
经由一第一导电凸块和围绕该第一导电凸块的一第一助焊剂层将一芯片接合至该布线基底,其中该第一导电凸块在该第二焊垫和该芯片之间并连接该第二焊垫和该芯片;以及
在该导电保护层覆盖该含镍层的同时,移除该第一助焊剂层。
2.如权利要求1的芯片封装结构的形成方法,还包括:
在将该芯片接合至该布线基底之前,回焊该导电保护层,其中该含金层溶解在该导电保护层中,并且在该导电保护层和该含镍层之间形成一金属间化合物层。
3.如权利要求1的芯片封装结构的形成方法,还包括:
在形成该含金层于该第一焊垫上方之前,在该含镍层上方形成一含钯层,其中该含金层形成在该含钯层上方。
4.如权利要求1的芯片封装结构的形成方法,其中该布线基底还包括在该第一表面上方的一第三焊垫,该含镍层、该含金层和该导电保护层更形成在该第三焊垫上方,该方法还包括:
在移除该第一助焊剂层之后,经由一第二导电凸块和围绕该第二导电凸块的一第二助焊剂层将一装置接合至该第三焊垫,其中该第二导电凸块由该第三焊垫上方的该导电保护层部分地形成;以及
移除该第二助焊剂层。
5.如权利要求1的芯片封装结构的形成方法,其中该第一助焊剂层的移除包括使用一除焊溶液以移除该第一助焊剂层,并且该导电保护层将该含镍层与该除焊溶液隔开。
6.一种芯片封装结构的形成方法,包含:
提供一布线基底,包括一基底、一第一焊垫、一第二焊垫和一绝缘层,其中该第一焊垫和该第二焊垫分别在该基底的一第一表面和一第二表面上方,并且该绝缘层在该第一表面和该第一焊垫上方且具有一开口部分地暴露出该第一焊垫;
在该开口中依序形成一含镍层和一含金层;
在该含金层上方形成一导电保护层,其中该导电保护层的一第一孔隙率小于该含金层的一第二孔隙率;
在该导电保护层形成于该含金层上方之后,经由一第一导电凸块将一芯片接合至该布线基底的该第二焊垫;
在将该芯片接合至该第二焊垫之后,在该导电保护层上方形成一导电结构;以及
使该导电结构和该导电保护层回焊,以将该导电结构和该导电保护层熔融并混合在一起,借此形成一第二导电凸块。
7.如权利要求6的芯片封装结构的形成方法,其中该导电保护层比该第一焊垫上方的该绝缘层薄。
8.一种芯片封装结构,包括:
一第一布线基底,包括一基底、一第一焊垫、一第二焊垫和一绝缘层,该第一焊垫和该第二焊垫分别位于该基底的一第一表面和一第二表面上方,该绝缘层在该第一表面上方且部分地覆盖该第一焊垫,并且该第一焊垫比该第二焊垫宽;
一含镍层,在该第一焊垫上方;
一导电保护层,在该含镍层上方,其中该导电保护层包括锡,并且该第一焊垫上方的该导电保护层和该绝缘层围绕一凹槽;
一芯片,在该基底的该第二表面上方;以及
一导电凸块,在该第二焊垫和该芯片之间。
9.如权利要求8的芯片封装结构,还包括:
一第二布线基底,其中该第一布线基底在该第二布线基底上方,该第二布线基底包括一第二基底和安装到该第二基底的一弹性接触结构,并且该弹性接触结构直接接触该导电保护层。
10.如权利要求9的芯片封装结构,其中该弹性接触结构穿入该导电保护层。
CN202010869951.8A 2019-08-30 2020-08-26 芯片封装结构及其形成方法 Pending CN112447530A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113517263A (zh) * 2021-07-12 2021-10-19 上海先方半导体有限公司 一种堆叠结构及堆叠方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113517263A (zh) * 2021-07-12 2021-10-19 上海先方半导体有限公司 一种堆叠结构及堆叠方法

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