TWI656581B - 使用具有微柱的半導體晶粒來形成直接晶片接合平面柵格陣列封裝之半導體裝置及方法 - Google Patents

使用具有微柱的半導體晶粒來形成直接晶片接合平面柵格陣列封裝之半導體裝置及方法 Download PDF

Info

Publication number
TWI656581B
TWI656581B TW105129584A TW105129584A TWI656581B TW I656581 B TWI656581 B TW I656581B TW 105129584 A TW105129584 A TW 105129584A TW 105129584 A TW105129584 A TW 105129584A TW I656581 B TWI656581 B TW I656581B
Authority
TW
Taiwan
Prior art keywords
semiconductor die
substrate
layer
semiconductor
contact pad
Prior art date
Application number
TW105129584A
Other languages
English (en)
Other versions
TW201727772A (zh
Inventor
沙亞莫希 奇努薩米
魏新 談
板安卓
客坤 侯
Original Assignee
美商先科公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商先科公司 filed Critical 美商先科公司
Publication of TW201727772A publication Critical patent/TW201727772A/zh
Application granted granted Critical
Publication of TWI656581B publication Critical patent/TWI656581B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/11452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81024—Applying flux to the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一種半導體裝置係具有一被設置在一基板之上的第一半導體晶粒。複數個複合的互連結構係被形成在該半導體晶粒之上。該些複合的互連結構係具有一非可熔的導電柱以及一被形成在該非可熔的導電柱之上的可熔的層。該可熔的層係被回焊，以將該第一半導體晶粒連接至該基板的一導電層。該非可熔的導電柱在回焊期間並不會熔化，此係消除在該基板之上形成一阻焊劑的需要。一密封劑係被沉積在該第一半導體晶粒以及複合的互連結構的周圍。該密封劑係流動在該第一半導體晶粒的主動表面與該基板之間。一第二半導體晶粒係相鄰該第一半導體晶粒而被設置在該基板之上。一散熱片係被設置在該第一半導體晶粒之上。該密封劑的一部分係被移除以露出該散熱片。

Description

使用具有微柱的半導體晶粒來形成直接晶片接合平面柵格陣列封裝之半導體裝置及方法
本發明係大致有關於半導體裝置，並且更具體而言係有關於一種利用具有微柱的半導體晶粒來形成一直接晶片接合平面柵格陣列(DCALGA)封裝之半導體裝置及方法。
半導體裝置係常見於現代的電子產品中。半導體裝置係在電氣構件的數目及密度上變化。離散的半導體裝置一般包含一類型的電氣構件，例如是發光二極體(LED)、小信號電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效電晶體(MOSFET)。集積的半導體裝置通常包含數百到數百萬個電氣構件。集積的半導體裝置的例子係包含微控制器、微處理器以及各種的信號處理電路。
半導體裝置係執行廣範圍的功能，例如是信號處理、高速的計算、傳送及接收電磁信號、控制電子裝置、轉換太陽光成為電力、以及產生用於電視顯示器的視覺影像。半導體裝置係見於娛樂、通訊、電力轉換、網路、電腦以及消費者產品的領域中。半導體裝置亦見於軍事的應用、航空、汽車、工業用的控制器、以及辦公室設備中。
半導體裝置係利用半導體材料的電氣特性。半導體材料的結構係容許該材料的導電度能夠藉由一電場或基極電流的施加或是透過摻雜的製程來加以操縱。摻雜係將雜質帶入半導體材料中，以操縱及控制半導體裝置的導電度。
一半導體裝置係包含主動及被動的電性結構。包含雙載子及場效電晶體的主動結構係控制電流的流動。藉由改變摻雜的程度以及一電場或基極電流的施加，該電晶體不是提升、就是限制電流的流動。包含電阻器、電容器及電感器的被動結構係在電壓及電流之間產生執行各種電性功能所必要的一種關係。該被動及主動結構係電連接以形成電路，此係使得該半導體裝置能夠執行高速的運算及其它有用的功能。
半導體裝置一般是利用兩個複雜的製程，亦即前端製造及後端製造來加以製造，每個製造潛在涉及數百道步驟。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。每一個半導體晶粒通常是相同的，並且包含藉由電連接主動及被動構件所形成的電路。後端製造係牽涉到從完成的晶圓單粒化(singulating)個別的半導體晶粒並且封裝該晶粒以提供結構的支撐、電互連以及環境的隔離。如同在此所用的術語"半導體晶粒"係指該字的單數與複數形兩者，並且於是可以指稱單一半導體裝置以及多個半導體裝置兩者。
半導體製造的一目標是產出較小的半導體裝置。較小的裝置通常消耗較低的功率，具有較高的效能，並且可以更有效率地加以生產。此外，較小的半導體裝置具有一較小的覆蓋區，此係較小的終端產品所期望的。降低的封裝輪廓對於在智慧型手機、可穿戴的技術、以及物聯網(IoT) 產業中的封裝而言是尤其重要的。較小的半導體晶粒尺寸可藉由在產生具有較小且較高密度的主動及被動構件之半導體晶粒的前端製程中的改良來達成。後端製程可以藉由在電互連及封裝材料上的改良來產生具有較小覆蓋區的半導體裝置封裝。
較小的半導體裝置的製造係依賴對於在一半導體晶粒與下面的基板之間、以及在被設置於單一基板上的多個半導體晶粒之間的水平及垂直的電互連實施的改良。一覆晶封裝係藉由用一覆晶的朝向來將一半導體晶粒安裝到一基板而被形成。該基板係提供在該半導體晶粒與外部的裝置之間的電互連。然而，在用於目前的覆晶封裝的封裝高度及處理量的時間上的縮減係受限於該基板的厚度以及被形成在該覆晶與基板之間的互連的高度。
對於減小封裝尺寸及製造時間，同時增加效能速度及可靠度係存在著需求。於是，在一實施例中，本發明是一種製造一半導體裝置之方法，其係包括提供一基板、設置一包含一複合的互連結構的第一半導體晶粒，該複合的互連結構係包括在該基板之上的一可熔的部分以及非可熔的部分、回焊該複合的互連結構的該可熔的部分、以及在該第一半導體晶粒的周圍沉積一密封劑的步驟。
在另一實施例中，本發明是一種製造一半導體裝置之方法，其係包括提供一基板、設置一包含一複合的互連結構的第一半導體晶粒，該複合的互連結構係包括在該基板之上的一可熔的部分以及非可熔的部分、以及回焊該複合的互連結構的該可熔的部分的步驟。
在另一實施例中，本發明是一種半導體裝置，其係包括一基板以及一包含一複合的互連結構的第一半導體晶粒，該複合的互連結構係被設置在該基板之上。一密封劑係被沉積在該第一半導體晶粒的周圍。
在另一實施例中，本發明是一種半導體裝置，其係包括一基板以及一包含一複合的互連結構的第一半導體晶粒，該複合的互連結構係被設置在該基板之上。
100‧‧‧半導體晶圓
102‧‧‧基底基板材料
104‧‧‧半導體晶粒
106‧‧‧切割道
108‧‧‧背表面
110‧‧‧主動表面
112‧‧‧導電層/接觸墊
114‧‧‧鈍化層
116‧‧‧圖案化層(光阻層)
117‧‧‧開口
118‧‧‧導電柱導電
120‧‧‧導電層
122‧‧‧微柱
124‧‧‧雷射切割工具
130‧‧‧半導體晶粒
132‧‧‧絕緣層
134‧‧‧半導體晶粒
136‧‧‧導電層
138‧‧‧絕緣層
140‧‧‧基板
142‧‧‧絕緣材料
144‧‧‧導電層
146、148‧‧‧表面
149‧‧‧助焊劑材料
150‧‧‧模具底膠填充(MUF)材料
152‧‧‧切割裝置
154‧‧‧DCALGA封裝
160‧‧‧DCALGA封裝
162‧‧‧導電層/散熱片
164‧‧‧絕緣層
166‧‧‧MUF材料
168‧‧‧表面
170‧‧‧DCALGA封裝
H1‧‧‧高度
圖1a-1f是描繪一種形成具有微柱的半導體晶粒之方法；圖2是描繪一具有微柱的半導體晶粒；圖3是描繪一具有被形成在一絕緣層之上的微柱的半導體晶粒；圖4是描繪一具有被形成在一RDL之上的微柱的半導體晶粒；圖5a-5f是描繪一種利用具有微柱的半導體晶粒來形成一DCALGA封裝之方法；圖6a-6b是描繪一包含一具有微柱的半導體晶粒的DCALGA封裝；圖7是描繪一DCALGA封裝，其係包含一散熱片以及多個具有微柱的半導體晶粒；以及圖8是描繪一DCALGA封裝，其係包含一被露出的散熱片以及多個具有微柱的半導體晶粒。
本發明係在以下參考該些圖式的說明中，以一或多個實施例來加以描述，其中相同的元件符號係代表相同或類似的元件。儘管本發明 係以用於達成本發明之目的之最佳模式來加以描述，但熟習此項技術者將會體認到的是，本揭露內容係欲涵蓋可內含在藉由以下的揭露內容及圖式所支持之所附的申請專利範圍及其等同項所界定的本發明的精神與範疇內的替換物、修改以及等同物。
半導體裝置一般是利用兩個複雜的製程：前端製造及後端製造來加以製造。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。在該晶圓上的每一個晶粒係包含電連接以形成功能電路的主動及被動電性構件。例如是電晶體及二極體的主動電性構件係具有控制電流流動的能力。例如是電容器、電感器及電阻器的被動電性構件係產生執行電路功能所必要的電壓及電流之間的一種關係。
被動及主動構件係藉由一系列的製程步驟而形成在半導體晶圓的表面之上，該些製程步驟包含摻雜、沉積、微影、蝕刻及平坦化。摻雜係藉由例如是離子植入或熱擴散的技術以將雜質帶入半導體材料中。該摻雜製程係藉由響應於一電場或基極電流來動態地改變該半導體材料的導電度以修改主動元件中的半導體材料的導電度。電晶體係包含具有不同類型及程度的摻雜的區域，該些區域係以使得該電晶體在電場或基極電流的施加時提升或限制電流的流動所必要的來加以配置。
主動及被動構件係藉由具有不同電氣特性的材料層來加以形成。該些層可藉由各種沉積技術來形成，該些技術部分是由被沉積的材料類型所決定的。例如，薄膜沉積可能牽涉到化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解的電鍍以及無電的電鍍製程。每一個層一般是被圖案化，以形成主動構件、被動構件或是構件間的電連接的部分。
後端製造係指切割或單粒化完成的晶圓成為個別的半導體晶粒，並且接著為了結構的支撐、電互連以及環境的隔離來封裝該半導體晶粒。為了單粒化該半導體晶粒，晶圓係沿著該晶圓的非功能區域(稱為切割道或劃線)來被劃線且截斷。該晶圓係利用一雷射切割工具或鋸刀而被單粒化。在單粒化之後，該個別的半導體晶粒係被安裝到一封裝基板，該封裝基板係包含用於和其它系統構件互連的接腳或接觸墊。形成在半導體晶粒之上的接觸墊係接著連接至該封裝內的接觸墊。該些電連接可以利用導電層、凸塊、柱形凸塊、導電膏、或是引線接合來做成。一密封劑或是其它模製材料係沉積在該封裝之上，以提供實體支撐及電性隔離。該完成的封裝係接著被插入一電性系統中，並且使得該半導體裝置的功能為可供其它系統構件利用的。
圖1a係展示一具有一種基底基板材料102的半導體晶圓100，例如是矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、碳化矽、或是其它用於結構的支撐的基體半導體材料。複數個半導體晶粒(或構件)104係被形成在半導體晶圓100上。半導體晶粒104係藉由如上所述的一非主動的晶粒間的晶圓區域或切割道106來加以分開。切割道106係提供切割區域以將半導體晶圓100單粒化成為個別的半導體晶粒104。
圖1b係展示半導體晶圓100的一部分的橫截面圖。每一個半導體晶粒104係具有一背表面(或非主動表面)108以及一包含類比或數位電路的主動表面110，該類比或數位電路係被實施為形成在該晶粒內並且根據該晶粒的電性設計及功能來電互連的主動元件、被動元件、導電層、以及介電層。例如，該電路係包含一或多個電晶體、二極體、以及其它電路 元件，其係被形成在主動表面110內以實施類比電路或數位電路，其例如是數位信號處理器(DSP)、ASIC、MEMS、記憶體、或是其它的信號處理電路。半導體晶粒104亦可包含例如是電感器、電容器及電阻器之整合的被動元件(IPD)，以用於射頻(RF)信號處理。
一導電層112係利用PVD、CVD、電解的電鍍、無電的電鍍製程、或是其它適合的金屬沉積製程而被形成在主動表面110上。導電層112係包含一或多層的鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鈀(Pd)、SnAg、SnAgCu、CuNi、CuNiAu、CuNiPdAu、或是其它適合的導電材料、或是其之組合。導電層112係運作為電連接至在主動表面110上的電路之接觸墊。接觸墊112係使得在半導體晶粒104內的主動電路與例如是印刷電路板(PCB)的外部的裝置之間的電互連變得容易。
一絕緣或鈍化層114係利用PVD、CVD、網版印刷、旋轉塗覆、噴霧塗覆、燒結、或是熱氧化，而被形成在主動表面110以及接觸墊112之上。鈍化層114係包含一或多層的二氧化矽(SiO2)、矽氮化物(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、鋁氧化物(Al2O3)、鉿氧化物(HfO2)、苯環丁烯(BCB)、聚醯亞胺(PI)、聚苯並噁唑(PBO)、聚合物、或是其它具有類似絕緣及結構的性質之材料。鈍化層114係覆蓋主動表面110，並且提供保護給主動表面110。鈍化層114係被形成在接觸墊112之上以及周圍，以用於電性隔離。複數個開口係藉由蝕刻、雷射直接剝蝕(LDA)、或是其它適當的製程，而被形成在接觸墊112之上的鈍化層114中。在鈍化層114中的開口係露出接觸墊112以用於後續的電互連。
在圖1c中，一圖案化或光阻層116係利用印刷、旋轉塗覆、 噴霧塗覆、或是其它適當的方法，而被形成在鈍化層114以及接觸墊112之上。光阻層116的一部分係藉由蝕刻、LDA、或是其它適當的製程來加以移除，以形成開口117。開口117係被形成在鈍化層114以及接觸墊112之上。開口117露出接觸墊112，並且延伸至接觸墊112。在一實施例中，圖案化的開口117係具有一圓形的橫截面的區域，其被配置以形成具有一包含圓形的橫截面之圓柱形的形狀的導電柱。在另一實施例中，圖案化的開口117係具有一矩形的橫截面的區域，其被配置以形成具有一包含矩形的橫截面之立方體形狀的導電柱。
在圖1d中，一種導電材料係利用一蒸鍍、濺鍍、電解的電鍍、無電的電鍍、網版印刷製程而沉積在開口117之內以及在接觸墊112之上，以形成導電柱(或圓柱)118。導電柱118包含一或多層的Al、Cu、Sn、鈦(Ti)、Ni、Au、Ag、鎢(W)、或是其它適當的導電材料。在一實施例中，導電柱118係藉由在光阻層116的圖案化的開口117中電鍍Cu來加以形成。導電柱118係電連接至接觸墊112。
一導電層(或凸塊材料)120係利用一蒸鍍、電解的電鍍、無電的電鍍、球式滴落、或是網版印刷製程，而沉積在導電柱118之上。導電層120係電性傳導的且包含Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、或是其之組合。導電柱118以及導電層120的組合係構成一複合的互連結構或是微柱122，其係具有一非可熔的部分(導電柱118)以及一可熔的部分(導電層120)。在一實施例中，導電柱118是一Cu柱，並且導電層120是SnAg。在另一實施例中，導電柱118是Cu，並且導電層120係包含一Ni以及SnAg。
在圖1e中，光阻層116係藉由一蝕刻製程來加以移除，以 留下個別的微柱122。微柱122可以具有一帶有圓形或橢圓形的橫截面之圓柱形的形狀、或者是微柱122可以具有一帶有矩形的橫截面之立方體形狀。微柱122係具有一50微米(μm)或更小的高度H1，並且具有一50μm或更小的直徑。微柱122係代表一種類型的可被形成在半導體晶粒104之上的互連結構。該互連結構亦可以使用凸塊、導電膏、柱形凸塊、或是其它的電互連。
在圖1f中，半導體晶圓100係藉由利用一鋸刀或是雷射切割工具124來切割穿過切割道106，而被單粒化成為個別的半導體晶粒104。圖2是展示在單粒化之後的半導體晶粒104。微柱122係被形成在接觸墊112之上，並且電連接至接觸墊112。
圖3是展示一類似於圖2中的半導體晶粒104之半導體晶粒130。半導體晶粒130係包含一被形成在鈍化層114之上的絕緣(或鈍化層)132。絕緣層132係利用PVD、CVD、網版印刷、旋轉塗覆、噴霧塗覆、燒結、或是熱氧化，而被形成在鈍化層114以及接觸墊112之上。絕緣層132係包含一或多層的PI、SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PBO、聚合物、或是其它具有類似絕緣及結構的性質之材料。絕緣層132的一部分係被移除以形成複數個露出接觸墊112的開口。在絕緣層132中的開口係比在鈍化層114中的開口更小的，亦即更窄的。絕緣層132的一部分係被設置在鈍化層114中的開口內，並且接觸到接觸墊112的表面。
微柱122係被形成在絕緣層132以及接觸墊112的露出的部分之上。微柱122的導電柱118係電連接至接觸墊112。導電層120係被形成在導電柱118之上。在一實施例中，一具有一黏著層、阻障層、以及晶 種或潤濕層的凸塊下金屬化(UBM)係被形成在導電柱118與接觸墊112之間。絕緣層132係提供電性絕緣以及應力釋放給在主動表面110之上的微柱122。
圖4是展示一類似於圖3中的半導體晶粒130的半導體晶粒134。半導體晶粒134係包含一導電層136。導電層136係利用一圖案化及金屬沉積製程，例如是PVD、CVD、濺鍍、電解的電鍍、以及無電的電鍍，而被形成在絕緣層132以及接觸墊112之上。導電層136係包含一或多層的Al、Cu、Sn、Ni、Au、Ag、Ti、TiW、W、或是其它適當的導電材料或是其之組合。導電層136的一部分係電連接至半導體晶粒134的接觸墊112。根據半導體晶粒134的設計及功能，導電層136的其它部分是電性共通或電性隔離的。導電層136係運作為一重分佈層(RDL)，以重分佈橫向地橫跨半導體晶粒134的電連接，亦即導電層136係重分佈從接觸墊112至半導體晶粒134的主動表面110之上的其它區域的電連接。
一絕緣(或鈍化)層138係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、燒結、或是熱氧化，而被形成在絕緣層132以及導電層136之上。絕緣層138係包含一或多層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、PI、BCB、PBO、或是其它具有類似絕緣及結構的性質之材料。絕緣層138的一部分係藉由蝕刻、LDA、或是其它適當的製程來加以移除，以露出導電層136的部分。
微柱122係被形成在絕緣層138以及導電層136的露出的部分之上。微柱122的導電柱118係電連接至導電層136。導電層120係被形成在導電柱118之上。在一實施例中，一具有一黏著層、阻障層、以及晶 種或潤濕層的UBM係被形成在導電柱118與導電層136之間。導電層136係重分佈橫跨半導體晶粒134的信號，並且容許微柱122的位置及佈局能夠被選擇以鏡射在任何基板或引線架上的接觸墊的位置及佈局。
圖5a-5f係描繪一種利用一具有微柱的半導體晶粒來形成一DCALGA封裝之方法。圖5a係展示一基板(或PCB)140的一部分的橫截面圖，其係包含絕緣材料142以及導電層144。在一實施例中，基板140係包含一或多個疊層的層之具有酚醛棉紙、環氧樹脂、樹脂、玻璃布、磨砂玻璃、聚酯、以及其它強化纖維或織物的一組合之預浸料、FR-4、FR-1、CEM-1、或是CEM-3。基板140亦可以是一引線架、多層的撓性積層、銅箔、或是包含一主動表面的半導體晶圓，該主動表面係包含一或多個電晶體、二極體、以及其它電路元件以實施類比電路或數位電路。
該絕緣材料142係包含一或多層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PI、PBO、聚合物、或是其它具有類似的結構及絕緣性質的介電材料。導電層144係包含Al、Cu、Sn、Ni、Au、Ag、Ti、W、或是其它適當的導電材料，其係利用一圖案化及金屬沉積製程，例如是濺鍍、電解的電鍍、以及無電的電鍍而被形成。導電層144係包含橫向的RDL以及垂直的導電貫孔，其係提供橫向地橫跨基板140以及垂直地在基板140的相對的表面146及148之間的電互連。根據該半導體晶粒以及其它接著安裝到基板140的裝置的設計及功能，導電層144的部分是電性共通或電性隔離的。導電層144在表面146上的部分係設置接觸墊，以供半導體晶粒及構件被安裝在表面146之上。導電層144在表面148上的部分係形成引線，以供在基板140與例如是PCB的外部的裝置之間的電互連。
在圖5b中，來自圖2的半導體晶粒104係在主動表面110被定向成朝向基板140的表面146下，例如是利用一拾放操作而被設置在基板140之上。一助焊劑材料149係被設置在微柱122的導電層120之上。助焊劑材料149係在將半導體晶粒104設置於基板140上之前，藉由將微柱122浸漬在一助焊劑床中來加以沉積。在一實施例中，如同在圖5c中所示，一助焊劑材料151係被形成在基板140的導電層144之上。
圖5d係展示被安裝到基板140的半導體晶粒104。導電層120係為了回焊而被帶往與導電層144的接觸墊實體接觸。微柱122的導電層120係被回焊，以電性及冶金地連接至基板140的導電層144。導電層120係在利用熱或是壓力的施加來回焊之際，形成一電性及冶金連接至導電層144的接觸墊。導電柱118係被固定到半導體晶粒104的接觸墊112。導電柱118在回焊期間並不會熔化或是變形。在一實施例中，導電柱118係利用一種具有比導電層120的材料更高的熔化溫度的材料而被形成。導電柱118係在半導體晶粒104與基板140之間提供一間隙。導電柱118的高度係被選擇以在半導體晶粒104與基板140的表面146之間維持一固定的偏移或間隔的距離。
在只有微柱122的導電層120在回焊期間熔化之下，在導電層144以及基板140的表面146之上並不需要一阻焊劑或是焊料遮罩。在只有導電層120在回焊期間熔化之下，在回焊期間所產生的液態的材料的體積係被減低。藉由微柱122所採用導電層120的小量的可熔材料係降低被熔化的材料在回焊期間擴散在導電層144的相鄰的部分之間的風險，亦即該導電層120中經減低的被熔化的可熔材料的體積係避免在導電層144的相鄰 的線路之間形成導電的橋或是短路。消除在基板140之上形成一焊料遮罩的需求係簡化基板140的製程，並且減小製造時間及成本。消除阻焊劑層亦最小化基板140的一厚度，亦即最小化在基板140的相對的表面146及148之間的距離。
在圖5e中，一密封劑或是模具底膠填充(MUF)材料150係利用一真空模製、膏印刷、壓縮模製、轉移模製、液體密封劑模製、旋轉塗覆、或是其它適當的施加製程，而被沉積在半導體晶粒104以及基板140之上。MUF材料150是聚合物複合材料，例如是具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有適當的填充物的聚合物。MUF材料150是非導電的，並且在環境上保護半導體晶粒104免於外部的元素及污染物。
MUF材料150係被設置在半導體晶粒104的背表面108之上，並且沿著半導體晶粒104的四個側表面來加以設置。MUF材料150係流動在微柱122的周圍，並且被設置在半導體晶粒104的主動表面110與基板的表面146之間。MUF材料150的填充物尺寸係被選擇以容許MUF材料150能夠流動在半導體晶粒104的主動表面110與基板140的表面146之間。在一實施例中，MUF材料150係在一後續的背面研磨步驟中被薄化，以露出背表面108、或者是在背表面108之上留下一降低厚度的MUF材料150。或者是，背表面108係藉由控制MUF材料150的沉積以避免MUF材料150流動在背表面108之上，而從MUF材料150被露出。
在圖5f中，切割裝置152(例如鋸刀或是雷射切割裝置)係切割穿過MUF材料150以及基板140，以單粒化個別的DCALGA封裝154。 圖6a係展示在單粒化之後的DCALGA封裝154。半導體晶粒104係經由微柱122來電連接至基板140的導電層144。半導體晶粒104係在本實施例中被舉例來使用，來自圖3的半導體晶粒130或是來自圖4的半導體晶粒134可被用來形成DCALGA封裝154。導電層144係根據半導體晶粒104的設計及功能來提供橫向地橫跨基板140以及垂直地穿過基板140的電互連。導電層144在基板140的表面148上的部分係形成平面柵格陣列(LGA)的引線，並且提供在DCALGA封裝154與例如是PCB的外部的裝置之間的互連。
圖6b係展示在半導體晶粒104的一微柱122與基板140的導電層144之間的互連的細節。導電柱118係被固定到半導體晶粒104的接觸墊112。導電層120係被設置在導電柱118與基板140的表面146上的導電層144的接觸墊之間。導電層120係在導電柱118與導電層144的接觸墊之間形成一電性及冶金連接。導電層120的回焊是在被選擇以避免導電柱118在回焊期間熔化或變形的一溫度及壓力下加以執行的。導電柱118係在半導體晶粒104與基板140的表面146之間提供一固定的偏移。
微柱122可以在一比例如是焊料凸塊更窄的間距下加以形成，因為只有導電層120係在回焊期間被熔化。相對於熔化整個互連結構，亦即導電柱118及導電層120，只熔化導電層120係減低在回焊期間的液態材料的體積，並且避免被熔化的材料擴散在導電層144的相鄰的線路之間。只熔化導電層120係減小電性短路的發生，並且增加DCALGA封裝154的可靠度。微柱122之縮減的間距亦容許較大數量的微柱122能夠被形成在半導體晶粒104之上。於是，具有增大的輸入/輸出密度需求的半導體晶粒及裝置可被納入到DCALGA封裝154中。
採用具有微柱122的半導體晶粒104係消除在基板140的表面146之上形成一焊料遮罩或是阻焊劑層的需求。基板140並不需要焊料遮罩，因為由微柱122所採用的可熔材料(亦即導電層120的材料)之減低的體積並不會冒著在回焊期間，在導電層144的相鄰的線路之間擴散的風險。消除在基板140之上形成一焊料遮罩的需求係簡化被用來形成基板140的製程。消除該焊料遮罩的形成步驟亦減小用於基板140的製造時間，其係增加處理量並且減小DCALGA封裝154的整體成本。此外，從基板140消除一焊料遮罩層係降低基板140的厚度以及DCALGA封裝154的整體厚度。
將具有微柱122的半導體晶粒104直接安裝至基板140的導電層144係最小化互連的距離。最小化互連的距離係增加封裝速度。將具有微柱122的半導體晶粒104直接安裝至基板140的導電層144亦最小化封裝的寄生元件，例如是寄生電阻、電容及電感(RLC)。在一實施例中，導電層120係由無鉛的材料所構成的，以提供一種綠色的對環境友善的互連結構。再者，導電層120的第一回焊係在將半導體晶粒104設置在該基板140之上後加以執行的。消除在晶圓層級，亦即在單粒化半導體晶圓100之前的回焊操作係降低製造時間。消除在該晶圓層級的一回焊操作亦增加裝置可靠度，因為降低在半導體晶粒104之上所執行的回焊操作的數目係最小化半導體晶粒104所遭受到的加熱週期的數目。最小化加熱週期的數目係降低翹曲及裝置失效的風險。因此，DCALGA封裝154係提供一較薄的封裝，其係具有增大的可靠度、較快的效能速度、以及一具有降低成本的簡化的製程。
圖7是描繪一DCALGA封裝160，其係包含一散熱片以及 多個具有微柱的半導體晶粒。來自圖2的半導體晶粒104係在主動表面110被定向朝向基板140的表面146下，利用例如是一拾放操作而被設置在基板140之上。在一實施例中，基板140是一引線架。一助焊劑材料係在安裝半導體晶粒104之前被設置在微柱122之上、或是在基板140的導電層144之上。半導體晶粒104係在本實施例中被舉例使用，而來自圖3的半導體晶粒130及/或來自圖4的半導體晶粒134亦可被用來形成DCALGA封裝160。
微柱122的導電層120係被設置在基板140的表面146上的導電層144的接觸墊之上。導電柱118係被固定到半導體晶粒104的接觸墊112。導電層120係被回焊並且形成一電性及冶金連接至表面146上的導電層144的接觸墊。導電柱118在回焊期間並不會熔化或是變形。導電柱118係在半導體晶粒104與基板140之間提供一固定的偏移。導電柱118的高度係被選擇以維持在半導體晶粒104與基板140的表面146之間的偏移或是間隔的距離。半導體晶粒104係經由導電層144來電連接至彼此。
在回焊期間只有微柱122的導電層120熔化之下，在導電層144以及基板140的表面146之上並不需要一阻焊劑或是焊料遮罩。在微柱122的回焊期間所產生的液態的材料的降低的體積並不會冒著在回焊期間，在導電層144的相鄰的線路之間擴散的風險，亦即在被熔化時，導電層120將不會在導電層144的相鄰的線路之間形成導電的橋或是短路。消除在基板140之上形成一焊料遮罩的需求係簡化用於基板140的製程，並且減小製造時間及成本。簡化該製程以及減少製造時間係增加DCALGA封裝160的處理量。從在基板140的表面146之上消除阻焊劑層亦降低基板140的厚度以及DCALGA封裝160的整體厚度。
一導電層162係被形成在該些半導體晶粒104中的至少一個之上。一種黏著材料、熱介面材料(TIM)、或是絕緣層164係被設置在導電層162與半導體晶粒104的背表面108之間。導電層162係電連接至基板140的導電層144。在一實施例中，導電層162係作用為一散熱片，以強化從半導體晶粒104的散熱並且改善DCALGA封裝160的熱效能。導電層162是Cu、Al、或是其它具有高導熱度的材料。在另一實施例中，導電層162係連接至接地並且作用為一屏蔽層，以阻擋或吸收EMI、RFI、諧波失真、以及其它的干擾。在半導體晶粒104之上形成一屏蔽層係改善DCALGA封裝160的電性效能。
一密封劑或是MUF材料166係利用一真空模製、膏印刷、壓縮模製、轉移模製、液體密封劑模製、旋轉塗覆、或是其它適當的施加製程，而被沉積在半導體晶粒104、散熱片162、以及基板140之上。MUF材料166是聚合物複合材料，例如是具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有適當的填充物的聚合物。MUF材料166是非導電的，並且在環境上保護半導體晶粒以及其它構件免於外部的元素及污染物。
MUF材料166係被設置在散熱片162之上、在半導體晶粒104的背表面108之上、以及在半導體晶粒104的側表面的周圍。MUF材料166係流動在散熱片162以及微柱122的周圍。MUF材料166係被設置在半導體晶粒104的主動表面110與基板140的表面146之間。MUF材料166的填充物尺寸係被選擇以容許MUF材料166能夠流動在相鄰的半導體晶粒104之間、以及在半導體晶粒104與基板140之間。
一類似於切割裝置152的鋸刀或是雷射切割裝置係被用來切割穿過MUF材料166以及基板140，以單粒化個別的DCALGA封裝160。圖7是展示在單粒化之後的DCALGA封裝160。半導體晶粒104係經由微柱122來電連接至基板140的導電層144。導電層144係根據半導體晶粒104的設計及功能來提供橫向地橫跨基板140以及垂直地穿過基板140的電互連。導電層144在基板140的表面148上的部分係形成LGA引線，並且提供在DCALGA封裝160與例如是PCB的外部的裝置之間的互連。
微柱122的導電柱118係被固定到半導體晶粒104的接觸墊112。微柱122的導電層120係被設置在導電柱118與在基板140的表面146上的導電層144的接觸墊之間。在被回焊時，導電層120係在導電柱118與導電層144的接觸墊之間形成一電性及冶金連接。導電柱118在回焊期間並不會熔化或是變形。導電柱118係在半導體晶粒104與基板140的表面146之間提供一固定的偏移。微柱122的間距可被縮減，因為只有導電層120係在回焊期間熔化。相對於熔化整個互連結構，亦即導電柱118以及導電層120，只熔化導電層120係減小在回焊期間的液態的材料的體積，並且避免被熔化的材料擴散在導電層144的相鄰的線路之間。因此，只熔化導電層120係減低電性短路的發生，並且增加DCALGA封裝160的可靠度。微柱122的縮減的間距亦容許較大數量的微柱122能夠被形成在半導體晶粒104之上。於是，具有增大的輸入/輸出密度需求的半導體晶粒及裝置可以被納入到DCALGA封裝160中。
基板140並不需要在導電層144以及基板140的表面146之上的一阻焊劑或是焊料遮罩，因為由微柱122所採用導電層120中小量的可 熔材料並不會在回焊期間，冒著在導電層144的相鄰的線路之間擴散的風險，亦即導電層120的被熔化材料將不會在導電層144的相鄰的線路之間造成導電的橋或是短路。消除在基板140之上形成一焊料遮罩的需求係簡化用於基板140的製程。消除在基板140之上形成一焊料遮罩的需求係減小製造時間及成本，此係增加處理量。消除一焊料遮罩層亦降低基板140的厚度以及DCALGA封裝160的整體厚度。
將具有微柱122的半導體晶粒104直接安裝至基板140的導電層144係最小化互連的距離，此係增加封裝速度。電連接在基板140之上的多個半導體晶粒係增加DCALGA封裝160的效能及功能。將具有微柱122的半導體晶粒104直接安裝至基板140的導電層144係最小化封裝的寄生元件，例如是寄生的RLC。在一實施例中，微柱122的導電層120係由無鉛的材料所構成的，以提供一綠色的對環境友善的互連結構。再者，導電層120的第一回焊係在將半導體晶粒104設置於該基板140之上之後加以執行。消除在該晶圓層級，亦即在單粒化半導體晶圓100之前的一回焊操作係降低製造時間並且增加裝置可靠度，因為減少在半導體晶粒104之上所執行的回焊操作的數目係減少半導體晶粒104所遭受到的加熱週期的數目。最小化在半導體晶粒104之上所執行的加熱週期的數目係降低翹曲以及裝置失效的風險。散熱片162係進一步增進DCALGA封裝160的熱效能以及可靠度。DCALGA封裝160係提供一較薄的封裝，其具有增大的可靠度、較快的效能速度、簡化的製程、以及降低的成本。
圖8是描繪一DCALGA封裝170，其係具有多個具有微柱122的半導體晶粒104以及一被露出的散熱片162。在DCALGA封裝170中， MUF材料166的一部分係在一背面研磨操作中被移除。該背面研磨操作係降低MUF材料166在半導體晶粒104的背表面108之上的一厚度，並且露出散熱片162。在背面研磨之後，MUF材料166的表面168係與散熱片162的表面共平面的。或者是，MUF材料166的沉積係被控制以避免MUF材料166流動在散熱片162之上。被露出的散熱片162係耗散由半導體晶粒104所產生的熱。散熱片162可被設置在DCALGA封裝170中的一個或是全部的半導體晶粒104之上。被露出的散熱片162係增進DCALGA封裝170的熱效能以及可靠度。在沉積MUF材料166之後，一類似於切割裝置152的鋸刀或是雷射切割裝置係被用來切割穿過MUF材料166以及基板140，並且單粒化個別的DCALGA封裝170。
圖8是展示在單粒化之後的DCALGA封裝170。半導體晶粒104係透過導電層144來加以電連接。導電層144係根據半導體晶粒104的設計及功能來提供橫向地橫跨基板140以及垂直地穿過基板140的電互連。導電層144在基板140的表面148上的部分係形成LGA引線，並且提供在DCALGA封裝170與例如是PCB的外部的裝置之間的互連。半導體晶粒104係在本實施例中被舉例使用，來自圖3的半導體晶粒130及/或來自圖4的半導體晶粒134亦可被用來形成DCALGA封裝170。
微柱122的導電柱118係被固定到半導體晶粒104的接觸墊112。微柱122的導電層120係被設置在導電柱118與在基板140的表面146上的導電層144的接觸墊之間。在被回焊時，導電層120係在導電柱118與導電層144的接觸墊之間形成電性及冶金連接。導電柱118在回焊期間並不會熔化或是變形。導電柱118係在半導體晶粒104與基板140的表面146之 間提供一固定的偏移。只回焊導電層120係容許微柱122的間距能夠被縮減。相對於熔化整個互連結構，亦即導電柱118以及導電層120，只熔化導電層120係減低在回焊期間的液態的材料的體積，並且避免在回焊期間被熔化的材料擴散在導電層144的相鄰的線路之間。只熔化導電層120係減低電性短路的發生，並且增加DCALGA封裝170的可靠度。微柱122的被縮減的間距亦容許較大數目的微柱122能夠被形成在半導體晶粒104之上。於是，具有增大的輸入/輸出密度需求的半導體晶粒及裝置可以被納入到DCALGA封裝170中。
基板140並不需要在導電層144以及基板140的表面146之上的一阻焊劑或是焊料遮罩，因為由微柱122所採用導電層120的小量的可熔材料並不會在回焊期間，冒著在導電層144的相鄰的線路之間擴散的風險，亦即導電層120的被熔化材料將不會在導電層144的相鄰的線路之間形成導電的橋或是短路。消除在基板140之上形成一焊料遮罩的需求係簡化用於基板140的製程。消除在基板140之上形成一焊料遮罩的需求係減小製造時間及成本，此係增加處理量。消除一焊料遮罩層亦降低基板140的厚度以及DCALGA封裝160的整體厚度。
將具有微柱122的半導體晶粒104直接安裝至基板140的導電層144係最小化互連的距離，此係增加封裝速度。電連接在基板140之上的多個半導體晶粒係增進DCALGA封裝170的功能及整體效能。將具有微柱122的半導體晶粒104直接安裝至導電層144係最小化封裝的寄生元件，例如是寄生的RLC。在一實施例中，微柱122的導電層120係由無鉛的材料所構成的，以提供一綠色的對環境友善的互連結構。再者，導電層120 的第一回焊係在半導體晶粒104被安裝至該基板140時加以執行。消除在該晶圓層級，亦即在單粒化半導體晶圓100之前的一回焊操作係降低製造時間並且增加裝置可靠度，因為減低在半導體晶粒104之上所執行的回焊操作的數目係最小化半導體晶粒104所遭受到的加熱週期的數目。最小化在半導體晶粒104之上所執行的加熱週期的數目係降低翹曲以及裝置失效的風險。被露出的散熱片162係耗散由半導體晶粒104所產生的熱，並且增進DCALGA封裝170的熱效能以及可靠度。因此，DCALGA封裝170係提供一較薄的封裝，其係具有增大的可靠度、較快的效能速度、以及一具有降低的成本之簡化的製程。
儘管本發明的一或多個實施例已經加以詳細地描述，但是本領域技術人員將會體認到對於那些實施例可以做成修改及調適，而不脫離如同在以下的申請專利範圍中所闡述的本發明的範疇。

Claims (15)

  1. 一種製造一半導體裝置之方法，其係包括：提供一基板；提供一第一半導體晶粒，其包含形成在該第一半導體晶粒上方的第一接觸墊；形成一絕緣層，其包含經形成穿過該絕緣層以曝露該第一接觸墊的第一開口，其中該第一開口的寬度是小於該第一接觸墊的寬度；在該第一半導體晶粒上方沉積遮罩層；在該第一接觸墊上方的該遮罩層中形成第二開口，其中該第二開口的寬度是大於該第一開口的寬度；直接在該第一接觸墊上的該第一開口和該第二開口之中沉積銅以形成銅柱，其中所述銅柱接觸該絕緣層的頂表面以及在該第一開口之中的該絕緣層的垂直表面；直接在該第二開口之中的該銅上沉積焊料層；從該第一半導體晶粒移除該遮罩層；將該第一半導體晶粒設置於該基板上方，而該焊料層接觸在該基板上的第二接觸墊；將第二半導體晶粒設置於該基板上方；回焊該焊料層至該第二接觸墊上；在該第一半導體晶粒以及該第二半導體晶粒的周圍沉積一密封劑，其中該密封劑接觸所述銅柱、焊料層和第二接觸墊；以及切割穿透該密封劑和基板以單粒化該第一半導體晶粒和第二半導體晶粒成為個別的半導體封裝。
  2. 如申請專利範圍第1項之方法，其中該基板係包含一引線架。
  3. 如申請專利範圍第1項之方法，其進一步包含在該第一半導體晶粒之上設置一散熱片。
  4. 如申請專利範圍第3項之方法，其進一步包含從該散熱片上方移除該密封劑的一部分。
  5. 如申請專利範圍第1項之方法，其進一步包含在形成所述銅柱和焊料層之後從一半導體晶圓單粒化該第一半導體晶粒。
  6. 如申請專利範圍第1項之方法，其進一步包括；在該第一半導體晶粒上方形成傳導層；以及形成該第一接觸墊作為該導電層的部分，其中該導電層從該第一接觸墊延伸朝向該第一半導體晶粒的中央。
  7. 一種製造一半導體裝置之方法，其係包括：提供一基板；提供一第一半導體晶粒，其包含經形成在該第一半導體晶粒上方的接觸墊；形成絕緣層於該第一半導體晶粒上方，其包含在該接觸墊上方的該絕緣層之中的開口；形成直接在接觸墊上並且物理性地接觸該絕緣層的銅柱；直接沉積焊料層於該銅柱上；回焊該焊料層至該基板上；沉積一密封劑於該基板和第一半導體晶粒上方，其中該密封劑接觸該銅柱和焊料層；以及切割穿透該密封劑和基板。
  8. 如申請專利範圍第7項之方法，其進一步包含在該第一半導體晶粒之上形成一屏蔽層。
  9. 如申請專利範圍第7項之方法，其進一步包含：設置第二半導體晶粒於該基板上方；以及切割穿透在該第一導半體晶粒和第二半導體晶粒之間的該密封劑和基板。
  10. 如申請專利範圍第7項之方法，其中該銅柱延伸進入該絕緣層的該開口以物理性地接觸該接觸墊。
  11. 如申請專利範圍第7項之方法，其進一步包含在該第一半導體晶粒之上設置一散熱片。
  12. 一種製造一半導體裝置之方法，其包括：提供一基板；提供一第一半導體晶粒，其包含形成在該第一半導體晶粒上方的接觸墊；形成一絕緣層於該第一半導體晶粒上方，其包含在該接觸墊上方的該絕緣層中的開口，其中該開口的寬度是小於該接觸墊的寬度；直接形成銅柱於該開口中的接觸墊上，其中在該開口之上的所述銅柱的寬度是大於在該開口之中的寬度；直接在該銅柱上形成焊料層；在該第一半導體晶粒以及該基板之間沉積一密封劑，而該密封劑延伸於該第一半導體晶粒相對於該基板的表面上方；以及切割穿透圍繞該第一半導體晶粒的該基板和密封劑。
  13. 如申請專利範圍第12項之方法，其進一步包含使用單一圖案化層來形成該銅柱和焊料層。
  14. 如申請專利範圍第12項之方法，其進一步包含設置屏蔽層於該第一半導體晶粒上方。
  15. 如申請專利範圍第12項之方法，其進一步包含：設置散熱片於該第一半導體晶粒上方；並且沉積該密封劑於該散熱片上方。
TW105129584A 2015-10-29 2016-09-12 使用具有微柱的半導體晶粒來形成直接晶片接合平面柵格陣列封裝之半導體裝置及方法 TWI656581B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/927,361 US9875988B2 (en) 2015-10-29 2015-10-29 Semiconductor device and method of forming DCALGA package using semiconductor die with micro pillars
US14/927,361 2015-10-29

Publications (2)

Publication Number Publication Date
TW201727772A TW201727772A (zh) 2017-08-01
TWI656581B true TWI656581B (zh) 2019-04-11

Family

ID=56939889

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105129584A TWI656581B (zh) 2015-10-29 2016-09-12 使用具有微柱的半導體晶粒來形成直接晶片接合平面柵格陣列封裝之半導體裝置及方法

Country Status (5)

Country Link
US (1) US9875988B2 (zh)
EP (1) EP3163613A1 (zh)
KR (1) KR101958521B1 (zh)
CN (2) CN113690179A (zh)
TW (1) TWI656581B (zh)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017112241A (ja) * 2015-12-17 2017-06-22 ルネサスエレクトロニクス株式会社 半導体装置
US10672731B2 (en) * 2015-12-23 2020-06-02 Intel IP Corporation Wafer level package structure with internal conductive layer
US10504827B2 (en) * 2016-06-03 2019-12-10 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US20180240738A1 (en) * 2017-02-22 2018-08-23 Cyntec Co., Ltd. Electronic package and fabrication method thereof
TWI652774B (zh) * 2017-03-03 2019-03-01 矽品精密工業股份有限公司 電子封裝件之製法
US10573579B2 (en) 2017-03-08 2020-02-25 Mediatek Inc. Semiconductor package with improved heat dissipation
US11302592B2 (en) 2017-03-08 2022-04-12 Mediatek Inc. Semiconductor package having a stiffener ring
US10580710B2 (en) 2017-08-31 2020-03-03 Micron Technology, Inc. Semiconductor device with a protection mechanism and associated systems, devices, and methods
EP3478033A1 (en) * 2017-10-25 2019-05-01 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Embedding component with pre-connected pillar in component carrier
US10446521B2 (en) * 2017-11-07 2019-10-15 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating an integrated fan-out package
US10381329B1 (en) 2018-01-24 2019-08-13 Micron Technology, Inc. Semiconductor device with a layered protection mechanism and associated systems, devices, and methods
US10475771B2 (en) 2018-01-24 2019-11-12 Micron Technology, Inc. Semiconductor device with an electrically-coupled protection mechanism and associated systems, devices, and methods
US10580715B2 (en) * 2018-06-14 2020-03-03 Texas Instruments Incorporated Stress buffer layer in embedded package
KR102477356B1 (ko) * 2018-09-11 2022-12-15 삼성전자주식회사 반도체 패키지
US10734304B2 (en) * 2018-11-16 2020-08-04 Texas Instruments Incorporated Plating for thermal management
US10985109B2 (en) * 2018-12-27 2021-04-20 STATS ChipPAC Pte. Ltd. Shielded semiconductor packages with open terminals and methods of making via two-step process
TWI736982B (zh) * 2019-09-17 2021-08-21 李蕙如 主動式rgb發光二極體像素元件
US10631405B1 (en) * 2019-09-20 2020-04-21 Raytheon Company Additive manufacturing technology (AMT) inverted pad interface
US20210217707A1 (en) * 2020-01-10 2021-07-15 Mediatek Inc. Semiconductor package having re-distribution layer structure on substrate component
EP3852132A1 (en) * 2020-01-20 2021-07-21 Infineon Technologies Austria AG Additive manufacturing of a frontside or backside interconnect of a semiconductor die
CN113725182B (zh) * 2020-03-27 2024-02-27 矽磐微电子(重庆)有限公司 芯片封装结构
US11769730B2 (en) * 2020-03-27 2023-09-26 STATS ChipPAC Pte. Ltd. Semiconductor device and method of providing high density component spacing
US11581281B2 (en) * 2020-06-26 2023-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Packaged semiconductor device and method of forming thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448114A (en) * 1992-07-15 1995-09-05 Kabushiki Kaisha Toshiba Semiconductor flipchip packaging having a perimeter wall
US5969426A (en) * 1994-12-14 1999-10-19 Mitsubishi Denki Kabushiki Kaisha Substrateless resin encapsulated semiconductor device
US6653730B2 (en) * 2000-12-14 2003-11-25 Intel Corporation Electronic assembly with high capacity thermal interface
US20050087852A1 (en) * 2003-04-22 2005-04-28 Kai-Chi Chen Chip package structure and process for fabricating the same
US20120273935A1 (en) * 2011-04-29 2012-11-01 Stefan Martens Semiconductor Device and Method of Making a Semiconductor Device

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5147084A (en) * 1990-07-18 1992-09-15 International Business Machines Corporation Interconnection structure and test method
US5261593A (en) * 1992-08-19 1993-11-16 Sheldahl, Inc. Direct application of unpackaged integrated circuit to flexible printed circuit
US6365500B1 (en) * 1994-05-06 2002-04-02 Industrial Technology Research Institute Composite bump bonding
US5729896A (en) 1996-10-31 1998-03-24 International Business Machines Corporation Method for attaching a flip chip on flexible circuit carrier using chip with metallic cap on solder
US6314639B1 (en) * 1998-02-23 2001-11-13 Micron Technology, Inc. Chip scale package with heat spreader and method of manufacture
US6050832A (en) * 1998-08-07 2000-04-18 Fujitsu Limited Chip and board stress relief interposer
US5977626A (en) 1998-08-12 1999-11-02 Industrial Technology Research Institute Thermally and electrically enhanced PBGA package
JP4239310B2 (ja) * 1998-09-01 2009-03-18 ソニー株式会社 半導体装置の製造方法
JP3577419B2 (ja) * 1998-12-17 2004-10-13 新光電気工業株式会社 半導体装置およびその製造方法
US6122171A (en) * 1999-07-30 2000-09-19 Micron Technology, Inc. Heat sink chip package and method of making
US6660560B2 (en) 2001-09-10 2003-12-09 Delphi Technologies, Inc. No-flow underfill material and underfill method for flip chip devices
JP3717899B2 (ja) * 2002-04-01 2005-11-16 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
US6811892B2 (en) 2002-08-22 2004-11-02 Delphi Technologies, Inc. Lead-based solder alloys containing copper
US6943058B2 (en) 2003-03-18 2005-09-13 Delphi Technologies, Inc. No-flow underfill process and material therefor
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
CN102306635B (zh) * 2004-11-16 2015-09-09 罗姆股份有限公司 半导体装置及半导体装置的制造方法
JP5215587B2 (ja) * 2007-04-27 2013-06-19 ラピスセミコンダクタ株式会社 半導体装置
EP2176883A2 (en) * 2007-08-08 2010-04-21 Casio Computer Co., Ltd. Semiconductor device and method for manufacturing the same
US7906857B1 (en) 2008-03-13 2011-03-15 Xilinx, Inc. Molded integrated circuit package and method of forming a molded integrated circuit package
CN102379037B (zh) * 2009-03-30 2015-08-19 高通股份有限公司 使用顶部后钝化技术和底部结构技术的集成电路芯片
US8198131B2 (en) * 2009-11-18 2012-06-12 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
KR101195271B1 (ko) * 2011-04-29 2012-11-14 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
US8552540B2 (en) 2011-05-10 2013-10-08 Conexant Systems, Inc. Wafer level package with thermal pad for higher power dissipation
CN103975427B (zh) 2011-10-07 2017-03-01 沃尔泰拉半导体公司 互连衬底的功率管理应用
KR20130140321A (ko) * 2012-06-14 2013-12-24 에스케이하이닉스 주식회사 임베디드 패키지 및 제조 방법
KR101970291B1 (ko) * 2012-08-03 2019-04-18 삼성전자주식회사 반도체 패키지의 제조 방법
KR101411813B1 (ko) 2012-11-09 2014-06-27 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448114A (en) * 1992-07-15 1995-09-05 Kabushiki Kaisha Toshiba Semiconductor flipchip packaging having a perimeter wall
US5969426A (en) * 1994-12-14 1999-10-19 Mitsubishi Denki Kabushiki Kaisha Substrateless resin encapsulated semiconductor device
US6653730B2 (en) * 2000-12-14 2003-11-25 Intel Corporation Electronic assembly with high capacity thermal interface
US20050087852A1 (en) * 2003-04-22 2005-04-28 Kai-Chi Chen Chip package structure and process for fabricating the same
US20120273935A1 (en) * 2011-04-29 2012-11-01 Stefan Martens Semiconductor Device and Method of Making a Semiconductor Device

Also Published As

Publication number Publication date
TW201727772A (zh) 2017-08-01
CN107039337A (zh) 2017-08-11
EP3163613A1 (en) 2017-05-03
US9875988B2 (en) 2018-01-23
CN113690179A (zh) 2021-11-23
KR20170051252A (ko) 2017-05-11
US20170125375A1 (en) 2017-05-04
KR101958521B1 (ko) 2019-03-14

Similar Documents

Publication Publication Date Title
TWI656581B (zh) 使用具有微柱的半導體晶粒來形成直接晶片接合平面柵格陣列封裝之半導體裝置及方法
TWI655692B (zh) 半導體裝置以及形成具有小ｚ方向尺寸的半導體封裝的方法
TWI614859B (zh) 半導體裝置和形成具有扇出互連結構以減少基板複雜性之擴大的半導體裝置之方法
US8409979B2 (en) Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties
KR102067840B1 (ko) 반도체 디바이스 및 그 제조 방법
KR101523383B1 (ko) 반도체 소자 및 그 제조 방법
TWI508226B (zh) 在基板的孔穴中鑲嵌具有直通矽晶穿孔的晶粒用以扇入封裝疊加的電互連之半導體裝置和方法
TWI581345B (zh) 半導體裝置以及形成引線上接合互連用於鑲嵌半導體晶粒在扇出晶圓級晶片規模封裝中之方法
KR102642327B1 (ko) 반도체 디바이스 및 그 제조 방법
US7880293B2 (en) Wafer integrated with permanent carrier and method therefor
TWI534974B (zh) 半導體裝置以及形成具有用於凸塊鎖定而被形成穿過抗蝕刻阻劑傳導層之凹處的基板之方法
EP3131117A1 (en) Semiconductor device and method of forming inverted pyramid cavity semiconductor package
TWI677034B (zh) 單次式封裝
US9252094B2 (en) Semiconductor device and method of forming an interconnect structure with conductive material recessed within conductive ring over surface of conductive pillar
US9230896B2 (en) Semiconductor device and method of reflow soldering for conductive column structure in flip chip package
KR102362426B1 (ko) 노출된 다이 후면을 갖는 플립 칩 패키지를 위한 emi 차폐