CN113690179A - 用有微柱的半导体管芯形成dcalga封装的方法和半导体器件 - Google Patents

用有微柱的半导体管芯形成dcalga封装的方法和半导体器件 Download PDF

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CN113690179A
CN113690179A CN202110994231.9A CN202110994231A CN113690179A CN 113690179 A CN113690179 A CN 113690179A CN 202110994231 A CN202110994231 A CN 202110994231A CN 113690179 A CN113690179 A CN 113690179A
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semiconductor die
substrate
semiconductor
layer
conductive
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S·金努萨米
W·H·谭
A·潘
K·K·侯
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Semtech Corp
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Semtech Corp
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Abstract

本发明涉及用有微柱的半导体管芯形成DCALGA封装的方法和半导体器件。半导体器件具有布置在衬底之上的第一半导体管芯。在半导体管芯之上形成多个复合互连结构。复合互连结构具有不可熔导电柱和在不可熔导电柱之上形成的可熔层。可熔层被回流以将第一半导体管芯连接到衬底的导电层。不可熔导电柱在回流期间不熔化，从而消除了在衬底之上形成阻焊剂的需要。将密封剂沉积在第一半导体管芯和复合互连结构周围。密封剂在第一半导体管芯的有源表面和衬底之间流动。第二半导体管芯相邻于第一半导体管芯布置在衬底之上。散热器布置在第一半导体管芯之上。密封剂的一部分被移除以暴露散热器。

Description

用有微柱的半导体管芯形成DCALGA封装的方法和半导体器件
技术领域
本发明大体上涉及半导体器件，且更具体地涉及用具有微柱的半导体管芯来形成芯片直接贴装焊盘网格阵列（DCALGA）封装的方法和半导体器件。
背景技术
半导体器件通常被发现在现代电子产品中。半导体器件在电气部件的数量和密度方面改变。分立半导体器件通常包含一种类型的电气部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器和功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件典型地包含数百到数百万个电气部件。集成半导体器件的示例包括微控制器、微处理器和各种信号处理电路。
半导体器件执行各种各样的功能，诸如信号处理、高速计算、传输和接收电磁信号、控制电子器件、将太阳光转换成电以及为电视显示器创建视觉图像。半导体器件被发现在娱乐、通信、功率转换、网络、计算机和消费产品的领域中。半导体器件还被发现在军事应用、航空、汽车、工业控制器和办公室设备中。
半导体器件采用半导体材料的电气性质。半导体材料的结构允许由电场或基极电流的施加或通过掺杂的工艺来操纵材料的导电性。掺杂将杂质引入到半导体材料中以操纵并控制半导体器件的导电性。
半导体器件包含有源和无源电气结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变电场或基极电流的施加和掺杂的水平，晶体管促进或限制电流的流动。包括电阻器、电容器和电感器的无源结构创建执行各种电气功能所需的电压和电流之间的关系。使无源和有源结构电连接以形成电路，其使半导体器件能够执行高速操作和其它有用的功能。
通常使用两种复杂的制造工艺（即，前端制造和后端制造）来制造半导体器件，每个制造潜在地涉及数百个步骤。前端制造涉及在半导体晶片的表面上的多个管芯的形成。每个半导体管芯典型地是相同的，并包含通过电连接有源和无源部件而形成的电路。后端制造涉及从完成的晶片单体化个体半导体管芯以及封装管芯以提供结构支持、电互连和环境隔离。如在本文中使用的术语“半导体管芯”指代词的单数和复数形式二者，并且相应地可以指代单个半导体器件和多个半导体器件二者。
半导体制造的一个目标是生产较小的半导体器件。较小的器件典型地消耗较少的功率，具有较高的性能，并可以被更有效地生产。此外，较小的半导体器件具有较小的覆盖区（footprint），这对于较小的最终产品是合乎需要的。减小的封装剖面对在智能电话中封装、可穿戴技术和物联网（IoT）工业特别重要。较小的半导体管芯尺寸可以由前端工艺中的改进实现，从而导致具有较小、较高密度的有源和无源部件的半导体管芯。后端工艺可以通过在电互连和封装材料中的改进来导致具有较小的覆盖区的半导体器件封装。
较小的半导体器件的制造依赖于实现对在半导体管芯和下层衬底之间以及在布置在单个衬底之上的多个半导体管芯之间的水平和垂直电互连的改进。通过在倒装芯片取向上将半导体管芯安装到衬底来形成倒装芯片封装。衬底提供在半导体管芯和外部器件之间的电互连。然而，对于当前倒装芯片封装的封装高度和完全生产时间（throughput time）的减小受衬底的厚度和在倒装芯片与衬底之间形成的互连的高度约束。
发明内容
存在减小封装尺寸和制造时间同时提高执行速度和可靠性的需要。相应地，在一个实施例中，本发明是制造半导体器件的方法，其包括下列步骤：提供衬底；布置包括复合互连结构的第一半导体管芯，复合互连结构包括在衬底之上的不可熔部分和可熔部分；使复合互连结构的可熔部分回流；以及将密封剂沉积在第一半导体管芯周围。
在另一实施例中，本发明是制造半导体器件的方法，其包括下列步骤：提供衬底；布置包括复合互连结构的第一半导体管芯，复合互连结构包括在衬底之上的不可熔部分和可熔部分；以及使复合互连结构的可熔部分回流。
在另一实施例中，本发明是包括衬底和第一半导体管芯的半导体器件，第一半导体管芯包括布置在衬底之上的复合互连结构。将密封剂沉积在第一半导体管芯周围。
在另一实施例中，本发明是包括衬底和第一半导体管芯的半导体器件，第一半导体管芯包括布置在衬底之上的复合互连结构。
附图说明
图1a-1f图示形成具有微柱的半导体管芯的方法；
图2图示具有微柱的半导体管芯；
图3图示具有在绝缘层之上形成的微柱的半导体管芯；
图4图示具有在RDL之上形成的微柱的半导体管芯；
图5a-5f 图示使用具有微柱的半导体管芯来形成DCALGA封装的方法；
图6a-6b图示包括具有微柱的半导体管芯的DCALGA封装；
图7图示包括散热器和具有微柱的多个半导体管芯的DCALGA封装；以及
图8图示包括暴露的散热器和具有微柱的多个半导体管芯的DCALGA封装。
具体实施方式
在下面的描述中参考附图在一个或多个实施例中描述了本发明，其中同样的数字表示相同或相似的元件。虽然在用于实现本发明的目的最佳模式方面描述了本发明，但是本领域技术人员将认识到，本公开意欲涵盖如可被包括在如由所附权利要求和权利要求等价物（如由下面的公开和附图支持的）限定的本发明的精神和范围内的替代方案、修改和等价物。
通常使用下述两种复杂的制造工艺来制造半导体器件：前端制造和后端制造。前端制造涉及在半导体晶片的表面上的多个管芯的形成。在晶片上的每个管芯包含有源和无源电气部件，其被电连接以形成功能电路。有源电气部件诸如晶体管和二极管具有控制电流的流动的能力。诸如电容器、电感器和电阻器的无源电气部件创建执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、蚀刻和平面化的一系列工艺步骤在半导体晶片的表面之上形成无源和有源部件。掺杂通过诸如离子注入或热扩散的技术将杂质引入到半导体材料中。掺杂工艺通过响应于电场或基极电流而动态地改变半导体材料导电性来修改在有源器件中的半导体材料的导电性。晶体管包含必要时被布置成当施加电场或基极电流时使晶体管能够促进或限制电流的流动的掺杂的变化的类型和程度的区。
通过具有不同的电气性质的材料层形成有源和无源部件。这些层可以通过部分地由被沉积的材料的类型确定的各种沉积技术来形成。例如，薄膜沉积可以涉及化学气相沉积（CVD）、物理气相沉积（PVD）、电解电镀和无电电镀工艺。每层通常被图案化以形成有源部件、无源部件或在这些部件之间的电连接的部分。
后端制造指代将完成的晶片切割或单体化成个体半导体管芯以及封装半导体管芯用于结构支持、电互连和环境隔离。为了单体化半导体管芯，沿着被称为锯切道（sawstreet）或划线的晶片的非功能区来切划并折断晶片。使用激光切割工具或锯条来单体化晶片。在单体化之后，将个体半导体管芯安装到包括用于与其它系统部件互连的管脚或接触焊盘的封装衬底。在半导体管芯之上形成的接触焊盘然后连接到在封装内的接触焊盘。可以用导电层、凸块、螺柱凸块、导电膏或丝焊做出电连接。密封剂或其它模制材料被沉积在封装之上以提供物理支持和电隔离。完成的封装然后插到电气系统中，并且使半导体器件的功能可用于其它系统部件。
图1a示出具有基本衬底材料102的半导体晶片100，基本衬底材料102诸如硅、锗、磷化铝、砷化铝、砷化镓、氮化镓、磷化铟、碳化硅或用于结构支持的其它块体半导体材料。在晶片100上形成多个半导体管芯或部件104。半导体管芯104通过如上所述的非有源、管芯间晶片区域或锯切道106分离。锯切道106提供切割区域以将半导体晶片100单体化成个体半导体管芯104。
图1b示出半导体晶片100的一部分的横截面视图。每个半导体管芯104具有背面或非有源表面108和有源表面110，有源表面110包含被实现为在管芯内形成并根据管芯的电气设计和功能而电互连的有源器件、无源器件、导电层和介质层的模拟或数字电路。例如，电路包括一个或多个晶体管、二极管和在有源表面110内形成的其它电路元件以实现模拟电路或数字电路，诸如数字信号处理器（DSP）、ASIC、MEMS、存储器或其它信号处理电路。半导体管芯104也可以包含用于射频（RF）信号处理的集成无源器件（IPD），诸如电感器、电容器和电阻器。
使用PVD、CVD、电解电镀、无电电镀工艺或其它适当的金属沉积工艺在有源表面110之上形成导电层112。导电层112包括以下各项中的一层或多层：铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、银（Ag）、钯（Pd）、SnAg、SnAgCu、CuNi、CuNiAu、CuNiPdAu或其它适当的导电材料或其组合。导电层112操作为被电连接到有源表面110上的电路的接触焊盘。接触焊盘112便于在半导体管芯104内的有源电路与外部器件例如印刷电路板（PCB）之间的电互连。
使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化在有源表面110和接触焊盘112之上形成绝缘或钝化层114。钝化层114包含以下各项中的一层或多层：二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、氧化铪（HfO2）、苯并环丁烯（BCB）、聚酰亚胺（PI）、聚苯并恶唑（PBO）、聚合物或具有类似的绝缘和结构性质的其它材料。钝化层114覆盖有源表面110并提供对有源表面110的保护。在接触焊盘112之上和周围形成钝化层114，用于电隔离。通过蚀刻、激光直接消融（LDA）或其它适当的工艺在接触焊盘112之上的钝化层114中形成多个开口。在钝化层114中的开口暴露接触焊盘112，用于随后的电互连。
在图1c中，使用印刷、旋涂、喷涂或其它适当的方法在钝化层114和接触焊盘112之上形成图案化或光刻胶层116。通过蚀刻、LDA或形成开口117的其它适当工艺来移除光刻胶层116的一部分。在钝化层114和接触焊盘112之上形成开口117。开口117暴露并延伸到接触焊盘112。在一个实施例中，图案化开口117具有圆形横截面区域，其配置成形成具有包括圆形横截面的圆柱形状的导电柱。在另一实施例中，图案化开口117具有矩形横截面区域，其配置成形成具有包括矩形横截面的立方体形状的导电柱。
在图1d中，使用蒸发、溅射、电解电镀、无电电镀、丝网印刷工艺在开口117内和在接触焊盘112之上沉积导电材料以形成导电柱或圆柱118。导电柱118包括以下各项中的一层或多层：Al、Cu、Sn、钛（Ti）、Ni、Au、Ag、钨（W）或其它适当的导电材料。在一个实施例中，通过在光刻胶层116的图案化开口117中镀Cu来形成导电柱118。导电柱118电连接到接触焊盘112。
使用蒸发、电解电镀、无电电镀、落球（ball drop）或丝网印刷工艺在导电柱118之上沉积导电层或凸块材料120。导电层120包括Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料或其组合。导电柱118和导电层120的组合构成具有不可熔部分（导电柱118）和可熔部分（导电层120）的复合互连结构或微柱122。在一个实施例中，不可熔部分118是Cu柱，并且可熔层120是SnAg。在另一实施例中，不可熔柱部分118是Cu，并且可熔层120包括Ni和SnAg。
在图1e中，通过蚀刻工艺来移除光刻胶层116以留下个体微柱122。微柱122可以有具有圆形或卵形横截面的圆柱形状，或微柱122可以有具有矩形横截面的立方体形状。微柱122具有50微米（µm）或更小的高度H1并具有50 µm或更小的直径。微柱122代表可以在半导体管芯104之上形成的一种类型的互连结构。互连结构还可以使用凸块、导电膏、螺柱凸块或其它电互连。
在图1f中，通过使用锯条或激光切割工具切穿锯切道106来将半导体晶片100单体化成个体半导体管芯104。图2示出在单体化之后的半导体管芯104。微柱122在接触焊盘112之上形成并电连接到接触焊盘112。
图3示出类似于图2中的半导体管芯104的半导体管芯130。半导体管芯130包括在钝化层114之上形成的绝缘或钝化层132。使用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化在钝化层114和接触焊盘112之上形成绝缘层132。绝缘层132包含以下各项中的一层或多层：PI、SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PBO、聚合物或具有类似的绝缘和结构性质的其它材料。绝缘层132的一部分被移除以形成暴露接触焊盘112的多个开口。在绝缘层132中的开口比在钝化层114中的开口更小，即更窄。绝缘层132的一部分布置在钝化层114中的开口中并与接触焊盘112的表面接触。
在绝缘层132和接触焊盘112的被暴露部分之上形成微柱122。微柱122的不可熔导电柱部分118电连接到接触焊盘112。在导电柱118之上形成可熔导电层120。在一个实施例中，在导电柱118和接触焊盘112之间形成具有粘附层、阻挡层和种子或润湿层的凸点下金属化（UBM）。绝缘层132向有源表面110之上的微柱122提供电绝缘和应力解除。
图4示出类似于图3中的半导体管芯130的半导体管芯134。半导体管芯134包括导电层136。使用诸如PVD、CVD、溅射、电解电镀和无电电镀的图案化和金属沉积工艺在绝缘层132和接触焊盘112之上形成导电层136。导电层136包括以下各项中的一层或多层：Al、Cu、Sn、Ni、Au、Ag、Ti、TiW、W或其它适当的导电材料或其组合。导电层136的一个部分电连接到半导体管芯134的接触焊盘112。导电层136的其它部分是电共有的或电隔离的，这取决于半导体管芯134的设计和功能。导电层136操作为再分布层（RDL）以横向地越过半导体管芯134再分布电连接，即导电层136再分布从接触焊盘112到半导体管芯134的有源表面110之上的其它区域的电连接。
使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在绝缘层132和导电层136之上形成绝缘或钝化层138。绝缘层138包含以下各项中的一层或多层：SiO2、Si3N4、SiON、Ta2O5、Al2O3、PI、BCB、PBO或具有类似的绝缘和结构性质的其它材料。通过蚀刻、LDA或其它适当的工艺移除绝缘层138的一部分以暴露导电层136的部分。
在绝缘层138和导电层136的被暴露部分之上形成微柱122。微柱122的不可熔导电柱部分118电连接到导电层136。在导电柱118之上形成可熔导电层120。在一个实施例中，在导电柱118和导电层136之间形成具有粘附层、阻挡层和种子或润湿层的UBM。导电层136跨半导体管芯134再分布信号并允许微柱122的位置和布局被选择为反映（mirror）在任何衬底或引线框上的接触焊盘的位置和布局。
图5a-5f图示使用具有微柱的半导体管芯形成DCALGA封装的方法。图5a示出包含绝缘材料142和导电层144的衬底或PCB 140的一部分的横截面视图。在一个实施例中，衬底140包含具有酚醛棉纸、环氧树脂、树脂、机织玻璃、磨砂玻璃（matte glass）、聚酯和其它加强纤维或织品的组合的预浸渍材料、FR-4、FR-1、CEM-1或CEM-3的一个或多个层压层。衬底140也可以是引线框、多层柔性层压品、铜箔或半导体晶片，其包括包含一个或多个晶体管、二极管或其它电路元件的有源表面以实现模拟电路或数字电路。
绝缘材料142包含以下各项中的一层或多层：SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PI、PBO、聚合物或具有类似的结构和绝缘性质的其它介质材料。导电层144包含Al、Cu、Sn、Ni、Au、Ag、Ti、W或使用诸如溅射、电解电镀和无电电镀的图案化和金属沉积工艺形成的其它适当的导电材料。导电层144包括提供横向地越过衬底140和垂直地在衬底140的相对的表面146和148之间的电互连的横向RDL和垂直导电通孔。根据半导体管芯和随后安装到衬底140的其它器件的设计和功能，导电层144的部分是电共有的或电隔离的。在表面146上的导电层144的部分为半导体管芯和安装在表面146之上的部件提供接触焊盘。在表面148上的导电层144的部分形成针对在衬底140和外部器件例如PCB之间的电互连的引线。
在图5b中，使用例如拾取和放置操作将来自图2的半导体管芯104布置在衬底140之上，其中有源表面110朝向衬底140的表面146。焊剂材料149布置在微柱122的可熔层120之上。通过在将半导体管芯104布置在衬底140之上之前将微柱122浸在焊剂床中来沉积焊剂149。在一个实施例中，在衬底140的导电层144之上形成焊剂材料151，如图5c所示。
图5d示出安装到衬底140的半导体管芯104。使可熔层120达到与接触焊盘144物理接触，用于回流。微柱122的可熔层120被回流以电气地和冶金地连接到衬底140的导电层144。可熔层120在用热或施加压力回流时形成与接触焊盘144的电气和冶金连接。不可熔柱118固定到半导体管芯104的接触焊盘112。不可熔柱118在回流期间不熔化或变形。在一个实施例中，用具有比可熔层120的材料高的熔化温度的材料形成不可熔柱118。不可熔柱118提供在半导体管芯104和衬底140之间的间隙。不可熔柱118的高度被选择为维持在半导体管芯104和衬底140的表面146之间的固定偏移或间隙距离。
在只有微柱122的可熔层120在回流期间熔化的情况下，在导电层144和衬底140的表面146之上不需要阻焊剂或焊接掩模。在只有可熔层120在回流期间熔化的情况下，在回流期间产生的液相材料的体积减小。由微柱122采用的少量的可熔材料120减小了熔化的材料在回流期间在导电层144的相邻部分之间扩散的风险，即熔化的可熔材料120的减小的体积防止在导电层144的相邻迹线之间的导电桥或短路的形成。消除在衬底140之上形成焊接掩模的需要简化了衬底140的制造工艺并减小了制造时间和成本。消除阻焊剂层也最小化衬底140的厚度，即最小化在衬底140的相对的表面146和148之间的距离。
在图5e中，使用真空模制、锡膏印刷、压缩模制、传递模制、液体密封剂模制、旋涂或其它适当的涂敷工艺在半导体管芯104和衬底140之上沉积密封剂或模制底部填充（MUF）材料150。MUF材料150是聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯或具有适当的填料的聚合物。MUF材料150是不导电的，并在环境上保护半导体管芯104免受外部元件和污染物的影响。
MUF材料150布置在半导体管芯104的背表面108之上并沿着半导体管芯104的四个侧表面。MUF材料150在微柱122周围流动并布置在半导体管芯104的有源表面110和衬底的表面146之间。MUF材料150的填料尺寸被选择为允许MUF材料150在半导体管芯104的有源表面110和衬底140的表面146之间流动。在一个实施例中，MUF材料150在随后的背面研磨步骤中被减薄以暴露背表面108或可替换地留下在背表面108之上的减小的厚度的MUF材料150。可替换地，通过控制MUF材料150的沉积来从MUF材料150暴露背表面108以防止MUF材料150在背表面108之上流动。
在图5f中，锯条或激光切割设备152切穿MUF材料150和衬底140以单体化个体DCALGA封装154。图6a示出在单体化之后的DCALGA封装154。半导体管芯104经由微柱122电连接到衬底140的导电层144。半导体管芯104作为示例被用在本实施例中，来自图3的半导体管芯130或来自图4的半导体管芯134可用于形成DCALGA封装154。导电层144根据半导体管芯104的设计和功能提供横向地越过和垂直地穿过衬底140的电互连。在衬底140的表面148上的导电层144的部分形成焊盘网格阵列（LGA）引线并提供在DCALGA封装154和外部器件例如PCB之间的互连。
图6b示出在半导体管芯104的微柱122和衬底140的导电层144之间的互连的细节。不可熔柱118固定到半导体管芯104的接触焊盘112。可熔层120布置在导电柱118和在衬底140的表面146上的接触焊盘144之间。回流的可熔层120形成在柱118和接触焊盘144之间的电气和冶金连接。在被选择为防止柱118在回流期间熔化或变形的温度和压力下执行可熔层120的回流。不可熔柱118提供在半导体管芯104和衬底140的表面146之间的固定偏移。
可以以比例如焊料凸块窄的间距形成微柱122，因为只有可熔层120在回流期间熔化。与整个互连结构（即，导电柱118和可熔层120）相反，仅熔化可熔层120减小在回流期间液相材料的体积并防止熔化的材料在导电层144的相邻迹线之间扩散。仅熔化可熔层120减少电短路的出现并提高DCALGA 154的可靠性。微柱122的减小的间距也允许更大数量的微柱122在半导体管芯104之上形成。相应地，具有增加的输入/输出密度要求的半导体管芯和器件可以合并到DCALGA 154中。
采用具有微柱122的半导体管芯104消除了在衬底140的表面146之上形成焊接掩模或阻焊剂层的需要。衬底140不需要焊接掩模，因为由微柱122采用的可熔材料，即可熔层120的减小的体积不冒在回流期间在导电层144的相邻迹线之间扩散的风险。消除在衬底140之上形成焊接掩模的需要简化了用于形成衬底140的制造工艺。消除焊接掩模形成步骤也减少衬底140的制造时间，这增加生产量并减小DCALGA 154的总成本。此外，从衬底140消除焊接掩模层减小衬底140的厚度和DCALGA 154的总厚度。
将具有微柱122的半导体管芯104直接安装到衬底140的导电层144最小化了互连距离。最小化互连距离提高了封装速度。将具有微柱122的半导体管芯104直接安装到衬底140的导电层144也最小化了封装寄生元件，例如寄生电阻、电容和电感（RLC）。在一个实施例中，可熔层120由无铅材料组成以提供绿色的、在环境上友好的互连结构。此外，在将半导体管芯104布置在衬底140之上之后执行可熔层120的第一回流。消除以晶片级的、即在单体化半导体晶片100之前的回流操作减小制造时间。消除以晶片级的回流操作也提高器件可靠性，因为减小在半导体管芯104之上执行的回流操作的数量最小化了半导体管芯104受到的加热循环的数量。最小化加热循环的数量减小翘曲和器件故障的风险。因此，DCALGA 154提供具有提高的可靠性的更薄的封装、更快的执行速度和简化的制造工艺与减小的成本。
图7图示包括散热器和具有微柱的多个半导体管芯的DCALGA封装160。使用例如拾取和放置操作将来自图2的半导体管芯104布置在衬底140之上，其中有源表面110朝向衬底140的表面146。在一个实施例中，衬底140是引线框。在安装半导体管芯104之前，将焊剂材料布置在微柱122之上或在衬底140的导电层144之上。半导体管芯104作为示例被用在本实施例中，来自图3的半导体管芯130和/或来自图4的半导体管芯134也可用于形成DCALGA封装160。
微柱120的可熔层120布置在衬底140的表面146上的导电层144的接触焊盘之上。不可熔柱118固定到半导体管芯104的接触焊盘112。可熔层120被回流并形成与在表面146上的接触焊盘144的电气和冶金连接。不可熔柱118在回流期间不熔化或变形。不可熔柱118提供在半导体管芯104和衬底140之间的固定偏移。不可熔柱118的高度被选择为维持在半导体管芯104与衬底140的表面146之间的偏移或间隙距离。半导体管芯104经由导电层144电连接到彼此。
在只有微柱122的可熔层120在回流期间熔化的情况下，在导电层144和衬底140的表面146之上不需要阻焊剂或焊接掩模。在微柱122的回流期间产生的液相材料的减小的体积不冒在回流期间在导电层144的相邻迹线之间扩散的风险，即熔化的可熔层120将不形成在导电层144的相邻迹线之间的导电桥或短路。消除在衬底140之上形成焊接掩模的需要简化了衬底140的制造工艺并减少了制造时间和成本。简化制造工艺并减少制造时间增加了DCALGA 160的生产量。从衬底140的表面146之上消除阻焊剂层也减小衬底140的厚度和DCALGA 160的总厚度。
在至少一个半导体管芯104之上形成导电层162。粘合材料、热界面材料（TIM）或绝缘层164布置在导电层162和半导体管芯104的背表面108之间。导电层162电连接到衬底140的导电层144。在一个实施例中，导电层162充当散热器以增强来自半导体管芯104的热耗散并改进DCALGA 160的热性能。导电层162是Cu、Al或具有高的热传导性的其它材料。在另一实施例中，导电层162连接到地并充当屏蔽层以阻挡或吸收EMI、RFI、谐波畸变和其它干扰。在半导体管芯104之上形成屏蔽层改进DCALGA 160的电性能。
使用真空模制、锡膏印刷、压缩模制、传递模制、液体密封剂模制、旋涂或其它适当的涂敷工艺在半导体管芯104、散热器162和衬底140之上沉积密封剂或MUF材料166。MUF材料166是聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯或具有适当的填料的聚合物。MUF材料166是不导电的，并在环境上保护半导体管芯和其它部件免受外部元件和污染物的影响。
MUF材料166布置在散热器162之上、在半导体管芯104的背表面108之上和在半导体管芯104的侧表面周围。MUF材料166在散热器162和微柱122周围流动。MUF材料166布置在半导体管芯104的有源表面110和衬底140的表面146之间。MUF材料166的填料尺寸被选择为允许MUF材料166在相邻半导体管芯104之间和在半导体管芯104和衬底140之间流动。
锯条或激光切割设备（类似于切割设备152）用于切穿MUF材料166和衬底140以单体化个体DCALGA封装160。图7示出在单体化之后的DCALGA封装160。半导体管芯104经由微柱122电连接到衬底140的导电层144。导电层144根据半导体管芯104的设计和功能提供横向地越过和垂直地穿过衬底140的电互连。在衬底140的表面148上的导电层144的部分形成LGA引线并提供在DCALGA封装160和外部器件例如PCB之间的互连。
微柱122的不可熔柱118固定到半导体管芯104的接触焊盘112。微柱122的可熔层120布置在导电柱118和在衬底140的表面146上的接触焊盘144之间。回流的可熔层120形成在导电柱118和接触焊盘144之间的电气和冶金连接。不可熔柱118在回流期间不熔化或变形。不可熔柱118提供在半导体管芯104和衬底140的表面146之间的固定偏移。微柱122的间距可以被减小，因为只有可熔层120在回流期间熔化。与整个互连结构（即，导电柱118和可熔层120）相反，仅熔化可熔层120减小在回流期间液相材料的体积并防止熔化的材料在导电层144的相邻迹线之间扩散。因此，仅熔化可熔层120减少电短路的出现并提高DCALGA160的可靠性。微柱122的减小的间距也允许更大数量的微柱122在半导体管芯104之上形成。相应地，具有增加的输入/输出密度要求的半导体管芯和器件可以合并到DCALGA 160中。
衬底140不需要在导电层144和衬底140的表面146之上的阻焊剂或焊接掩模，因为由微柱122采用的少量的可熔材料120不冒在回流期间在导电层144的相邻迹线之间扩散的风险，即熔化的材料可熔层120将不引起在导电层144的相邻迹线之间的导电桥或短路。消除在衬底140之上形成焊接掩模的需要简化了衬底140的制造工艺。消除在衬底140之上形成焊接掩模的需要减少了制造时间和成本，这增加生产量。消除焊接掩模层也减小衬底140的厚度和DCALGA 160的总厚度。
将具有微柱122的半导体管芯104直接安装到衬底140的导电层144最小化了互连距离，这提高了封装速度。电连接在衬底140之上的多个半导体管芯提高了DCALGA 160的性能和功能。将具有微柱122的半导体管芯104直接安装到衬底140的导电层144最小化了封装寄生元件，例如寄生RLC。在一个实施例中，微柱122的可熔层120由无铅材料组成以提供绿色的、在环境上友好的互连结构。此外，在将半导体管芯104布置在衬底140之上之后执行可熔部分120的第一回流。消除以晶片级的、即在单体化半导体晶片100之前的回流操作减小制造时间并提高器件可靠性，因为减小在半导体管芯104之上执行的回流操作的数量减小了半导体管芯104受到的加热循环的数量。最小化在半导体管芯104之上执行的加热循环的数量减小翘曲和器件故障的风险。散热器162进一步提高DCALGA 160的热性能和可靠性。DCALGA 160提供具有提高的可靠性的更薄的封装、更快的执行速度、简化的制造工艺和减小的成本。
图8图示具有带有微柱122的多个半导体管芯104和被暴露的散热器162的DCALGA封装170。在DCALGA封装170中，在背面研磨操作中移除MUF材料166的一部分。背面研磨操作减小在半导体管芯104的背表面108之上的MUF材料166的厚度并暴露散热器162。在背面研磨之后，MUF材料166的表面168与散热器162的表面共面。可替换地，MUF材料166的沉积被控制以防止MUF材料166在散热器162之上流动。被暴露的散热器162耗散由半导体管芯104生成的热。散热器162可以布置在DCALGA 170中的一个或所有半导体管芯104之上。被暴露的散热器162提高DCALGA 170的热性能和可靠性。在沉积MUF材料166之后，锯条或激光切割设备（类似于切割设备152）用于切穿MUF材料166和衬底140并单体化个体DCALGA封装170。
图8示出在单体化之后的DCALGA封装170。半导体管芯104通过导电层144被电连接。导电层144根据半导体管芯104的设计和功能提供横向地越过和垂直地穿过衬底140的电互连。在衬底140的表面148上的导电层144的部分形成LGA引线并提供在DCALGA封装170和外部器件例如PCB之间的互连。半导体管芯104作为示例被用在本实施例中，来自图3的半导体管芯130和/或来自图4的半导体管芯134也可用于形成DCALGA封装170。
微柱122的不可熔柱118固定到半导体管芯104的接触焊盘112。微柱122的可熔层120布置在导电柱118和在衬底140的表面146上的接触焊盘144之间。回流的可熔层120形成在导电柱118和接触焊盘144之间的电气和冶金连接。不可熔柱118在回流期间不熔化或变形。不可熔柱118提供在半导体管芯104和衬底140的表面146之间的固定偏移。仅使可熔层120回流允许微柱122的间距减小。与整个互连结构（即，导电柱118和可熔层120）相反，仅熔化可熔层120减小在回流期间液相材料的体积，并防止熔化的材料在回流期间在导电层144的相邻迹线之间扩散。仅熔化可熔层120减少电短路的出现并提高DCALGA 170的可靠性。微柱122的减小的间距也允许更大数量的微柱122在半导体管芯104之上形成。相应地，具有增加的输入/输出密度要求的半导体管芯和器件可以合并到DCALGA 170中。
衬底140不需要在导电层144和衬底140的表面146之上的阻焊剂或焊接掩模，因为由微柱122采用的少量的可熔材料120不冒在回流期间在导电层144的相邻迹线之间扩散的风险，即可熔层120的熔化的材料将不形成在导电层144的相邻迹线之间的导电桥或短路。消除在衬底140之上形成焊接掩模的需要简化了衬底140的制造工艺。消除在衬底140之上形成焊接掩模的需要减少了制造时间和成本，这增加生产量。消除焊接掩模层也减小衬底140的厚度和DCALGA 170的总厚度。
将具有微柱122的半导体管芯104直接安装到衬底140的导电层144最小化了互连距离，这提高了封装速度。电连接在衬底140之上的多个半导体管芯提高了DCALGA 170的功能和总性能。将具有微柱122的半导体管芯104直接安装到导电层144最小化了封装寄生元件，例如寄生RLC。在一个实施例中，微柱122的可熔层120由无铅材料组成并提供绿色的、在环境上友好的互连结构。此外，在将半导体管芯104安装到衬底140时执行可熔部分120的第一回流。消除以晶片级的、即在单体化半导体晶片100之前的回流操作减小制造时间并提高器件可靠性，因为减小在半导体管芯104之上执行的回流操作的数量最小化了半导体管芯104受到的加热循环的数量。最小化在半导体管芯104之上执行的加热循环的数量减小翘曲和器件故障的风险。被暴露的散热器162耗散由半导体管芯104生成的热并提高DCALGA 170的热性能和可靠性。因此，DCALGA 170提供具有提高的可靠性的更薄的封装、更快的执行速度和简化的制造工艺与减小的成本。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将认识到，可以在不偏离如在所附权利要求中阐述的本发明的范围的情况下做出对那些实施例的修改和修正。

Claims (15)

1.一种制造半导体器件的方法，包括：
提供半导体晶片；
在所述半导体晶片中形成多个半导体管芯，包括一个或多个晶体管、二极管和其他电路元件形成在所述半导体管芯的有源表面内；
在所述半导体管芯的有源表面上形成多个接触焊盘；
在所述半导体管芯的有源表面上形成钝化层；
在所述钝化层中形成多个第一开口，其中每个第一开口形成在接触焊盘之一上；
在所述钝化层上形成光刻胶层；
移除所述光刻胶层的部分以形成多个第二开口，其中每个第二开口暴露相应的接触焊盘并且延伸到所述相应的接触焊盘；
在所述接触焊盘上的所述第二开口内沉积导电材料以形成多个导电柱；
在所述导电柱上在所述第二开口中沉积凸块材料而不使所述凸块材料回流；
在沉积所述凸块材料后，去除所述光刻胶层；
在去除所述光刻胶层后，单体化所述半导体晶片以将所述多个半导体管芯彼此分离；
提供衬底，所述衬底包括，
由绝缘材料形成的芯，
在所述芯的第一表面上形成的第一导电层，
在所述芯的第二表面上形成的第二导电层，以及
导电通孔，耦合在所述第一导电层的第一接触焊盘和所述第二导电层的第二接触焊盘之间；
在所述凸块材料或所述第一导电层上设置焊剂材料；
通过使所述第一导电层和所述导电柱之间的凸块材料回流，将所述半导体管芯安装到所述衬底；
在所述多个半导体管芯的第一半导体管芯上设置散热器，其中所述散热器从所述第一半导体管芯的背表面上延伸至所述衬底的所述第一导电层；
在所述半导体管芯上以及在所述半导体管芯和衬底之间沉积模制底部填充材料，其中所述模制底部填充材料设置在每个半导体管芯的背表面上并且沿着每个半导体管芯的四个侧表面；
背面研磨所述模制底部填充材料以从所述模制底部填充材料暴露所述散热器，其中与所述第一半导体管芯相邻设置的第二半导体管芯的背表面保持被所述模制底部填充材料覆盖；以及
切穿所述模制底部填充材料和衬底以单体化包括所述第一半导体管芯和第二半导体管芯的个体半导体封装。
2.如权利要求1所述的方法，其中在将所述半导体管芯安装到所述衬底时使所述凸块材料回流是在制造工艺期间执行的所述凸块材料的第一次回流。
3.如权利要求1所述的方法，还包括在所述散热器和所述第一半导体管芯的背表面之间设置热界面材料。
4.一种制造半导体器件的方法，包括：
提供第一半导体管芯；
在所述第一半导体管芯的有源表面上形成多个接触焊盘；
在所述第一半导体管芯的有源表面上形成钝化层；
在所述钝化层中形成多个第一开口，其中每个第一开口形成在接触焊盘之一上；
在所述钝化层上形成光刻胶层；
移除所述光刻胶层的部分以形成多个第二开口，其中每个第二开口暴露相应的接触焊盘并且延伸到所述相应的接触焊盘；
在所述接触焊盘上的所述第二开口内沉积导电材料以形成多个导电柱；
在所述导电柱上在所述第二开口中沉积凸块材料而不使所述凸块材料回流；
在沉积所述凸块材料后，去除所述光刻胶层；
提供衬底，所述衬底包括，
由绝缘材料形成的芯，
在所述芯的第一表面上形成的第一导电层，
在所述芯的第二表面上形成的第二导电层，以及
导电通孔，耦合在所述第一导电层的第一接触焊盘和所述第二导电层的第二接触焊盘之间；
在所述凸块材料或所述第一导电层上设置焊剂材料；
通过使所述第一导电层和所述导电柱之间的凸块材料回流，将所述第一半导体管芯安装到所述衬底；
在所述第一半导体管芯上设置散热器，其中所述散热器从所述第一半导体管芯的背表面上延伸至所述衬底的所述第一导电层；
与所述第一半导体管芯相邻且在所述第一半导体管芯的覆盖区之外地将第二半导体管芯安装到所述衬底；
在所述第一半导体管芯和第二半导体管芯上以及在所述第一半导体管芯和衬底之间沉积模制底部填充材料，其中所述模制底部填充材料设置在所述第一半导体管芯的背表面上并且沿着所述第一半导体管芯的四个侧表面；
背面研磨所述模制底部填充材料以从所述模制底部填充材料暴露所述散热器，其中与所述第二半导体管芯的背表面保持被所述模制底部填充材料覆盖；以及
切穿所述模制底部填充材料和衬底以单体化包括所述第一半导体管芯和第二半导体管芯的个体半导体封装。
5.如权利要求4所述的方法，其中在将所述第一半导体管芯安装到所述衬底时使所述凸块材料回流是在制造工艺期间执行的所述凸块材料的第一次回流。
6.如权利要求4所述的方法，还包括在所述散热器和所述第一半导体管芯的背表面之间设置热界面材料。
7.如权利要求4所述的方法，还包括：
在所述第一半导体管芯的有源表面和所述接触焊盘上形成绝缘层；和
在所述绝缘层上形成所述钝化层。
8.如权利要求4所述的方法，还包括在所述半导体管芯上形成包括所述接触焊盘的再分布层。
9.一种制造半导体器件的方法，包括：
提供半导体管芯；
在所述半导体管芯的有源表面上形成多个接触焊盘；
在所述半导体管芯的有源表面上形成钝化层；
在所述钝化层中形成多个第一开口，其中每个第一开口形成在接触焊盘之一上；
在所述钝化层上形成光刻胶层；
移除所述光刻胶层的部分以形成多个第二开口，其中每个第二开口暴露相应的接触焊盘并且延伸到所述相应的接触焊盘；
在所述接触焊盘上的所述第二开口内沉积导电材料以形成多个导电柱；
在所述导电柱上在所述第二开口中沉积凸块材料而不使所述凸块材料回流；
在沉积所述凸块材料后，去除所述光刻胶层；
提供衬底，所述衬底包括，
由绝缘材料形成的芯，
在所述芯的第一表面上形成的第一导电层，
在所述芯的第二表面上形成的第二导电层，以及
导电通孔，耦合在所述第一导电层的第一接触焊盘和所述第二导电层的第二接触焊盘之间；
通过使所述第一导电层和所述导电柱之间的凸块材料回流，将所述半导体管芯安装到所述衬底；
在所述半导体管芯上以及在所述半导体管芯和衬底之间沉积模制底部填充材料，其中所述模制底部填充材料设置在所述半导体管芯的背表面上并且沿着所述半导体管芯的四个侧表面；
以及
切穿所述模制底部填充材料和衬底以单体化包括所述半导体管芯的个体半导体封装。
10.根据权利要求9所述的方法，其中在将所述第一半导体管芯安装到所述衬底时使所述凸块材料回流是在制造工艺期间执行的所述凸块材料的第一次回流。
11.如权利要求9所述的方法，还包括在所述散热器和所述第一半导体管芯的背表面之间设置热界面材料。
12.如权利要求9所述的方法，还包括：
在所述第一半导体管芯的有源表面和所述接触焊盘上形成绝缘层；和
在所述绝缘层上形成所述钝化层。
13.如权利要求9所述的方法，还包括在所述半导体管芯上形成包括所述接触焊盘的再分布层。
14.如权利要求9所述的方法，还包括在所述半导体管芯的背表面上设置散热器。
15.如权利要求14所述的方法，还包括背面研磨所述模制底部填充材料以暴露所述散热器。
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CN107039337A (zh) 2017-08-11
US9875988B2 (en) 2018-01-23
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