TWI655692B - 半導體裝置以及形成具有小ｚ方向尺寸的半導體封裝的方法 - Google Patents

半導體裝置以及形成具有小ｚ方向尺寸的半導體封裝的方法 Download PDF

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TWI655692B
TWI655692B TW105122194A TW105122194A TWI655692B TW I655692 B TWI655692 B TW I655692B TW 105122194 A TW105122194 A TW 105122194A TW 105122194 A TW105122194 A TW 105122194A TW I655692 B TWI655692 B TW I655692B
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semiconductor die
semiconductor
encapsulant
bump
protective layer
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TW105122194A
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TW201705315A (zh
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客坤 侯
沙亞莫希 奇努薩米
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美商先科公司
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Abstract

半導體裝置具有多個第一半導體晶粒。多個第一凸塊被形成在第一半導體晶粒上方。第一保護層被形成在第一凸塊上方。第一半導體晶粒的一部分在背部研磨操作中被移除。背側保護層被形成在第一半導體晶粒上方。囊封物被沉積在第一半導體晶粒和第一凸塊上方。囊封物的一部分被移除以曝露第一凸塊。傳導層被形成在第一凸塊和囊封物上方。絕緣層和多個第二凸塊被形成在傳導層上方。多個導電通孔被形成以穿過囊封物。多個半導體裝置被堆疊，而導電通孔電性連接經堆疊的半導體裝置。具有直通矽晶穿孔的第二半導體晶粒被設置在第一半導體晶粒上方。

Description

半導體裝置以及形成具有小Z方向尺寸的半導體封裝的方法
本發明一般而言有關於半導體裝置，更具體地是有關於半導體裝置和形成具有縮小Z方向尺寸的半導體封裝的方法。
半導體裝置在現代電子產品中是常見的。半導體裝置在電性構件的數量和密度方面有所變化。離散式半導體裝置大致上含有一種類型的電性構件，例如，發光二極體(LED)、小型訊號電晶體、電阻器、電容器、電感器以及功率金屬氧化物半導體場效電晶體(MOSFET)。整合式半導體裝置通常含有數百到數百萬個電性構件。整合式半導體裝置的範例包括微控製器、微處理器和各種訊號處理電路。
半導體裝置執行廣泛的功能，諸如訊號處理、高速計算、傳送和接收電磁訊號、控制電子裝置、將太陽光轉換為電能以及產生用於電視顯示的視覺影像。半導體裝置在娛樂、通信、電力轉換、網路、電腦以及消費性產品的領域中被發現。半導體裝置在軍事應用、航空、汽車、工業控制器以及辦公設備中亦被發現。
半導體裝置利用半導體材料的電性特性。半導體材料的結構允許材料的導電性藉由電場或基極電流的施加或經由摻雜的製程所操縱。 摻雜引入雜質進入半導體材料，以操縱和控制的半導體裝置的傳導性。
半導體裝置含有主動和被動電性結構。主動結構(包括雙極性和場效電晶體)控制電流的流動。藉由改變摻雜的位準和電場或基極電流的施加，電晶體會促進或限制電流的流動。被動結構(包括電阻器、電容器和電感器)在電壓和電流之間產生執行各種電性功能所需的關係。被動和主動結構被電性連接以形成電路，而使半導體裝置能夠執行高速的操作和其他有用的功能。
半導體裝置大致上使用兩種複雜的製程來製造(亦即，前端製造以及後端製造)，其每一者皆可能涉及數百個步驟。前端製造涉及在半導體晶圓的表面上形成複數個晶粒。每一個半導體晶粒通常是相同的並且含有藉由電性連接主動和被動構件所形成的電路。後端製造涉及從完成的晶圓單粒化出個別的半導體晶粒並且將晶粒封裝以提供結構支撐、電性互連以及環境隔離。本文中所使用的「半導體晶粒(semiconductor die)」一詞兼具單數與複數兩種形式，據此，其可能係表示單一半導體裝置與多個半導體裝置。
半導體製造的一個目標是生產較小的半導體裝置。較小的裝置通常消耗較少的功率、具有較高的效能以及會被更有效率地生產。此外，較小的半導體裝置具有較小的覆蓋區，這對於較小的最終產品是理想的。較小的半導體晶粒大小是藉由改善前端製程而導致具有較小、較高密度的主動和被動構件的半導體晶粒來達成。後端製程的強化亦導致具有較小覆蓋區的半導體裝置並且是藉由改善電性互連和封裝材料來達成。縮小的封裝輪廓(package profile)對於行動電話或智慧型手機工業的封裝而言是特別 重要的。
封裝大小的減少是藉由減少封裝覆蓋區(亦即，藉由減少封裝的x和y方向尺寸)來達成。封裝大小的減少亦是藉由減少封裝高度或厚度(亦即，藉由減少封裝的z方向尺寸)來達成。z方向尺寸的減少是藉由減少在封裝內的半導體晶粒的厚度來達成。然而，減少半導體晶粒的厚度會增加半導體晶粒的脆弱度，而使得半導體晶粒或整個封裝更容易受到損壞。再者，形成具有減少的厚度的封裝常涉及到費時的製造製程，其會增加整體的成本並且減少生產量。
一種需要存在以形成具有減少的厚度的堅固的半導體裝置同時降低製造時間和成本。因此，在一實施例中，本發明揭示一種製造半導體裝置的方法，其包括以下步驟：提供多個第一半導體晶粒，其包括形成在所述第一半導體晶粒上方的多個凸塊；形成保護層於與所述凸塊相對的所述第一半導體晶粒上方；沉積囊封物於所述第一半導體晶粒上方；從所述凸塊上方移除所述囊封物的一部分；以及形成傳導層於所述凸塊和所述囊封物上方。
在另一實施例中，本發明揭示一種製造半導體裝置的方法，其包括以下步驟：提供第一半導體晶粒；形成第一保護層於所述第一半導體晶粒上方；沉積囊封物於所述第一半導體晶粒上方；從所述第一半導體晶粒上方移除所述囊封物的一部分；以及形成第一傳導層於所述囊封物的第一表面上方。
在另一實施例中，本發明揭示一種製造半導體裝置的方法， 其包括以下步驟：提供第一半導體晶粒；沉積囊封物於所述第一半導體晶粒上方；從所述第一半導體晶粒上方移除所述囊封物的一部分；以及形成傳導層於所述囊封物上方。
在另一實施例中，本發明揭示一種半導體裝置，其包括：第一半導體晶粒；以及保護層，其形成在所述第一半導體晶粒上方。囊封物，其沉積在所述第一半導體晶粒周圍。傳導層，其形成在與所述保護層相對的所述第一半導體晶粒上方。
100‧‧‧晶圓
102‧‧‧基底基板材料
104‧‧‧半導體晶粒
106‧‧‧切割道
108‧‧‧表面
110‧‧‧表面
112‧‧‧接觸墊
114‧‧‧凸塊
116‧‧‧保護層
118‧‧‧研磨器
120‧‧‧表面
122‧‧‧保護層
124‧‧‧薄膜框架/暫時性載體
126‧‧‧介面層
128‧‧‧鋸片/雷射切割工具
130‧‧‧載體
132‧‧‧介面層
134‧‧‧晶圓
136‧‧‧保護環
138‧‧‧囊封物
140‧‧‧表面
142‧‧‧研磨器
144‧‧‧表面
146‧‧‧傳導層
148‧‧‧絕緣層
150‧‧‧開口
152‧‧‧凸塊
154‧‧‧鋸片/雷射切割工具
156‧‧‧表面
160‧‧‧半導體裝置
170‧‧‧半導體裝置
180‧‧‧半導體裝置
182‧‧‧散熱器
190‧‧‧半導體裝置
192‧‧‧半導體晶粒
193‧‧‧表面
194‧‧‧表面
196‧‧‧傳導層
198‧‧‧TSV
199‧‧‧凸塊
200‧‧‧載體
202‧‧‧介面層
204‧‧‧晶圓
206‧‧‧保護環
208‧‧‧囊封物
210‧‧‧表面
212‧‧‧研磨器
214‧‧‧表面
216‧‧‧傳導層
218‧‧‧絕緣層
220‧‧‧凸塊
221‧‧‧表面
222‧‧‧保護層
224‧‧‧載體
228‧‧‧鋸片/雷射切割工具
230‧‧‧半導體裝置
236‧‧‧半導體裝置
238‧‧‧底部填充
240‧‧‧載體
242‧‧‧介面層
244‧‧‧通孔
246‧‧‧電射
248‧‧‧導電通孔
250‧‧‧傳導層
252‧‧‧鋸片/雷射切割工具
260‧‧‧半導體裝置
262‧‧‧半導體封裝
264‧‧‧半導體封裝
圖1a至圖1h說明形成保護層於半導體晶粒上方的方法；圖2a至圖2c說明形成具有經暴露的背表面的半導體晶粒的方法；圖3a至圖3g說明形成具有被形成於半導體晶粒上方的背側保護層的半導體裝置的方法；圖4說明具有被形成於半導體晶粒上方的背側保護層的半導體裝置；圖5說明具有含有經暴露的背表面的半導體晶粒的半導體裝置；圖6說明具有被設置於半導體晶粒上方的散熱器的半導體裝置；圖7說明具有經堆疊的半導體晶粒的半導體裝置；圖8a至圖8h說明製造具有被設置以橫跨半導體裝置的表面的保護層的半導體裝置的方法；圖9說明具有被設置以橫跨半導體裝置的表面的保護層的半導體裝置；圖10說明具有含有被形成以橫跨半導體裝置的表面的保護層的經堆疊的半導體晶粒的半導體裝置； 圖11a至圖11c說明形成具有用於電性連接經堆疊的裝置的導電通孔的方法；圖12說明在開放的半導體裝置堆疊中具有多個半導體裝置的半導體封裝；以及圖13說明在封閉的半導體裝置堆疊中具有多個半導體裝置的半導體封裝。
本發明在以下參照圖示的說明中以一或多個實施例來說明，其中相似的數字代表相同或相似的元件。儘管以實現本發明目的之最佳模式來說明本發明，然該領域中習知此技術者將瞭解的是，本揭示意圖涵蓋替代物、修改以及等效物，如同包含於藉以下的揭露事項與附圖所支撐的所附申請專利範圍及其等效物所定義的本發明精神與範疇之內。
半導體裝置大致上使用兩種複雜的製程來製造：前端製造以及後端製造。前端製造涉及在半導體晶圓的表面上形成複數個晶粒。在晶圓上的每一個晶粒皆包括主動與被動電性構件，其等被電性連接以形成功能性電路。主動電性構件(諸如，電晶體和二極體)具有控制電流流動之能力。被動電性構件(諸如，電容器、電感器以及電阻器)在電壓和電流之間建立執行電路功能所需的關係。
被動和主動構件係藉由一連串包含摻雜、沉積、光微影、蝕刻及平坦化之製程步驟而形成於半導體晶圓之表面上方。摻雜步驟藉由諸如離子植入或熱擴散的技術將雜質摻入半導體材料之中。摻雜製程藉由動態地改變半導體材料的傳導性修改在主動裝置中的半導體材料之導電性， 以回應電場或基極電流(base current)。電晶體包含具有不同類型及程度的摻雜的區域，該些區域係以使得電晶體在電場或基極電流的施加時提升或限制電流的流動所必要的來加以配置。
主動及被動構件係藉由具有不同電性特性的多個材料層來加以形成。該些層可藉由多種沉積技術來形成，該技術部分地是由被沉積的材料類型來決定的。舉例而言，薄膜沉積可涉及到化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解電鍍以及無電電鍍製程。每一個層大致上是被圖案化，以形成由主動構件、被動構件或構件之間的電性連接所組成的部件。
後端製造係指切割或單粒化完成的晶圓為個別的半導體晶粒並且封裝半導體晶粒以提供結構支撐、電性互連以及環境隔離。為了單粒化出半導體晶粒，晶圓沿著該晶圓的非功能性區域(稱為切割道或劃線)被劃線且截斷。晶圓利用雷射切割工具或鋸片被單粒化。在單粒化之後，個別的半導體晶粒被安裝到封裝基板，封裝基板包括用於和其它系統構件互連的接腳或接觸墊。形成在半導體晶粒上方的接觸墊接著被連接至封裝內的接觸墊。電性連接是利用傳導層、凸塊、柱形凸塊(stud bump)、導電膏或是引線接合所製成。囊封物或是其它模製材料沉積在封裝上方，以提供實體支撐以及電性隔離。該完成的封裝接著被插入電性系統中，並且使得該半導體裝置的功能是可供其它系統構件利用的。
圖1a例示半導體晶圓100，其具有用於結構支撐的基底基板材料102(諸如，矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、碳化矽或其它的塊體半導體材料)。多個半導體晶粒或構件104形成在晶圓 100上而由如上所述的非主動、晶粒間的晶圓區域或切割道106所隔開。切割道106提供切割區域，以將半導體晶圓100單粒化成個別的半導體晶粒104。
圖1b例示半導體晶圓100的一部分的截面圖。每一個半導體晶粒104皆具有背部或非主動表面108以及含有類比或數位電路的主動表面110，類比或數位電路根據電性設計以及晶粒的功能被實作為形成在晶粒內並且電性互連的主動裝置、被動裝置、傳導層以及介電層。舉例而言，電路包括形成在主動表面110內的一或多個電晶體、二極體以及其他電路元件，以實施類比電路或數位電路(諸如，數位訊號處理器(DSP)、ASIC、MEMS、記憶體或其他訊號處理電路)。半導體晶粒104亦含有整合式被動裝置(IPD)(諸如，電感器、電容器以及電阻器)，以用於RF訊號處理。
電性傳導層112利用PVD、CVD、電解電鍍、無電電鍍製程或其他合適的金屬沉積製程而形成在主動表面110上方。傳導層112包括以下所組成的一或多個層：鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鈀(Pd)、SnAg、SnAgCu、CuNi、CuNiAu、CuNiPdAu或其他合適的電性傳導材料或它們的組合。傳導層112作用為電性連接至主動表面110上的電路的接觸墊。接觸墊112有助於半導體晶粒104內的主動電路與外部裝置(舉例而言，印刷電路板(PCB))之間的後續電性互連。
電性傳導凸塊材料利用蒸鍍、電解電鍍、無電解電鍍、球式滴落(ball drop)或網版印刷製程被沉積在接觸墊112上方。凸塊材料可以是Al、Sn、Ni、Au、Ag、鉛(Pb)、鉍(Bi)、Cu、焊料以及上述組合，其具有選擇性的助焊溶液(flux solution)。舉例而言，凸塊材料是共晶的Sn/Pb、 高鉛焊料或無鉛焊料。凸塊材料利用合適的附接或接合製程被接合至接觸墊112。凸塊材料藉由加熱該材料到該材料的熔點之上被回焊，以形成球或凸塊114。在一些應用中，凸塊114被回焊第二次以改善與接觸墊112的電性連接。凸塊114亦可被壓縮接合或熱壓縮接合至接觸墊112。凸塊114代表被形成在接觸墊112上方的一種類型的互連結構。互連結構亦可使用柱形凸塊、微凸塊(micro bump)或其他電性互連件。
在圖1c中，暫時性保護層116是利用層壓、網版印刷、旋轉塗覆、噴霧塗覆或其他合適的方法被形成在凸塊114和晶圓110上方。暫時性保護層116含有以下的一或多個層：光阻、液體塗覆材料、乾膜(dry film)、聚合物膜、聚合物複合物或是其他具有順應性(compliance)、結構性支構、熱穩定性和容易剝離的性質的材料。保護層116覆蓋凸塊114和主動表面110。在一實施例中，保護層116是背研磨膠帶(backgrinding tape)。保護層116是被使用以在後續製造製程期間(舉例而言，在晶圓100的背部研磨期間)提供結構性支撐以及保護主動表面110的犧牲層。在沉積保護層116之後，可施加額外的處理(諸如，UV曝光和熱處理)以提供必要的黏合性和機械性質。
在圖1d中，晶圓100的背側表面108利用研磨器118進行背部研磨操作，以減少半導體晶粒104的厚度。背部研磨操作從表面108移除基底基板材料102的部分且使得半導體晶粒104有新的背側表面120。可使用化學蝕刻、電漿蝕刻、化學機械研磨(CMP)或雷射直接燒蝕(LDA)以移除基底基板材料102的部分。在一實施例中，背部研磨操作減少半導體晶粒104的厚度至25至300微米(μm)，亦即，在背部研磨之後半導體 晶粒104具有在25至300μm之間的z方向尺寸。保護層116在背部研磨操作期間保護主動表面110並且防止研磨碎屑污染接觸墊112和主動表面110內的裝置。保護層116亦在背部研磨操作期間以及背部研磨操作之後結構性地支撐半導體晶粒104。由保護層116所提供的結構性支撐允許一較大部分的基底基板材料102從表面108被移除。
在圖1e中，背側保護層122被形成在半導體晶粒104的表面120上。背側保護層122是藉由層壓、網版印刷、旋轉塗覆、噴霧塗覆或其他合適的方法所形成。背側保護層122是以下的一或多個層：光敏感聚合物介電膜，其可具有或不具有填充物；非光敏感聚合物介電膜；環氧化合物(epoxy)；環氧樹脂(epoxy resin)；聚合性材料；聚合物複合材料(諸如，具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯或具有合適填充物的聚合物)；墊固性塑膠層壓板；或具有類似絕緣或結構性質的其他材料。背側保護層122是非傳導的並且在環境上保護半導體晶粒104的背側表面120。背側保護層亦提供結構性支撐，以增加堅硬性並減少半導體晶粒104的脆弱度。背側保護層122亦可提供散熱性，以改善半導體裝置的熱效能。背側保護層122亦可提供翹曲調控能力，以控制整體的封裝翹曲度。
在圖1f中，半導體晶圓100被設置在介面層或雙面膠帶126上方。介面層126藉由薄膜框架(film frame)或暫時性載體124被保持在原處。介面層126被形成在薄膜框架124上方以作為暫時性黏合接合膜、蝕刻停止層或脫膜層。晶圓100被安裝至介面層126，而背側保護層122朝向並且接觸介面層126。
薄膜框架126、介面層126和晶圓100以適當溫度(temperate) 在烘箱中或者以加熱板加熱，並且持續一段足夠的時間以使保護層116脫膜並且暴露凸塊114和主動表面110。假如在使保護層116脫膜時背側保護層122未完全固化，則晶圓100、薄膜框架124和介面層126被允許在適當溫度下繼續烘烤並且持續一段足夠的時間以允許背側保護層122完全固化。
圖1g例示去除保護層116之後的半導體晶圓100。半導體晶圓100利用鋸片或雷射切割工具128經由切割道106被單粒化為個別的半導體晶粒104。替代而言，半導體晶粒104利用化學或電漿蝕刻製程被單粒化出來。
圖1h例示單粒化之後的半導體晶粒104。背側保護層122被形成在半導體晶粒104的背表面120上。背側保護層122保護背表面120免於污染並且實體性地強化半導體晶粒104。半導體晶粒104接著被清洗、乾燥和照射。清洗製程包括旋轉清洗乾燥(spin rinse drying，SRD)製程、電漿清洗製程、乾式清洗製程、濕式清洗製程或它們的組合。在單粒化之前或單粒化之後，半導體晶粒104被檢驗並且電性測試，以識別已知的良好晶粒(known good die，KGD)。經清洗和檢驗的半導體晶粒104接著被裝載至拾放設備中，用以進一步處理。
圖2a至圖2c例示形成具有經暴露的背側表面120的半導體晶粒104的方法。從圖1d繼續，半導體晶圓100被設置在介面層126或薄膜框架124上方。圖2a例示被安裝在薄膜框架124上方並且背表面120朝向並且接觸介面層126的半導體晶圓100。
薄膜框架126、介面層126和晶圓100以適當溫度在烘箱中或者以加熱板加熱，並且持續一段足夠的時間以使保護層116脫膜並且暴 露凸塊114和主動表面110。圖2b例示去除保護層116之後的半導體晶圓100。半導體晶圓100利用鋸片或雷射切割工具128經由切割道106被單粒化為個別的半導體晶粒104。替代而言，半導體晶粒104利用化學或電漿蝕刻製程被單粒化出來。
圖2c例示單粒化之後的半導體晶粒104。半導體晶粒104具有經暴露的背側表面120。個別半導體晶粒104接著被清洗、乾燥和照射。清洗製程包括SRD製程、電漿清洗製程、乾式清洗製程、濕式清洗製程或它們的組合。在單粒化之後，半導體晶粒104被檢驗並且電性測試，以識別KGD。經清洗和檢驗的半導體晶粒104接著被裝載至拾放設備中，用以進一步處理。
圖3a至圖3g例示形成具有被形成於半導體晶粒上方的背側保護層的半導體裝置的方法。圖3a例示含有用於結構支撐的犧牲基底材料(諸如，矽、聚合物、氧化鈹、玻璃、或其他合適的低成本、剛性材料)的載體或暫時性基板130的部分的截面圖。介面層或雙面膠帶132被形成在載體130上方以作為暫時性黏合接合膜、蝕刻停止層或熱脫膜層。來自圖1h的半導體晶粒104利用(舉例而言)拾放操作被設置在載體130和介面層132上方，而背側保護層122朝向載體。
圖3b例示被安裝至介面層132和載體130以作為重組或重新配置的晶圓134的半導體晶粒104。凸塊114被定向以遠離載體130。半導體晶粒104藉由介面層132在原位被保持在載體130上方。可重複使用的保護環136被設置在半導體晶粒104周圍。
在圖3c中，囊封物或模製化合物138利用網版印刷、噴霧 塗覆、焊膏印刷(paste printing)、壓縮模製、轉移模製、液態囊封模製、真空層壓、旋轉塗覆或其他合適的塗覆方法被沉積在半導體晶粒104和載體130上方。囊封物138被沉積在半導體晶粒104周圍並且覆蓋凸塊114、主動表面110和半導體晶粒104的四個側表面。囊封物138包括聚合物複合材料(諸如，具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯或具有合適填充物的聚合物)。囊封物138是非傳導的並且在環境上保護半導體晶粒104免受外部元件和污染物影響。
在圖3d中，保護環136被移除，並且囊封物138的表面140接受研磨操作以平坦化囊封物138且暴露凸塊114。研磨器142從表面140移除囊封物138的一部分。研磨操作露出凸塊114的一部分並且使囊封物具有平坦化的表面144。在研磨之後，表面144與凸塊114共面。
在圖3e中，電性傳導層146利用圖案化和金屬沉積製程(諸如，印刷、PVD、CVD、濺鍍、電解電鍍和無電解電鍍)被形成在凸塊114和囊封物138的表面144上方。傳導層146是以下所組成的一或多個層：Al、Cu、Sn、Ni、Au、Ag或其他合適的電性傳導材料。傳導層146操作為被形成在半導體晶粒104上方的重新分佈層(RDL)。傳導層146提供從凸塊114延伸至半導體晶粒104和囊封物138上方的其他區域的傳導路徑。傳導層146的一部分被電性連接至凸塊114。傳導層146的其他部分是共電的(electrically common)或是被電性隔離，其取決於半導體晶粒104的設計和功能。
在一實施例中，在暴露凸塊114之後，傳導層146藉由將經重組的晶圓134放置於高速奈米粒子噴射或雷射印刷機中而形成。傳導層 146的跡線接著以想要的圖案被直接印刷在凸塊114和囊封物138上方。奈米的Cu或Ag跡線被使用以形成傳導層146。在完成印刷之後，跡線被固化或燒結。替代而言，跡線在印刷時就被即時地同時燒結。
在另一實施例中，在暴露凸塊114之後，除膠渣操作(desmearing operation)在凸塊114和囊封物138的表面144上被執行。在除膠渣之後，經囊封的半導體晶粒104在烘箱中被乾燥。在乾燥之後，無電解電鍍操作被執行。接著，乾膜層壓製程(dry film lamination process)被執行，後續執行乾膜圖案化和銅電鍍(electro Cu-plating)。乾膜接著被移除並且閃蝕和退火製程被執行，以完成傳導層146在凸塊114和囊封物138上方的形成。
在另一實施例中，傳導層146是藉由利用噴霧塗覆、旋轉塗覆或其他合適的塗覆製程將篩網塗層(screen coating)或光阻層沉積以橫跨經暴露的凸塊114和囊封物138的表面144所形成。經重組的晶圓114接著被放置在烘箱中以乾燥光阻層。在乾燥製程之後，UV曝光被使用以圖案化光阻層。去離子(DI)清洗被執行以使想要的跡線圖案形成在光阻層中。無電解電鍍接著被執行以將傳導層146沉積在經圖案化的光阻層中。無電解電鍍之後是清洗和乾燥製程，以移除光阻層並且使經圖案化的傳導層146形成在凸塊114和囊封物138的表面144上方。
轉到圖3f，絕緣層或鈍化層148利用PVD、CVD、印刷、層壓、旋轉塗覆、噴霧塗覆或其他合適的塗覆製程而形成在囊封物138和傳導層146上方。絕緣層148含有由以下所組成的一或多個層：阻焊劑、二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、 氧化鋁(Al2O3)、氧化鉿(HfO2)，苯並環丁烯(BCB)、聚亞醯胺(PI)、聚苯噁唑(PBO)、聚合物或具有類似的結構和絕緣性質的其它材料。絕緣層148的一部分藉由LDA、蝕刻或其他的合適製程被移除，以在傳導層146上方形成多個開口150。開口150暴露傳導層146，以用於後續的電性互連。
在圖3g中，電性傳導凸塊材料利用蒸鍍、電解電鍍、無電解電鍍、球式滴落或網版印刷製程被沉積在開口150中的傳導層146上方。在一實施例中，凸塊材料是以球落模版(ball drop stencil)來沉積，亦即，不需要遮罩。凸塊材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及上述組合，其具有選擇性的助焊溶液。舉例而言，凸塊材料是共晶的Sn/Pb、高鉛焊料或無鉛焊料。凸塊材料利用合適的附接或接合製程被接合至傳導層146。凸塊材料藉由加熱該材料到該材料的熔點之上被回焊以形成球或凸塊152。在一些應用中，凸塊152被回焊第二次以改善與傳導層146的電性接觸。凸塊152亦可被壓縮接合或熱壓縮接合至傳導層146。凸塊152代表被形成在傳導層146上方的一種類型的互連結構。該互連結構亦可使用導電膏、柱形凸塊、微凸塊或其他電性互連件。
經重組的晶圓134接著利用鋸片或雷射切割工具154被單粒化為個別的半導體裝置或封裝160。在單粒化之後，半導體裝置160利用熱烘烤、UV光或機械式剝離從介面層132脫離。
圖4例示單粒化之後的半導體裝置160。半導體晶粒104經由凸塊114和傳導層146被電性連接至凸塊152，以用於外部互連。囊封物138被沉積在半導體晶粒104和背側保護層122周圍。將半導體晶粒104從介面層132脫離暴露了背側保護層122和囊封物138的表面156。囊封物138 的表面156是與背側保護層122的表面共面。
傳導層146被形成在半導體晶粒104和囊封物138的表面144上方。傳導層146允許訊號從半導體晶粒104橫跨半導體裝置160被重新佈線。傳導層146的一部分沿著囊封物138的表面144平行於半導體晶粒104的主動表面110水平延伸，以從凸塊114橫向地重新分佈電性訊號。形成傳導層146以延伸在囊封物138上方(亦即，延伸在半導體晶粒104的覆蓋區外側)為凸塊152的位置和設計佈局提供更好的靈活性。舉例而言，凸塊152的間距被選擇以反映具有工業標準輸入/輸出(I/O)密度的一基板，或者凸塊152的間距和佈局被選擇以與具有獨特I/O密度和圖案的一基板匹配。更好的互連佈局靈活性可使半導體裝置160與更多數量的其他裝置相容。再者，形成傳導層146在囊封物138和半導體晶粒104上(相對於將半導體晶粒104安裝至預先形成的插入物基板而言)減少半導體裝置160的整體厚度或z方向尺寸。
背側保護層122被形成在半導體晶粒104的表面120上。背側保護層122強化並且保護在半導體裝置160內的半導體晶粒104。背側保護層122在環境上保護半導體晶粒104免受外部元件影響並且提供堅硬性和實體支撐以強化半導體晶粒104。背側保護層122減少半導體晶粒104在處理或其他製造製程期間(例如，在囊封物138的沉積期間或在傳導層146的形成期間)會被損壞的可能性。由於背側保護層122使得在製造期間和之後半導體晶粒104較不易受到損壞，增加了良好半導體裝置160的生產量。
因為半導體晶粒104的厚度在如圖1d中所示的背部研磨操作中被減少，所以半導體裝置160具有縮小的z方向尺寸。因為保護層116 在背部研磨期間支撐半導體晶粒104並且背側保護層122在背部研磨之後支撐半導體晶粒104，所以可從半導體晶粒104移除更多部分的基底基板材料102。據此，半導體晶粒104和半導體裝置160的整體厚度被減少。具有背側保護層122的經囊封的半導體晶粒104製造出具有縮小z方向尺寸的堅固半導體裝置160。
圖5例示半導體裝置170。半導體裝置170包括具有經暴露的背表面120的半導體晶粒104。半導體晶粒104經由凸塊114和傳導層146被電性連接至凸塊152，以用於外部互連。
傳導層146被形成在半導體晶粒104和囊封物138的表面144上方。傳導層146允許訊號從半導體晶粒104橫跨半導體裝置160被重新佈線。傳導層146的一部分沿著囊封物138的表面144平行於半導體晶粒104的主動表面110水平延伸，以從凸塊114橫向地重新分佈電性訊號。形成傳導層146以延伸在囊封物138上方(亦即，延伸在半導體晶粒104的覆蓋區外側)為凸塊152的位置和設計佈局提供更好的靈活性。舉例而言，凸塊152的間距被選擇以反映具有工業標準I/O密度的一基板，或者凸塊152的間距和佈局被選擇以與具有獨特I/O密度和圖案的一基板匹配。更好的互連佈局靈活性可使半導體裝置170與更多數量的其他裝置相容。再者，形成傳導層146在囊封物138和半導體晶粒104上(相對於將半導體晶粒104安裝至預先形成的插入物基板而言)減少半導體裝置170的整體厚度或z方向尺寸。
半導體裝置170是藉由將來自圖2c的半導體晶粒104設置在載體130上方而使背側表面120接觸介面層132而形成。製造接著如同圖 3b至圖3g所示而繼續。在使半導體晶粒104從介面層132脫離之後，半導體晶粒104的背表面120與囊封物138的表面156共面。
因為半導體晶粒104的厚度在如圖1d中所示的背部研磨操作中被減少，所以半導體裝置170具有縮小的z方向尺寸。因為保護層116在背部研磨期間支撐半導體晶粒104，所以可從半導體晶粒104移除更多部分的基底基板材料102。據此，半導體晶粒104和半導體裝置170的整體厚度被減少。經暴露的背表面120允許半導體晶粒104有更好的散熱性。利用具有經暴露的背表面120的半導體晶粒104亦進一步減少半導體裝置170的整體厚度。
圖6例示具有被設置於背側保護層122和囊封物138的表面156上方的散熱器182而類似於圖4中的半導體裝置160的半導體裝置180。替代而言，散熱器182被設置於具有經暴露的背表面120的半導體晶粒104上方，亦即，在類似於在圖5中的半導體裝置170的裝置上方。散熱器182是Cu、Al或具有高熱傳導性的其他材料。在一實施例中，背側保護層122是熱介面層(TIM)，其被設置在散熱器182和半導體晶粒104的背表面120之間，以有助於從半導體晶粒104至散熱器182的熱連接和熱的流動。TIM可以是氧化鋁、氧化鋅、氮化硼或粉末化的銀。散熱器182有助於分佈和消散由半導體晶粒104所產生的熱。
在將半導體晶粒104設置於載體上方之前，散熱器182藉由將傳導金屬薄片層合在載體130和介面層132上方而形成在半導體晶粒104上方。半導體晶粒104接著利用拾放操作被安裝至傳導金屬薄片，而凸塊114被定向以遠離傳導金屬薄片。背側保護層或TIM 122包括黏著性材料， 以在原位保持半導體晶粒104於傳導金屬薄片上方。製造製程接著如圖3b至圖3g所示而繼續，而切割工具154切割穿過囊封物138和傳導金屬薄片，亦即，散熱器182，以將經重組的晶圓134單粒化為個別的半導體裝置180。
替代而言，在將經重組的晶圓134從介面層132和載體130取下之後，散熱器182被形成在半導體晶粒104和囊封物138的表面156上方。在移除載體130和介面層132之後，散熱器182的傳導材料利用層壓、PVD、CVD、電解電鍍、無電電鍍製程或其他合適的金屬沉積製程而沉積在半導體晶粒104和囊封物138的表面156上方。具有被形成在半導體晶粒104和囊封物138上方的傳導材料182的經重組的晶圓134接著被單粒化為半導體裝置180。在一實施例中，切割保護膠(dicing tape)或其他支撐載體被附接至經重組的晶圓134，以在散熱器182的形成期間和在單粒化期間支撐經重組的晶圓134。散熱器182消散由半導體晶粒104所產生的熱並且增加半導體裝置180的熱效能和整體功能。
圖7例示具有被設置於半導體晶粒104上方的半導體晶粒192的半導體裝置190。半導體晶粒104具有經暴露的背表面120。替代而言，半導體晶粒192被設置於半導體晶粒104上方，其具有被形成於背表面120上方的背側保護層122。
半導體晶粒192具有背部或非主動表面193以及含有類比或數位電路的主動表面194，類比或數位電路根據電性設計以及晶粒的功能被實作為形成在晶粒內並且電性互連的主動裝置、被動裝置、傳導層以及介電層。舉例而言，電路包括被形成在主動表面194內的一或多個電晶體、二極體以及其他電路元件，以實施類比電路或數位電路(諸如，DSP、ASIC、 MEMS、記憶體或其他訊號處理電路)。半導體晶粒192亦含有IPD(諸如，電感器、電容器以及電阻器)，以用於RF訊號處理。
電性傳導層196利用PVD、CVD、電解電鍍、無電電鍍製程或其他合適的金屬沉積製程而形成在主動表面194上方。傳導層196包括以下所組成的一或多個層：Al、Cu、Sn、Ni、Au、Ag、Pd、SnAg、SnAgCu、CuNi、CuNiAu、CuNiPdAu或其他合適的電性導電材料或它們的組合。傳導層196作用為電性連接至主動表面194上的電路的接觸墊。接觸墊196有助於在半導體晶粒192內的主動電路與外部裝置之間的後續電性互連。
電性傳導凸塊材料利用蒸鍍、電解電鍍、無電解電鍍、球式滴落或網版印刷製程被沉積在接觸墊196上方。凸塊材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及上述組合，其具有選擇性的助焊溶液。舉例而言，凸塊材料是共晶的Sn/Pb、高鉛焊料、或無鉛焊料。凸塊材料利用合適的附接或接合製程被接合至接觸墊196。凸塊材料藉由加熱該材料到該材料的熔點之上被回焊，以形成球或凸塊199。在一些應用中，凸塊199被回焊第二次以改善與接觸墊196的電性連接。凸塊199亦可被壓縮接合或熱壓縮接合至接觸墊196。凸塊199代表被形成在接觸墊196上方的一種類型的互連結構。互連結構亦可使用柱形凸塊、微凸塊或其他電性互連件。
多個直通矽晶穿孔(TSV)198被形成以穿過半導體晶粒192。TSV 198從背表面193延伸至半導體晶粒192的主動表面194。TSV 198是垂直互連結構，其在被設置在背表面193上方的裝置或構件(例如，半導體晶粒104)和被設置在主動表面194上方的裝置或構件(例如傳導層146)之間提供電性互連。
半導體晶粒192被安裝至半導體晶粒104。凸塊114將半導體晶粒104電性和冶金連接至半導體晶粒192的TSV 198。囊封物138被沉積在半導體晶粒104和半導體晶粒192上方和周圍。囊封物138在凸塊114周圍以及在半導體晶粒104的主動表面110和半導體晶粒192的背表面193之間流動。在一實施例中，在沉積囊封物138之前，底部填充被沉積在半導體晶粒104的主動表面110和半導體晶粒192的背表面193之間。
囊封物138接受研磨操作以暴露凸塊199並且平坦化囊封物138的表面144和凸塊199。傳導層146被形成在凸塊199和囊封物138的表面144上方。傳導層146的一部分被電性連接至凸塊199。傳導層146的其他部分是共電的或是被電性隔離，其取決於半導體晶粒104和半導體晶粒192的設計和功能。絕緣層148和凸塊152被形成在傳導層146上方。
半導體晶粒104經由凸塊114、TSV 198、凸塊199和傳導層146被電性連接至凸塊152，以用於外部互連。半導體晶粒192經由凸塊199和傳導層146被電性連接至凸塊152，以用於外部互連。TSV 198將半導體晶粒104電性連接至半導體晶粒192。
傳導層146被形成在半導體晶粒192和囊封物138的表面144上方。傳導層146允許訊號從半導體晶粒104和192橫跨半導體裝置190被重新佈線。傳導層146的一部分沿著囊封物138的表面144平行於半導體晶粒192的主動表面194水平延伸，以從凸塊199橫向地重新分佈電性訊號。形成傳導層146以延伸在囊封物138上方(亦即，延伸在半導體晶粒192的覆蓋區外側)為凸塊152的位置和設計佈局提供更好的靈活性。舉例而言，凸塊152的間距被選擇以反映具有工業標準I/O密度的一基板，或者凸塊152 的間距和佈局被選擇以與具有獨特I/O密度和圖案的一基板匹配。更好的互連佈局靈活性可使半導體裝置190與更多數量的其他基板和裝置相容。再者，形成傳導層146在囊封物138和半導體晶粒192上(相對於將半導體晶粒104和192安裝至預先形成的插入物基板而言)減少半導體裝置190的整體厚度或z方向尺寸。
因為半導體晶粒104的厚度在如圖1d中所示的背部研磨操作中被減少，所以半導體裝置190具有縮小的z方向尺寸。因為保護層116在背部研磨期間支撐半導體晶粒104，所以可從半導體晶粒104移除更多部分的基底基板材料102。據此，半導體晶粒104和半導體裝置190的整體厚度被減少。將具有TSV 198的半導體晶粒192設置於半導體晶粒104上方允許半導體裝置190可併入具有不同功能的多個半導體晶粒於單一個封裝內。在半導體裝置190內連接多個半導體晶粒將增加半導體封裝190的電性效能和整體的功能。
圖8a至圖8h說明製造具有被設置以橫跨半導體裝置的表面的保護層的半導體裝置的方法。圖8a例示含有用於結構支撐的犧牲基底材料(諸如，矽、聚合物、氧化鈹、玻璃、或其他合適的低成本、剛性材料)的載體或暫時性基板200的部分的截面圖。介面層或雙面膠帶202被形成在載體200上方以作為暫時性黏合接合膜、蝕刻停止層或熱脫膜層。來自圖2c的半導體晶粒104利用(舉例而言)拾放操作被設置在載體200和介面層202上方，而背側表面120朝向並且接觸載體200的介面層202。
圖8b例示被安裝至介面層202和載體200以作為重組或重新配置的晶圓204的半導體晶粒104。凸塊114被定向以遠離載體200。半 導體晶粒104藉由介面層202在原位被保持在載體200上方。可重複使用的保護環206被設置在半導體晶粒104周圍。
在圖8c中，囊封物或模製化合物208利用網版印刷、噴霧塗覆、焊膏印刷、壓縮模製、轉移模製、液態囊封模製、真空層壓、旋轉塗覆或其他合適的塗覆方法被沉積在半導體晶粒104和載體200上方。囊封物208被沉積在半導體晶粒104上方和周圍。囊封物208覆蓋凸塊114、主動表面110和半導體晶粒104的四個側表面。囊封物208包括聚合物複合材料(諸如，具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯或具有合適填充物的聚合物)。囊封物208是非傳導的並且在環境上保護半導體晶粒104免受外部元件和污染物影響。
在圖8d中，保護環206被移除，並且囊封物208的表面210接受研磨操作以平坦化囊封物208且暴露凸塊114。研磨器212從表面210移除囊封物208的一部分。研磨操作露出凸塊114的一部分並且使囊封物208具有新的平坦化表面214。在研磨之後，表面214與凸塊114的經暴露的表面共面。
在圖8e中，電性傳導層216利用圖案化和金屬沉積製程(諸如，印刷、PVD、CVD、濺鍍、電解電鍍和無電解電鍍)被形成在凸塊114和囊封物208的表面214上方。傳導層216是以下所組成的一或多個層：Al、Cu、Sn、Ni、Au、Ag或其他合適的電性導電材料。傳導層216的一部分被電性連接至凸塊114。傳導層216的其他部分是共電的或是被電性隔離，其取決於半導體晶粒104的設計和功能。傳導層216操作為被形成在半導體晶粒104上方的RDL。傳導層216提供從凸塊114延伸至半導體晶粒 104和囊封物208上方的其他區域的傳導路徑。
在一實施例中，在暴露凸塊114之後，經重組的晶圓204被放置於高速奈米粒子噴射或雷射印刷機中。傳導層216的跡線接著以想要的圖案被直接印刷在凸塊114和表面214上方。奈米的Cu或Ag跡線被使用以形成傳導層216。在完成印刷之後，跡線被固化或燒結以完成傳導層216的形成。替代而言，跡線在印刷時就被同時(亦即，即時地)燒結。
在另一實施例中，在暴露凸塊114之後，除膠渣操作在凸塊114和囊封物208的表面214上被執行。在除膠渣之後，經囊封的半導體晶粒104在烘箱中被乾燥。在乾燥之後，無電解電鍍操作被執行。接著，乾膜層壓製程被執行，後續執行乾膜圖案化和銅電鍍。乾膜接著被移除並且閃蝕和退火製程被執行，以完成傳導層146的形成。
在另一實施例中，傳導層216是藉由利用噴霧塗覆、旋轉塗覆或其他合適的塗覆製程將篩網塗層或光阻層沉積以橫跨經暴露的凸塊114和囊封物208的表面214所形成。經重組的晶圓204接著被放置在烘箱中以乾燥光阻層。在乾燥製程之後，UV曝光被使用以圖案化光阻層。執行DI清洗以使想要的跡線圖案形成在光阻層中。無電解電鍍接著被執行以將傳導層216沉積在經圖案化的光阻層中。無電解電鍍之後是清洗和乾燥製程，以移除光阻層並且使經圖案化的傳導層216形成在凸塊114和囊封物208的表面214上方。
轉到圖8f，絕緣層或鈍化層218利用PVD、CVD、印刷、層壓、旋轉塗覆、噴霧塗覆或其他合適的塗覆製程而形成在囊封物208和傳導層216上方。絕緣層218含有由以下所組成的一或多個層：阻焊劑、 SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2，BCB、PI、PBO、聚合物或具有類似的結構和絕緣性質的其它材料。絕緣層218的一部分藉由LDA、蝕刻或其他的合適製程移除，以在傳導層216上方形成多個開口。在絕緣層218中的開口暴露傳導層216，以用於後續的電性互連。
電性傳導凸塊材料利用蒸鍍、電解電鍍、無電解電鍍、球式滴落或網版印刷製程被沉積在絕緣層218中的開口中的傳導層216上方。在一實施例中，凸塊材料是以球落模版來沉積，即，不需要遮罩。凸塊材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料以及上述組合，其具有選擇性的助焊溶液。舉例而言，凸塊材料是共晶的Sn/Pb、高鉛焊料、或無鉛焊料。凸塊材料利用合適的附接或接合製程被接合至傳導層216。凸塊材料藉由加熱該材料到該材料的熔點之上被回焊，以形成球或凸塊220。在一些應用中，凸塊220被回焊第二次以改善與傳導層216的電性接觸。凸塊220亦可被壓縮接合或熱壓縮接合至傳導層216。凸塊220代表被形成在傳導層216上方的一種類型的互連結構。該互連結構亦可使用導電膏、柱形凸塊、微凸塊或其他電性互連件。
在圖8g中，暫時性載體200和介面層202是藉由化學蝕刻、機械式剝除(mechanical peel-off)、CMP、機械式研磨(mechanical grinding)、熱烘烤(thermal bake)、雷射掃描(laser scanning)、UV脫膜(UV release)或濕式剝除(wet stripping)而被移除。在移除載體200和介面層202之後，囊封物208的表面221和半導體晶粒104的背表面120被暴露。
背側保護層222接著被形成在半導體晶粒104的表面120和囊封物208的表面221上方。背側保護層222是藉由層壓、網版印刷、旋轉 塗覆、噴霧塗覆或其他合適的塗覆方法所形成。背側保護層222是以下的一或多個層：光敏感聚合物介電膜，其可具有或不具有填充物；非光敏感聚合物介電膜；環氧化合物(epoxy)；環氧樹脂(epoxy resin)；聚合性材料；聚合物複合材料(諸如，具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯或具有合適填充物的聚合物)；墊固性塑膠層壓板；或具有類似絕緣或結構性質的其他材料。背側保護層222是非傳導的並且為半導體晶粒104和經重組的晶圓204提供環境保護和實體支撐。背側保護層222亦可提供散熱性，以改善半導體裝置的熱效能。背側保護層222亦可提供翹曲調控能力，以控制整體的封裝翹曲度。
在圖8h中，經重組的晶圓204被設置在暫時性載體224上方，而背側保護層222朝向載體。類似於介面層202的選擇性介面層或雙面膠帶可被設置在背側保護層222和載體224的表面之間。在一實施例中，背側保護層222被形成在載體224上方，並且接著經重組的晶圓204被安裝在保護層222上，而半導體晶粒104的表面120被設置在保護層222上並與其接觸。
經重組的晶圓204被加熱以固化背側保護層222。經重組的晶圓204接著利用鋸片或雷射切割工具228被單粒化為個別的半導體裝置或封裝230。在單粒化之後，半導體裝置230利用熱烘烤、UV光或機械式剝離從載體224脫離。
圖9例示單粒化之後的半導體裝置230。半導體晶粒104經由凸塊114和傳導層216被電性連接至凸塊220，以用於外部互連。傳導層216被形成在半導體晶粒104和囊封物208的表面214上方。傳導層216的 一部分沿著囊封物208的表面214平行於半導體晶粒104的主動表面110水平延伸，以從凸塊114橫向地重新分佈電性訊號。形成傳導層216以延伸在囊封物208上方(亦即，延伸在半導體晶粒104的覆蓋區外側)為凸塊220的位置和設計佈局提供更好的靈活性。舉例而言，凸塊220的間距被選擇以反映具有工業標準I/O密度的一基板，或者凸塊220的間距和佈局被選擇以與具有獨特I/O密度和圖案的一基板匹配。更好的互連佈局靈活性可使半導體裝置230與更多數量的其他基板和裝置相容。形成傳導層216在半導體晶粒104和囊封物上(相對於將半導體晶粒104安裝至預先形成的插入物基板而言)減少半導體裝置230的整體厚度或z方向尺寸。
背側保護層222被形成在半導體晶粒104和囊封物208上方。背側保護層222覆蓋半導體晶粒104的表面120和囊封物208的表面221。背側保護層222在環境上保護半導體晶粒104免受外部元件影響並且提供堅硬性和實體支撐以強化半導體裝置230。由於背側保護層222的存在，半導體裝置230較不易在後續處理和加工期間受到損壞。由於背側保護層222使得半導體裝置230較不易受到損壞，增加了良好半導體裝置230的整體功能和生產量。
因為半導體晶粒104的厚度在如圖1d中所示的背部研磨操作中被減少，所以半導體裝置230具有縮小的z方向尺寸。因為保護層116在背部研磨期間支撐半導體晶粒104並且背側保護層222提供堅硬性並強化半導體晶粒104和裝置230，所以可從半導體晶粒104移除更多部分的基底基板材料102。據此，半導體晶粒104和半導體裝置230的整體厚度被減少。具有經囊封的半導體晶粒104和覆蓋半導體裝置230整個表面的背側保護層 222的半導體裝置230提供具有縮小z方向尺寸的堅固半導體裝置。
圖10例示具有被設置於半導體晶粒104上方的半導體晶粒192而類似於圖7中的裝置190的半導體裝置236。背側保護層222覆蓋囊封物208和半導體晶粒104的背表面120。半導體晶粒104的凸塊114被電性和冶金連接至半導體晶粒192的TSV198。半導體晶粒192的凸塊199被電性連接至傳導層216。半導體晶粒104經由凸塊114、TSV 198、凸塊199和傳導層216被電性連接至凸塊220，以用於外部互連。半導體晶粒192經由凸塊199和傳導層216被電性連接至凸塊220，以用於外部互連。TSV 198電性連接半導體晶粒104和半導體晶粒192。在半導體裝置236內連接多個半導體晶粒增加半導體封裝236的整體功能。
底部填充材料238利用焊膏印刷、噴射點膠、壓縮模製、轉移模製、液態囊封模製、真空層壓、旋轉塗覆、模製底部填充或其他合適的塗覆方法被沉積在半導體晶粒104的主動表面110和半導體晶粒192的背表面193之間。底部填充238是環氧化合物、環氧樹脂黏著性材料、聚合性材料、膜或其他非傳導的材料。底部填充238被設置在凸塊114周圍。底部填充238是非傳導的並且在環境上保護半導體晶粒免受外部元件和污染物影響。底部填238充亦增加了半導體晶粒104和半導體晶粒192之間的接合強度。
囊封物208被沉積在底部填充材料238、半導體晶粒104和半導體晶粒192周圍。研磨操作被執行以露出凸塊199並且平坦化囊封物208的表面214和凸塊199。傳導層216被形成在凸塊199和囊封物208的表面214上方。傳導層216的一部分被電性連接至凸塊199。傳導層216的 其他部分是共電的或是被電性隔離，其取決於半導體晶粒104和半導體晶粒192的設計和功能。
傳導層216允許訊號從半導體晶粒104和192橫跨半導體裝置236被重新佈線。傳導層216的一部分沿著囊封物208的表面214平行於半導體晶粒192的主動表面194水平延伸，以從凸塊199橫向地重新分佈電性訊號。形成傳導層216以延伸在囊封物208上方(亦即，延伸在半導體晶粒192的覆蓋區外側)為凸塊220的位置和設計佈局提供更好的靈活性。舉例而言，凸塊220的間距被選擇以反映具有工業標準I/O密度的一基板，或者凸塊220的間距和佈局被選擇以與具有獨特I/O密度和圖案的一基板匹配。更好的互連佈局靈活性可使半導體裝置236與更多數量的其他基板和裝置相容。再者，形成傳導層216在囊封物208和半導體晶粒192上(相對於將半導體晶粒104和192安裝至預先形成的插入物基板而言)減少半導體裝置236的整體厚度或z方向尺寸。
背側保護層222覆蓋囊封物208的表面和半導體晶粒104的背表面120。背側保護層222強化半導體裝置236並且在後續處理和加工期間保護半導體晶粒104免受損壞。由於背側保護層222的存在，半導體裝置236較不易在後續處理和加工期間受到損壞。由於背側保護層222使得半導體裝置236較不易受到損壞，增加了良好半導體裝置236的整體功能和生產量。
因為半導體晶粒104的厚度在如圖1d中所示的背部研磨操作中被減少，所以半導體裝置236具有縮小的z方向尺寸。因為保護層116在背部研磨期間支撐半導體晶粒104並且背側保護層222提供堅硬性並且支 撐在裝置236內的半導體晶粒104，所以可從半導體晶粒104移除更多部分的基底基板材料102。據此，半導體晶粒104和半導體裝置236的整體厚度被減少。具有經囊封的半導體晶粒104和192而背側保護層222覆蓋半導體裝置236整個表面的半導體裝置236提供具有縮小z方向尺寸的堅固半導體裝置。將具有TSV 198的半導體晶粒192設置於半導體晶粒104上方允許半導體裝置236可併入具有不同功能的多個半導體晶粒於單一個封裝內。在半導體裝置236內連接多個半導體晶粒將增加半導體封裝236的電性效能和整體的功能。
圖11a至圖11c說明製造具有用於電性連接經堆疊的半導體裝置的導電通孔的半導體裝置的方法。從圖3f繼續，在形成凸塊152於傳導層146上方之後，暫時性載體130和介面層132藉由化學蝕刻、機械式剝除、CMP、機械式研磨、熱烘烤、雷射掃描、UV脫膜或濕式剝除被移除，並且經重組的晶圓134被安裝在載體或暫時性基板240和介面層242上方。圖11a例示被設置在載體240和介面層242上方而凸塊152朝向介面層242並與其接觸的經重組的晶圓134。載體240含有用於結構支撐的犧牲基底材料(諸如，矽、聚合物、氧化鈹、玻璃、或其他合適的低成本、剛性材料)。介面層或雙面膠帶242被形成在載體240上方以作為暫時性黏合接合膜、蝕刻停止層或熱脫膜層。
藉由使用電射246的LDA，多個通孔244被形成以穿過囊封物138的表面156。替代而言，通孔244藉由機械鑽孔、深式反應離子蝕刻(DRIE)或其他合適的形成製程而形成。通孔244完全經由囊封物138從表面144延伸至表面156。
在圖11b中，通孔244利用電解電鍍、無電電鍍製程或其他合適的沉積製程以Al、Cu、Sn、Ni、Au、Ag、Ti、W或其他合適的電性傳導材料填充，以形成導電通孔248。導電通孔248完全經由囊封物138延伸，以在囊封物138的表面144和156之間提供電性互連。傳導層146的一部分被連接至導電通孔248。
電性傳導層或RDL 250利用圖案化和金屬沉積製程(諸如，印刷、PVD、CVD、濺鍍、電解電鍍和無電解電鍍)被形成在導電通孔248和囊封物138的表面156上方。傳導層250包括以下所組成的一或多個層：Al、Cu、Sn、Ni、Au、Ag或其他合適的電性傳導材料。傳導層250的一部分被電性連接至導電通孔248並且操作為被電性連接至導電通孔248的接觸墊。傳導層250的其他部分是共電的或是被電性隔離，其取決於半導體晶粒104和後續被安裝在傳導層250上方的半導體裝置的設計和功能。
在圖11c中，經重組的晶圓134利用鋸片或雷射切割工具252被單粒化為個別的半導體裝置260。在單粒化之後，半導體裝置260利用熱烘烤、UV光或機械式剝離從載體240和介面層242脫離。
圖12例示包括經堆疊的半導體裝置260的半導體封裝262。頂部半導體裝置260的凸塊152被電性和冶金連接至底部半導體裝置260的傳導層250。導電通孔248將頂部半導體裝置260內的半導體晶粒104電性連接至底部半導體裝置260內的半導體晶粒104。任何數目的半導體裝置260皆可在半導體封裝262內被堆疊。頂部半導體裝置260包括接觸墊250，以用於額外的裝置整合。併入半導體裝置260作為半導體封裝262內的頂部裝置產生開放的堆疊配置，亦即，允許額外的半導體裝置或構件被堆疊在頂 部半導體裝置260上方或與其電性連接的一種配置。堆疊多個裝置和構件增加半導體封裝262的整體電性效能和功能。
背側保護層122被形成在半導體晶粒104的表面120上。背側保護層122強化並且保護半導體裝置260內的半導體晶粒104。背側保護層122在環境上保護半導體晶粒104並且提供堅硬性和實體支撐以強化半導體晶粒104。背側保護層122減少半導體晶粒104在處理或其他製造製程期間(例如，在囊封物138的沉積期間或在導電通孔248和傳導層250的形成期間)會被損壞的可能性。背側保護層122減少半導體晶粒104在半導體裝置260的堆疊期間被損壞的可能性。由於背側保護層122使得半導體晶粒104和半導體裝置260較不易受到損壞，增加了良好半導體裝置262的生產量。
因為半導體晶粒104的厚度在如圖1d中所示的背部研磨操作中被減少，所以半導體裝置262具有縮小的z方向尺寸。因為保護層116在背部研磨期間支撐半導體晶粒104並且背側保護層122在背部研磨之後支撐半導體晶粒104，所以可從半導體晶粒104移除更多部分的基底基板材料102。據此，半導體晶粒104和半導體裝置260的厚度被減少。減少半導體裝置260的厚度減少半導體封裝262的整體的z方向尺寸。
形成導電通孔248以穿過囊封物137提供經由半導體裝置260的垂直互連。形成具有垂直互連結構的半導體裝置260允許多個半導體晶粒和裝置在半導體封裝262內被堆疊。併入多個半導體晶粒和裝置增加半導體封裝262的整體電性效能和功能。
圖13說明包括被設置於來自圖11c的半導體裝置260上方 的來自圖9的半導體裝置230之半導體封裝264。半導體裝置230的凸塊220被電性和冶金連接至半導體裝置260的傳導層250。半導體裝置230中的半導體晶粒104經由凸塊114、傳導層216、凸塊220、傳導層250、TSV 248和傳導層146被電性連接至凸塊152，以用於外部互連。導電通孔248提供經由半導體裝置260的垂直互連，並且將半導體裝置230中的半導體晶粒104電性連接至半導體裝置260中的半導體晶粒104。
併入半導體裝置230作為半導體封裝264內的頂部半導體裝置產生封閉的堆疊配置，亦即，不允許額外的半導體裝置或構件被堆疊在頂部半導體裝置上方或與其電性連接的一種配置。然而，任何數目的半導體裝置260或其他半導體構件可在半導體裝置230和半導體裝置260之間被堆疊或是在與半導體裝置230相對的半導體裝置260上方被堆疊。
背側保護層222覆蓋半導體晶粒104的背表面120和囊封物208的表面。背側保護層222在環境上保護半導體晶粒104免受外部元件影響並且提供堅硬性和實體支撐以強化半導體裝置230。由於背側保護層222的存在，半導體裝置230較不易在處理和加工期間受到損壞。舉例而言，背側保護層222減少半導體裝置230在將半導體裝置230附接至半導體裝置260的期間被損壞的可能性。由於背側保護層222使得半導體裝置230較不易受到損壞，增加了良好半導體裝置264的整體功能和生產量。
背側保護層122被形成在半導體晶粒104的表面120上。背側保護層122強化並且保護半導體裝置260內的半導體晶粒104。背側保護層122減少半導體晶粒104在處理或其他製造製程期間被損壞的可能性。背側保護層122亦減少半導體裝置260在將半導體裝置230附接至半導體裝置 260的期間被損壞的可能性。由於背側保護層122使得半導體裝置260較不易受到損壞，增加了良好半導體裝置264的生產量。
因為在半導體裝置230和260內的半導體晶粒104的厚度在如圖1d中所示的背部研磨操作中被減少，所以半導體裝置264具有縮小的z方向尺寸。因為保護層116在背部研磨期間支撐半導體晶粒104並且背側保護層122和222在背部研磨之後提供堅硬性並支撐半導體晶粒104，所以可從半導體晶粒104移除更多部分的基底基板材料102。據此，半導體晶粒104和半導體裝置230和260的厚度被減少。減少半導體裝置230和260的厚度減少半導體封裝264的整體的z方向尺寸。
被形成以穿過囊封物137的導電通孔248提供經由半導體裝置260的垂直互連。形成具有垂直互連結構的半導體裝置260允許半導體裝置230被堆疊在半導體裝置260上方。將多個半導體裝置併入於半導體封裝264內增加半導體封裝262的電性效能和整體的功能。
儘管已經詳細地說明了本發明一或更多之實施例，然該領域中習知此技術者將理解的是，在不違反在以下申請專利範圍中所提的本發明之範疇的情況下，可以從事這些實施例的修改與變更。

Claims (15)

  1. 一種製造半導體裝置的方法，其包括：提供半導體晶圓，其包括形成在所述半導體晶圓上方的多個凸塊；形成第一保護層於與所述凸塊相對的所述半導體晶圓上方；在形成所述第一保護層之後，將所述半導體晶圓單粒化為多個第一半導體晶粒；在將所述半導體晶圓單粒化之後將多個所述第一半導體晶粒設置在載體上，所述第一保護層朝向所述載體且所述凸塊背對所述載體；沉積囊封物於所述第一半導體晶粒和所述載體上方，其中所述囊封物的背表面與所述第一保護層的表面共平面；平坦化所述囊封物以暴露所述凸塊，其中平坦化所述囊封物使所述囊封物的表面與所述凸塊的表面共平面；以及將傳導層直接形成於所述凸塊的所述表面和所述囊封物的所述表面上，其中所述傳導層的部分從多個所述凸塊中的第一凸塊延伸至所述半導體晶粒的覆蓋區之外。
  2. 如申請專利範圍第1項所述的方法，進一步包括背部研磨所述半導體晶圓以使所述半導體晶圓有新的背側表面；以及將所述第一保護層直接形成在所述新的背側表面上。
  3. 如申請專利範圍第1項所述的方法，進一步包括將第二半導體晶粒設置於所述第一半導體晶粒上方。
  4. 如申請專利範圍第1項所述的方法，進一步包括將導電通孔形成在所述傳導層上方以穿過所述囊封物。
  5. 一種製造半導體裝置的方法，其包括：提供第一半導體晶粒，其包括形成在所述第一半導體晶粒的主動表面上的傳導凸塊；形成第一保護層於所述第一半導體晶粒上方；將所述第一半導體晶粒設置在載體上方，所述傳導凸塊背對所述載體；沉積囊封物於所述第一半導體晶粒和所述載體上方；平坦化所述囊封物以暴露所述傳導凸塊，其中平坦化所述囊封物使所述囊封物的表面與所述傳導凸塊的表面共平面；以及將第一傳導層形成於所述囊封物上方且與所述傳導凸塊連接，其中所述第一傳導層在所述半導體晶粒的覆蓋區之外延伸。
  6. 如申請專利範圍第5項所述的方法，進一步包括將散熱器(heat spreader)設置於所述第一保護層和所述囊封物上方。
  7. 如申請專利範圍第5項所述的方法，進一步包括形成第二保護層於與所述第一保護層相對的所述第一半導體晶粒上方。
  8. 如申請專利範圍第7項所述的方法，進一步包括移除與所述第二保護層相對的所述第一半導體晶粒的部分。
  9. 如申請專利範圍第5項所述的方法，進一步包括：形成傳導通孔以穿過所述囊封物；以及形成第二傳導層於與所述第一傳導層相對的所述囊封物的第二表面上方，所述傳導通孔從所述第一傳導層延伸至所述第二傳導層。
  10. 一種製造半導體裝置的方法，其包括：提供第一半導體晶粒；將所述第一半導體晶粒設置在載體上；沉積囊封物於所述第一半導體晶粒和所述載體上方，其中所述囊封物實質覆蓋所述半導體晶粒的主動表面和側表面；將在所述第一半導體晶粒的所述主動表面上方的所述囊封物平坦化；以及將傳導層形成於所述囊封物上方且與所述半導體晶粒電性連接。
  11. 如申請專利範圍第10項所述的方法，進一步包括將保護層形成在所述第一半導體晶粒上。
  12. 如申請專利範圍第11項所述的方法，進一步包括將所述保護層形成以在所述囊封物上方延伸。
  13. 如申請專利範圍第10項所述的方法，進一步包括形成傳導通孔以穿過所述囊封物。
  14. 如申請專利範圍第10項所述的方法，進一步包括將散熱器設置於所述第一半導體晶粒上方。
  15. 如申請專利範圍第10項所述的方法，其中所述第一半導體晶粒的表面與所述囊封物的表面共平面。
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