TWI528437B - 半導體裝置及形成犧牲保護層以於單一化過程中保護半導體晶粒邊緣之方法 - Google Patents

半導體裝置及形成犧牲保護層以於單一化過程中保護半導體晶粒邊緣之方法 Download PDF

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TWI528437B
TWI528437B TW100107876A TW100107876A TWI528437B TW I528437 B TWI528437 B TW I528437B TW 100107876 A TW100107876 A TW 100107876A TW 100107876 A TW100107876 A TW 100107876A TW I528437 B TWI528437 B TW I528437B
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semiconductor
semiconductor die
layer
protective layer
insulating layer
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TW201142932A (en
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林耀劍
陳康
方建敏
馮霞
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史達晶片有限公司
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Description

半導體裝置及形成犧牲保護層以於單一化過程中保護半導體晶粒邊緣之方法 【本國優先權之主張】
該非暫時申請案主張2010年3月12日提出申請、序號61/313,208美國暫時申請案之優先權的權益，其係並且根據35 U.S.C.§120主張對先前母案的優先權。
本發明一般係關於半導體裝置，且更特別地係關於一種形成暫時平面保護層以在單一化期間內保護半導體晶粒邊緣的半導體裝置與方法。
在現代電子產品中通常可發現半導體裝置。半導體裝置在電性元件的數目與密度上會有變化。個別的半導體裝置一般包含一種電性元件，例如發光二極體(LED)、小訊號電晶體、電阻器、電容器、電感器以及功率金屬氧化物半導體場效電晶體(MOSFET)。積體半導體裝置基本上包含數百至數百萬個電性元件。積體半導體裝置的實例包括微控制器、微處理器、電荷耦合裝置(CCD)、太陽能電池與數位微鏡裝置(DMD)。
半導體裝置進行廣範圍的功能，譬如訊號處理、高速計算、傳送與接收電磁訊號、控制電子裝置、將太陽光轉換成電、以及產生電視顯示器用的視覺投射。半導體裝置可在娛樂、通訊、功率轉換、網路、電腦與消費者產品的領域中被發現。半導體裝置亦可在軍事應用、航空、汽車、工業控制器與辦公室設備中被發現。
半導體裝置利用半導體材料的電性特性。半導體材料的原子結構促使其導電性藉由施加電場或基極電流或經由摻雜製程而被操縱。摻雜將雜質引入半導體材料內，以操作並且控制半導體裝置的傳導率。
一種半導體裝置包含主動與被動電性結構。包括雙極性與場效電晶體的主動結構，其係會控制電流的流動。藉由改變電場與基極電流之摻雜與施加的層級，電晶體可促進或限制電流的流動。包括電阻器、電容器與電感器的被動結構，其係可在進行許多電性功能所必要的電壓與電流之間產生關係。被動與主動結構可被電性連接，以形成電路，其係致使半導體裝置進行高速計算與其他有用功能。
半導體裝置通常可使用兩複雜製造製程來製造，亦即前端製造與後端製造，每一個均潛在地包含數百個步驟。前端製造包含將複數個晶粒形成在半導體晶圓表面上。每一個晶粒基本上相等，其係並且包含藉由電性連接主動與被動元件所形成的電路。後端製造包含從該拋光晶圓將個別晶粒單一化，並且將該晶粒封裝，以提供結構性支撐與環境隔離。
半導體製造的一個目標係為產生更小的半導體裝置。更小的裝置基本上消耗更少功率、具有更高性能，以及更有效率地生產。此外，更小的半導體裝置具有更小足跡，其係對更小的最終產品而言是期望的。更小的晶粒尺寸可藉由改善前端製程來得到，其係會造成具有更小、更高密度之主動與被動元件的晶粒。藉由改善電性互連與封裝材料，後端製程會造成具有更小足跡的半導體裝置封裝物。
一種半導體晶圓包含由切割道所隔開的複數個半導體晶粒或元件。該半導體晶圓可使用鋸片刀片或雷射切割工具、經由該切割道而被單一化成個別的半導體晶粒。一旦被單一化，該半導體晶粒則可被安裝到一暫時載體，以便形成一集結互連結構，以用於一扇出晶圓級晶片尺寸封裝(Fo-WLCSP)。更明確地藉由旋轉鋸片刀片的影響，在該單一化製程期間內，該半導體晶粒會沿著晶粒邊緣受到剝離與破裂或其它損害。金屬毛邊可在單一化期間內沿著切割道來發生，其係會在形成該集結互連結構的時候造成電性短路。在該半導體晶粒具有不均勻或高拓樸的情況下，該晶粒與該載體之間的黏著可為弱的，其可能會導致該互連集結製程期間內的缺陷。
在單一化期間內保護該半導體晶粒以及在該集結互連製程期間內提供一平面表面於該晶粒與該載體之間的需要是存在的。於是，在一種實施例中，本發明係為一種製造半導體裝置的方法，包含以下步驟：提供一種半導體晶圓，其係包含由一切割道所隔開的複數個半導體晶粒；形成一第一絕緣層於該半導體晶圓上；形成一保護層於第一絕緣層上，其係包括該半導體晶粒沿著該切割道的一邊緣；將該半導體晶圓單一化穿過該保護層與切割道，以隔開該半導體晶粒，同時保護該半導體晶粒的該邊緣；以該保護層來引導，將該半導體晶粒安裝到一載體；將一封裝材料沈積在該半導體晶粒與載體上；移除該載體與保護層；以及將一集結互連結構形成在該半導體晶粒與封裝材料上。
在另一種實施例中，本發明係為一種製造半導體裝置的方法，包含以下步驟：提供包含複數個半導體晶粒的一半導體晶圓；將一第一絕緣層形成在該半導體晶圓上；將一保護層形成在第一絕緣層上；將該半導體晶圓單一化穿過該保護層，以隔開該半導體晶粒，同時保護該半導體晶粒的邊緣；將該半導體晶粒安裝到一載體；將一封裝材料沈積在該半導體晶粒與載體上；移除該載體與保護層；以及將一集結互連結構形成在該半導體晶粒與封裝材料上。
在另一種實施例中，本發明係為一種製造半導體裝置的方法，包含以下步驟：提供一種半導體晶粒；形成一第一絕緣層於該半導體晶粒上；形成一保護層於第一絕緣層上；以該保護層來引導；將該半導體晶粒安裝到一載體；將一封裝材料沈積在該半導體晶粒與載體上；移除該載體與保護層；以及將一集結互連結構形成在該半導體晶粒與封裝材料上。
在另一種實施例中，本發明係為一種半導體裝置，其係包含：一半導體晶粒以及形成於該半導體晶粒上的第一絕緣層。一保護層係形成於第一絕緣層上。一封裝材料係沈積在該半導體晶粒上。一集結互連結構係形成在該半導體晶粒與封裝材料上。
本發明係在參考圖式之以下說明中的一或更多個實施例中被說明，其中相同的數字代表相同或類似的元件。當本發明根據最佳模式來說明以得到本發明目的時，所屬技術領域中具有通常知識者將理解到，其係意圖涵蓋被包括在以下發明與圖式所支持之附加申請專利範圍與它們等同物所定義之本發明精神與範圍內的替代、變更與等同物。
半導體裝置一般可使用兩複雜製造製程來製造：前端製造與後端製造。前端製造包含將複數個晶粒形成在半導體晶圓表面上。在該晶圓上的每一個晶粒均包含主動與被動電性元件，其係會被電性連接以形成功能性電路。主動電性元件，譬如電晶體與二極體，其係具有控制電流流動的能力。被動電性元件，譬如電容器、電感器、電阻器與變壓器，其係會在進行電路功能所必要的電壓與電流之間產生關係。
藉由一連串製程步驟，包括摻雜、沈積、光學微影、蝕刻與平面化，被動與主動元件係被形成在半導體晶圓表面上。藉由譬如離子植入或熱擴散的技術，摻雜可將雜質引入到半導體材料內。該摻雜製程修改在主動裝置中半導體材料的導電率，以將該半導體材料轉換成絕緣體、導體，或者因應電場或基極電流來動態地改變該半導體材料導電率。電晶體包含為了當施加電場或基極電流時使該電晶體促進或限制電流流動而必須排列之改變摻雜種類與程度的區域。
主動與被動元件係藉由具有不同電特性的材料層所形成。該些層可藉由沈積材料種類所部份決定的種種沈積技術來形成。例如，薄膜沈積包含化學氣相沈積(CVD)、物理氣相沈積(PVD)、電解電鍍以及無電電鍍製程。每一層一般均會被圖案化，以在元件之間形成主動元件、被動元件或電性連接部份。
該些層可使用光學微影來圖案化，其係包含將例如光阻的光敏材料沈積在欲被圖案化之層上。一圖案可使用光線從一光罩被傳遞到該光阻。在一個實施例中，受到光線的該光阻圖案部份可使用溶劑來移除，以暴露欲被圖案化的底層部份。在另一個實施例中，沒有受到光線的光阻圖案部份，該負光阻，其係會使用溶劑來移除，以暴露欲被圖案化的底層部份。剩餘的光阻會被移除，而留下一圖案化層。或者，某些種類的材料會被圖案化，其係藉由使用譬如無電與電解電鍍的技術，將該材料直接沈積在由先前沈積/蝕刻製程所形成的區域或空隙內。
將薄膜材料沈積在現存圖案上，其係會誇大該底部圖案並且產生一非均勻的平表面。就產生更小且更密集封裝的主動與被動元件而言，均勻平表面是必要的。平面化可被使用來從該晶圓表面移除材料，並且產生一均勻的平表面。平面化包含以拋光襯墊將該晶圓表面拋光。研磨材料與腐蝕化學藥劑會在拋光期間內被添加到該晶圓表面。該研磨機械動作與該化學藥劑腐蝕動作之組合，其係會將任何不規則拓樸移除，以導致均勻的平表面。
後端製造意指將該拋光晶圓切割或單一化成個別晶粒，隨後並且將該晶粒封裝，以用於結構性支撐與環境隔離。為了將該晶粒單一化，該晶圓會沿著稱為切割道或劃線區之晶圓的非功能性區域被劃線與折斷。該晶圓可使用雷射切割工具或鋸片刀片被單一化。在單一化以後，該個別晶粒會被安裝到一封裝基板，其係包括用於與其他系統元件互連的接腳或接觸襯墊。形成在半導體晶粒上的接觸襯墊隨後會被連接到在該封裝物內的接觸襯墊。該電性連接可以銲料凸塊、柱形凸塊、導電膏或佈線接合來進行。一種封裝材料或其它模鑄材料會被沈積在封裝物上，以提供物理支撐與電性隔離。該拋光的封裝物隨後會被插入於電性系統內，且該半導體裝置的功能對其他系統元件而言係為有效的。
圖1顯示擁有具有複數個半導體封裝物安裝於其表面之晶片載體基板或印刷電路板(PCB)52的電子裝置50。取決於該應用，電子裝置50具有一種半導體封裝物或複數種半導體封裝物。為了顯示之目的，不同種類的半導體封裝物係被顯示於圖1中。
電子裝置50係為獨立自足的系統，其係使用該半導體封裝物來進行一或更多電性功能。或者，電子裝置50係為更大系統的子元件。例如，電子裝置50係為部份的行動電話、個人數位助理(PDA)、數位影音照相機(DVC)或其它電子通訊裝置。或者，電子裝置50係為可被插入於電腦內的圖形卡、網路介面卡或其它訊號處理卡。該半導體封裝物包括微處理器、記憶體、特殊應用積體電路(ASIC)、邏輯電路、類比電路、射頻電路、離散裝置或其它半導體晶粒或電性元件。對這些被市場接受的產品而言，微型化與輕量化是必要的。半導體裝置之間的距離必須被減少，以得到更高的密度。
在圖1中，PCB52提供一般性基板，以用於被安裝在PCB上之半導體封裝物的結構性支撐與電性互連。傳導訊號軌跡54使用蒸發、電解電鍍、無電電鍍、網版印刷或其它適當的金屬沈積製程而被形成在PCB52的表面上或諸層內。訊號軌跡54提供用於半導體封裝物、安裝元件與其他外部系統元件之任一個之間的電性溝通。軌跡54亦可同樣地提供功率與接地連接到每一個半導體封裝物。
在一些實施例中，半導體裝置具有兩封裝級。第一級封裝係為一種用於將半導體晶粒機械與電性附著到中間載體的技術。第二級封裝包含將該中間載體機械與電性附著到PCB。在其他實施例中，半導體裝置僅僅具有第一級封裝，在此該晶粒會被機械且電性地直接安裝到PCB。
為了顯示之目的，數種第一級封裝，包括接合佈線封裝56以及覆晶58，其係會被顯示於PCB52上。此外，數種第二級封裝，包括球柵陣列(BGA)60、凸塊晶片載體(BCC)62、雙排型封裝(DIP)64、地格柵陣列(LGA)66、多晶片模組(MCM)68、四方形扁平無引線封裝(QFN)70以及四方形扁平封裝72，其係顯示被安裝在PCB52上。依據該系統需求規格，任何半導體封裝物之組合，以第一與第二級封裝型態以及其他電子元件的任何組合來架構，其係均可被連接到PCB52。在一些實施例中，電子裝置50包括單一附著的半導體封裝物，同時其他實施例則需要多重互連封裝物。藉由將一或更多個半導體封裝物組合在一單一基板上，製造商可將事先製造的元件合併到電子裝置與系統內。因為該半導體封裝物包括複雜的功能，所以電子裝置則可使用較便宜的元件以及流線製造製程來製造。結果產生的裝置則不太可能失敗，並且製造上不會太貴，其係會造成消費者的成本下降。
圖2a-2c顯示典型半導體封裝物。圖2a顯示被安裝在PCB52上之DIP64的進一步細節。半導體晶粒74包括一主動區域，其包含類比或數位電路，其係實施當作被形成在該晶粒內的主動裝置、被動裝置、傳導層與介質層，其係並且根據該晶粒的電性設計而被電性互連。例如，該電路包括被形成在半導體晶粒74主動區域內的一或更多電晶體、二極體、電感器、電容器、電阻器與其他電路元件。接觸襯墊76係為一或更多層的傳導材料，譬如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)，其係並且電性連接到被形成在半導體晶粒74內的電路元件。在DIP64組裝期間內，使用金-矽共晶層或黏著材料，譬如熱環氧或環氧樹脂，半導體晶粒74會被安裝到中間載體78。該封裝物體部包括一絕緣性封裝材料，譬如聚合物或陶瓷。導體引線80與接合佈線82會提供電性互連於半導體晶粒74與PCB52之間。封裝材料84會被沈積在該封裝物上，以用於環境保護，其係藉由避免濕氣與顆粒進入該封裝物並且污染晶粒74或接合佈線82。
圖2b顯示安裝在PCB52上之BCC62的進一步細節。半導體晶粒88係使用下填或環氧樹脂黏著材料92被安裝在載體90上。接合佈線94提供第一級封裝互連於接觸襯墊96與98之間。模鑄化合物或封裝材料100會被沈積在半導體晶粒88與接合佈線94上，以提供物理支撐與電性絕緣給該裝置。接觸襯墊102係使用適當的金屬沈積製程，譬如電解電鍍或無電電鍍，而被形成在PCB52的表面上。接觸襯墊102會被電性連接到在PCB52中的一或更多傳導訊號軌跡54。凸塊104係形成在BCC62的接觸襯墊98以及PCB52的接觸襯墊102之間。
在圖2C中，半導體晶粒58係以覆晶型第一級封裝而面向下地安裝到中間載體106。半導體晶粒58的主動區域108包含類比或數位電路，其係被實施當作根據該晶粒之電性設計而形成的主動裝置、被動裝置、傳導層與介質層。例如，該電路可包括一或更多個電晶體、二極體、電感器、電容器、電阻器與其他電路元件於主動區域108內。半導體晶粒58係經由凸塊110被電性與機械性連接到載體106。
BGA60係使用凸塊112被電性且機械性連接到具有BGA型第二級封裝的PCB52。半導體晶粒58會經由凸塊110、訊號線114與凸塊112而電性連接到在PCB52中的傳導訊號軌跡54。一種模鑄化合物或封裝材料116係被沈積在半導體晶粒58與載體106上，以提供物理性支撐與電性絕緣給該裝置。該覆晶半導體裝置提供從半導體晶粒58上主動裝置到PCB52上傳導軌跡的短導電路徑，以便減少訊號傳播距離，降低電容並且改善整個電路性能。在另一個實施例中，半導體晶粒58可使用不具有中間載體106的覆晶型第一級封裝而被機械且電性地直接連接到PCB52。
相關於圖1與2a-2c，圖3a-3i顯示一種將暫時保護層形成在不均勻絕緣層上的製程，以將半導體晶粒平面化並且在單一化期間內保護晶粒邊緣。圖3a顯示半導體晶圓120，其係具有基底基板材料122，譬如矽、鍺、砷化鎵、磷化銦、或碳化矽，以用於結構性支撐。複數個半導體晶粒或元件124係被形成在切割道126所隔開的晶圓120上，如以上所描述。
圖3b顯示一部份半導體晶圓120的截面圖。每一個半導體晶粒124皆具有背表面128與主動表面130，其係包含類比或數位電路，其係被實施當作形成在該晶粒內並且根據該晶粒的電性設計與功能而被電性互連的主動裝置、被動裝置、傳導層以及介質層。例如，該電路包括被形成在主動表面130內的一或更多電晶體、二極體與其他電路元件，以實施類比電路或數位電路，譬如數位訊號處理器(DSP)、ASIC、記憶體或其它訊號處理電路。半導體晶粒124亦可包含積體被動裝置(IPD)，譬如用於射頻訊號處理的電感器、電容器與電阻器。在一種實施例中，半導體晶粒124係為覆晶型半導體晶粒。
導電層132係使用PVD、CVD、電解電鍍、無電電鍍製程或其它適當的金屬沈積製程而形成在主動表面130上。傳導層132係為鋁、銅、錫、鎳、金、銀或其它適當導電材料的其中一或更多層。在一種實施例中，傳導層132在主動表面130上延伸0.6微米(μm)或更多。傳導層132操作當作接觸襯墊，以電性連接到在主動表面130上的電路。
在圖3c中，使用PVD、CVD、網版印刷、旋塗、噴塗、燒結或熱氧化，絕緣或被動層134係被保角地施加到主動表面130與傳導層132上。絕緣層134包含二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、氧化鋁(Al2O3)、聚亞醯胺、聚苯并噁唑(PBO)、聚合物介質材料或具有類似絕緣與結構特性之其它材料的其中之一或更多層。在一個實施例中，絕緣層134的厚度大於0.6μm。絕緣層134會被標記為具有第一部份134a於主動表面130上，以及第二部份134b於傳導層132上。由於絕緣層134保角應用在傳導層132上，第二部份134b相關於主動表面130具有高拓樸。於是，絕緣層134一般具有不均勻的拓樸或非平面表面。一部份絕緣層134b會被移除，以暴露傳導層132，如圖3d所示。一部份絕緣層134b仍然在傳導層132上，以導致絕緣層134的不均勻拓樸或非平面表面。
在圖3e中，使用網版印刷、旋塗、噴塗與疊層，覆蓋暫時保護平面化層136係被形成在絕緣層134與傳導層132上，同時呈晶圓形式。在將暫時保護平面化層136沈積以後，額外的處理，譬如紫外線曝光與熱處理，其係可被施加，以提供必要的黏著與機械特性。暫時保護平面化層136包含一或更多層光阻、液體塗層材料、乾膜、聚合物膜、聚合物合成物或其它材料，其係具有柔順性、結構性支撐、平面化能力、在110-160℃達5至120分鐘之熱穩定性以及在封裝製程以後簡單剝離的特性。保護平面化層136係為一暫時或犧牲層，其係被使用來將絕緣層134的不均勻拓樸平面化。該暫時保護平面化層136填滿絕緣層134之不均勻部份周圍，以產生一平面表面135。在一個實施例中，暫時保護平面化層136的厚度係為5至25μm。
在一個實施例中，暫時保護平面化層136可在沒有圖案化之下覆蓋半導體晶圓或基板120的整個表面，包括半導體晶粒124與切割道126，如圖3f所示。在圖3g中，使用鋸片刀片或雷射切割工具137，將半導體晶圓120單一化，穿過絕緣層134、暫時保護平面化層136、與切割道126，而成個別半導體晶粒124。
或者，暫時保護平面化層136會被圖案化，以具有溝渠或溝槽138形成在切割道126上，如圖3h所示。溝渠138的寬度(WT)小於切割道126的寬度(WS)，例如WT會被做成小於WS 10μm，暫時保護平面化層136則重疊切割道126每一邊至少5μm。鋸片刀片或雷射切割工具137的寬度係顯示為維度Wc。假如傳導層139被形成在切割道126上的話，那麼WT會做成比傳導層139最寬部份的寬度還小10μm，暫時保護平面化層136則重疊傳導層139每一邊至少5μm。
藉由移除具有2-7通道的金屬、絕緣材料與基底半導體材料，可將一雷射使用來形成溝渠或溝槽138於切割道中。該雷射會減少絕緣材料的破裂，特別低介質常數(k)的材料，其係可發生在以鋸片刀片或切割工具137所進行的機械切割期間內。在雷射激發以前，暫時保護平面化層136會被沈積在切割道126上。保護平面化層136提供用於方便控制介質厚度，以額外保護在可靠性測試中的半導體晶粒124。此外，暫時保護平面化層136有助於避免在圖4c中後封裝製程中的晶粒位移與飛行晶粒問題。暫時保護平面化層136亦有助於避免晶圓表面免於切割灰塵爆炸以及在機械切割製程中的損害。
圖3i顯示具有凹口141之開口140的替代圖案。在任何情形中，暫時保護平面化層136保護半導體晶粒124的鋸口邊緣免於剝離與破裂，以及在單一化期間內，抑制沿著切割道126或晶粒邊緣的金屬凸出成形與剝層。
相關於圖1與2a-2c，圖4a-4j顯示一種將擁有具有犧牲保護層之半導體晶粒的晶圓級晶片尺寸封裝形成到平面不均勻表面的製程。圖4a顯示一部份基板或載體142，其係包含暫時或犧牲基底材料，譬如鋼、鐵合金、矽、聚合物、氧化鈹或其它適當低成本、剛性材料，以用於結構性支撐。一界面層或雙邊帶144係形成在載體142上，以做為暫時黏著接合薄膜或蝕刻停止層。在一種實施例中，界面層144係可釋放熱或光線。
來自圖3a-3i的半導體晶粒124係使用選擇與放置操作而被置於並且安裝到載體124上。圖4b顯示被安裝到載體142的半導體晶粒124，其係具有朝著界面層144與載體142而定位之暫時保護平面化層136的平面表面135。暫時保護平面化層136的平面表面135，其係會藉由增加有效的接觸表面面積以及將形成於半導體晶粒124表面與界面層144之間空隙最小化，而來促進半導體晶粒124到界面層144的黏著或接合強度。載體142延伸超過在圖4b所示的尺度，以用於晶圓級多晶粒附著。許多半導體晶粒124可被安裝到載體142。
在圖4c中，使用膠膏印刷、壓縮模鑄、傳送模鑄、液體封裝模鑄、真空疊層、旋塗或其它適當施加器，封裝材料或模鑄化合物146會被沈積在存在有暫時保護平面化層136的半導體晶粒124與界面層144上。封裝材料146係為聚合物合成材料，譬如具有充填物的環氧樹脂、具有充填物的環氧丙烯酸、或具有適當充填物的聚合物。封裝材料146係為非傳導性，其係並且可在環境上保護半導體裝置免於受到外部元件與污染。
在圖4d中，載體142與界面層144係藉由化學蝕刻、機械脫落、CMP、機械研磨、熱烘焙、雷射掃瞄或濕式剝離來移除，以暴露暫時保護平面化層136以及封裝材料146。
暫時保護平面化層136係藉由剝落來移除，如圖4e所示。或者，暫時保護平面化層136可用去離子(DI)水噴霧與清洗或者藉由溶劑或化學剝離來移除。暫時保護平面化層136提供許多有利的優點給半導體晶粒124，包括減少在晶圓切割期間內的晶粒邊緣剝離與破裂、減少在封裝期間內的飛行晶粒、減少在晶圓切割期間內的傳導凸珠形成、對介質厚度的簡單控制、以及減少在晶圓單一化期間內主動表面130上的灰塵損害。
在另一實施例中，從圖4d持續，背面研磨膠帶150會被施加到封裝材料146以及暫時保護平面化層136，如圖4f所示。一部份封裝材料146表面152係藉由研磨器154來移除，以將封裝材料平面化並且將半導體晶粒124的背面表面128暴露。暫時保護平面化層136隨後會在研磨操作以後用背面研磨膠帶來移除，而使絕緣層134與傳導層132的背面表面128暴露，如圖4g所示。
在圖4h中，使用PVD、CVD、網版印刷、旋塗、噴塗、燒結或熱氧化，絕緣或鈍化層156會被形成在封裝材料152的表面158上，其係與表面128以及152相對。絕緣層156包含一或更多層聚亞醯胺、苯環丁烯(BCB)、PBO、低溫(＜280℃)固化聚合物介質、或具有類似絕緣與結構特性的其他材料。一部份絕緣層156會被移除，以暴露傳導層132。
在圖4i，使用圖案化與金屬沈積製程，譬如PVD、CVD、濺射、電解電鍍與無電電鍍，導電層或重分配層(RDL)160會被形成在絕緣層156與傳導層132上。傳導層160係為鋁、銅、鈦/銅、鈦鎢/銅、錫、鎳、金、銀或其它適當導電材料的其中一層或更多層。傳導層160會被電性連接到傳導層132。
使用PVD、CVD、網版印刷、旋塗、噴塗、燒結或熱氧化，絕緣或鈍化層162係被形成在絕緣層156與傳導層160上。絕緣層162包含聚亞醯胺、苯環丁烯、PBO、低溫(＜280℃)固化聚合物介質、或具有類似絕緣與結構特性之其他材料的其中一層或更多層。一部份絕緣層162會被移除，以暴露傳導層160。額外RDL層，包括傳導與絕緣層，可被建立以做為每一設計必要條件。
在圖4j中，使用蒸發、電解電鍍、無電電鍍、球墜落或網版印刷製程，導電凸塊材料會被沈積在該暴露傳導層160上。該凸塊材料係為鋁、錫、鎳、金、銀、鉛、鉍、銅、銲料與其組合，其係具有選擇性溶液流。例如，凸塊材料係為共晶錫/鉛、高鉛銲料、或無鉛銲料。凸塊材料使用適當的附著或接合製程而被接合到傳導層160。在一個實施例中，該凸塊材料可藉由將該材料加熱超過其熔點而回流，以形成圓球或凸塊164。在一些應用中，凸塊164可回流第二次，以改善到傳導層160的電性接觸。該些凸塊亦可被壓縮接合到傳導層160。凸塊164代表一種可形成在傳導層160上的互連結構。該互連結構亦可使用柱形凸塊、微凸塊或其它電性互連。
圖5顯示另一個實施例，類似圖4j，其係具有淺孔穴或通道170形成在傳導層160與凸塊164以下的封裝材料146中。在移除暫時保護平面化層136以前，淺孔穴170可藉由將在圖4d中的封裝材料146雷射鑽孔5-50μm的深度而來形成。淺孔穴170提供傾倒支撐於墜落試驗(DT)中以及電板溫度循環(TcoB)測試。淺孔穴170亦可用絕緣層156來促進再鈍化。
圖6顯示另一個實施例，類似圖4j，其係具有淺圓腔或通道172形成在傳導層160與凸塊164以下之半導體晶粒124周圍的封裝材料146中。在移除暫時保護平面化層136以前，淺圓腔172可藉由將在圖4d中的封裝材料146雷射鑽孔5-50μm的深度而來形成。淺圓腔172提供傾倒支撐於DT以及TcoB測試中。此外，在移除暫時保護平面化層136以前，雷射可修整在圖4d中半導體晶粒142周圍之封裝材料146的邊緣174。
圖7顯示另一個實施例，類似圖4j，其係具有淺孔穴或通道178形成在傳導層160與凸塊164以下之半導體晶粒124周圍的封裝材料146中。此外，淺孔穴或通道180可形成在半導體晶粒124邊緣周圍的封裝材料146中。在移除暫時保護平面化層136以前，淺孔穴178-180可藉由將在圖4d中的封裝材料146雷射鑽孔5-50μm的深度而來形成。淺孔穴178-180提供傾倒支撐於DT以及TcoB測試中。
圖8顯示另一個實施例，類似圖4j，其係具有淺孔穴或通道182形成在傳導層160與凸塊164以下之半導體晶粒124周圍的封裝材料146中。此外，淺孔穴或通道184可形成在半導體晶粒124邊緣周圍的封裝材料146中。在移除暫時保護平面化層136以前，淺孔穴182-184可藉由將在圖4d中的封裝材料146雷射鑽孔5-50μm的深度而來形成。淺孔穴182-184提供傾倒支撐於DT以及TCoB測試中。絕緣層156具有足夠厚度，以在沒有將基板表面完全平面化時，形成碟狀於淺孔穴182上。傳導層160具有更厚的圓頂形部份186於淺孔穴182與184下。
雖然本發明的一或更多實施例已經被詳細說明，但是熟諳技藝者將理解，那些實施例的變更與適應度可在不背離以下申請專利範圍所陳述的本發明範圍之下進行。
在圖式中主要元件的參考數目列表
50．．．電子裝置
52．．．印刷電路板
54．．．訊號軌跡
56．．．接合佈線封裝
58．．．覆晶
60．．．球柵陣列(BGA)
62．．．凸塊晶片載體(BCC)
64．．．雙排型封裝
66．．．地格柵陣列(LGA)
68．．．多晶片模組(MCM)
70．．．四方形扁平無引線封裝(QFN)
72．．．四方形扁平封裝
74．．．半導體晶粒
76．．．接觸襯墊
78．．．中間載體
80．．．導體引線
82．．．接合佈線
84．．．封裝材料
88．．．半導體晶粒
90．．．載體
92．．．下填或環氧樹脂黏著材料
94．．．接合佈線
96,98．．．接觸襯墊
100．．．鑄模化合物或封裝材料
102．．．接觸襯墊
106．．．中間載體
108．．．主動區域
110．．．凸塊
112．．．凸塊
114．．．訊號線
116．．．載體
120．．．晶圓
122．．．基底基板材料
124．．．半導體晶粒或元件
126．．．切割道
128．．．背表面
130．．．主動表面
132．．．導電層
134．．．絕緣或被動層
134a．．．第一部份
134b．．．第二部份
135．．．平面表面
136．．．覆蓋暫時保護平面化層
137．．．鋸片刀片或雷射切割工具
138．．．溝渠或溝槽
139．．．傳導層
140．．．開口
141．．．凹口
142．．．基板或載體
144．．．界面層或雙邊帶
146．．．封裝或模鑄化合物
150．．．膠帶
152．．．表面
154．．．研磨器
156．．．絕緣或被動層
158．．．表面
160．．．導電層或重分配層(RDL)
162．．．絕緣或被動層
164．．．圓球或凸塊
170．．．淺孔穴或通道
172．．．淺圓腔或通道
174．．．邊緣
178-184．．．淺孔穴或通道
186．．．較厚圓頂形部份
圖1顯示具有不同種封裝物被安裝到其表面的PCB；
圖2a－2c顯示被安裝到PCB之半導體封裝物的進一步細節；
圖3a－3i顯示將一保護層形成在不均勻絕緣層上以將半導體晶粒平面化並且在單一化期間內保護晶粒邊緣的製程；
圖4a－4j顯示一種形成具有半導體晶粒之晶圓級晶片尺寸封裝的製程，其係具有犧牲保護層，以將不均勻表面平面化；
圖5顯示一種晶圓級晶片尺寸封裝，其係具有淺孔穴被形成在RDL與凸塊上的封裝材料中；
圖6顯示一種晶圓級晶片尺寸封裝，其係具有一淺圓腔被形成在半導體晶粒周圍之RDL與凸塊與封裝材料切邊上的封裝材料中；
圖7顯示一種晶圓級晶片尺寸封裝，其係具有淺孔穴被形成在RDL與凸塊上以及半導體晶粒周圍的封裝材料中；以及
圖8顯示一種晶圓級晶片尺寸封裝，其係具有淺孔穴被形成在該封裝材料中，以及厚RDL在該孔穴之下。
124．．．半導體晶粒或元件
128．．．背表面
130．．．主動表面
132．．．導電層
134a．．．第一部份
134b．．．第二部份
146．．．封裝或模鑄化合物
152．．．表面
156．．．絕緣或被動層
158．．．表面
160．．．導電層或重分配層(RDL)
162．．．絕緣或被動層
164．．．圓球或凸塊
170．．．淺孔穴或通道

Claims (15)

  1. 一種製造半導體裝置的方法，包含：提供包含複數個半導體晶粒的一半導體晶圓；將一第一絕緣層形成在該半導體晶圓上；將一保護層形成在第一絕緣層上；將該半導體晶圓單一化穿過該保護層以隔開該半導體晶粒，同時保護該半導體晶粒的一邊緣；將該半導體晶粒安裝到一載體；將一封裝材料沈積在該半導體晶粒與載體上；移除該載體與保護層；以及將一集結互連結構形成在該半導體晶粒與封裝材料上。
  2. 如申請專利範圍第1項之方法，其中第一絕緣層具有非平面表面，且該保護層具有一平面表面。
  3. 如申請專利範圍第1項之方法，進一步包括將與第一絕緣層相對的一部份封裝材料移除。
  4. 如申請專利範圍第1項之方法，進一步包括形成該保護層於該半導體晶圓的整個表面上。
  5. 如申請專利範圍第1項之方法，進一步包括在移除該保護層以前，形成一孔穴於該封裝材料中。
  6. 一種製造半導體裝置的方法，包含：提供一半導體晶粒；形成一第一絕緣層於該半導體晶粒上；形成一保護層於第一絕緣層上； 以該保護層來引導，將該半導體晶粒安裝到一載體；將一封裝材料沈積在該半導體晶粒與載體上；移除該載體與保護層；以及將一集結互連結構形成在該半導體晶粒與封裝材料上。
  7. 如申請專利範圍第6項之方法，其中第一絕緣層具有非平面表面。
  8. 如申請專利範圍第6項之方法，其中該保護層保護該半導體晶粒的一邊緣。
  9. 如申請專利範圍第6項之方法，進一步包括：將一膠帶施加到該封裝材料與保護層上；將與第一絕緣層相對的一部份封裝材料移除；以及將具有該膠帶的該保護層移除。
  10. 如申請專利範圍第6項之方法，進一步包括將一孔穴形成在該半導體晶粒周圍的封裝材料中。
  11. 一種半導體裝置，包含：一半導體晶粒；一第一絕緣層，形成於該半導體晶粒上；一暫時保護層，形成於第一絕緣層上並且經建構以從該第一絕緣層上方而被移除；以及一封裝材料，沈積在該半導體晶粒上以形成具有該暫時保護層的一平坦表面。
  12. 如申請專利範圍第11項之半導體裝置，其中該暫時保護層保護該半導體晶粒的邊緣。
  13. 如申請專利範圍第11項之半導體裝置，進一步包括形成在封裝材料中的一孔穴。
  14. 如申請專利範圍第11項之半導體裝置，進一步包括一互連結構被形成於該半導體晶粒和該封裝材料之上。
  15. 如申請專利範圍第11項之半導體裝置，其中該封裝材料被平面化以相應於該半導體晶粒的一表面。
TW100107876A 2010-03-12 2011-03-09 半導體裝置及形成犧牲保護層以於單一化過程中保護半導體晶粒邊緣之方法 TWI528437B (zh)

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US8183095B2 (en) 2012-05-22
US8907476B2 (en) 2014-12-09
US9558958B2 (en) 2017-01-31
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US10204866B2 (en) 2019-02-12
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US20120199965A1 (en) 2012-08-09
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US20170098612A1 (en) 2017-04-06
US20110221057A1 (en) 2011-09-15

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