CN102683279A - 半导体器件和形成牺牲保护层以在单体化期间保护半导体管芯边缘的方法 - Google Patents

半导体器件和形成牺牲保护层以在单体化期间保护半导体管芯边缘的方法 Download PDF

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CN102683279A
CN102683279A CN2011100584659A CN201110058465A CN102683279A CN 102683279 A CN102683279 A CN 102683279A CN 2011100584659 A CN2011100584659 A CN 2011100584659A CN 201110058465 A CN201110058465 A CN 201110058465A CN 102683279 A CN102683279 A CN 102683279A
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protective layer
semiconductor element
semiconductor
insulating barrier
sealant
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CN102683279B (zh
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林耀剑
陈康
方建敏
冯霞
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Stats Chippac Pte Ltd
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Abstract

半导体器件和形成牺牲保护层以在单体化期间保护半导体管芯边缘的方法。半导体晶片包含被划片街区分开的多个半导体管芯。绝缘层形成在半导体晶片上。保护层形成在包括沿划片街区的半导体管芯的边缘的绝缘层上。保护层覆盖半导体晶片的整个表面。可替换地，在划片街区上的保护层中形成开口。绝缘层具有非平面表面且保护层具有平面表面。通过保护层和划片街区将半导体晶片单体化以分离半导体管芯同时保护半导体管芯的边缘。以保护层为首，将半导体管芯安装到载体。密封剂沉积在半导体管芯和晶片上。载体和保护层被除去。装配互连结构形成在半导体管芯和密封剂上。

Description

半导体器件和形成牺牲保护层以在单体化期间保护半导体管芯边缘的方法
要求国内优先权
本非临时申请要求2010年3月12日提交的序号为No. 61/313,208的美国临时申请的优先权的权益，并且根据35 U.S.C. § 120要求在先原申请的优先权。
技术领域
本发明总体上涉及半导体器件，更具体地，涉及半导体器件和形成临时平面化保护层以在单体化期间保护半导体管芯边缘的方法。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池、以及数字微镜器件（DMD）。
半导体器件执行多种功能，例如信号处理、高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流（base current）或者通过掺杂工艺来操纵（manipulated）它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。
半导体器件包括有源和无源电结构。有源结构（包括双极和场效应晶体管）控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构（包括电阻器、电容器、和电感器）产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速计算和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化（singulating）单个管芯并且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目标是制造更小的半导体器件。更小的半导体器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外，更小的半导体器件具有更小的占用空间（footprint），其对于更小的最终产品而言是期望的。通过改善导致产生具有更小、更高密度的有源和无源部件的管芯的前端工艺可以实现更小的管芯尺寸。通过改善电互连和封装材料，后端工艺可以产生具有更小占用空间的半导体器件封装。
半导体晶片包含多个被划片街区分开的半导体管芯或部件。利用锯条或激光切割工具通过划片街区将半导体晶片单体化成单个半导体管芯。一旦被单体化，半导体管芯可以被安装到临时载体以便形成用于扇出型晶片级芯片规模封装（FO-WLCSP）的装配互连结构（build-up interconnect structure）。在单体化过程期间，半导体管芯沿着管芯边缘遭受破片和裂开或遭受其它损伤，更具体地说是通过旋压锯条的冲击而遭受的。在单体化期间沿着划片街区可能出现金属毛刺（metal burring），其在形成装配互连结构时可能引起电短路。在半导体管芯具有不平坦的或高表面形貌（topography）的情况下，管芯和载体之间的粘附性可以变得微弱，在互连装配过程期间导致产生缺陷。
发明内容
存在在单体化期间保护半导体管芯并且在装配互连过程期间在管芯和载体之间提供平面表面的需要。因此，在一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供包含被划片街区分开的多个半导体管芯的半导体晶片，在半导体晶片上形成第一绝缘层，沿划片街区在包括半导体管芯的边缘的第一绝缘层上形成保护层，通过保护层和划片街区单体化半导体晶片以分离半导体管芯同时保护半导体管芯的边缘，以保护层为首，将半导体管芯安装到载体，在半导体管芯和载体上沉积密封剂，除去载体和保护层，以及在半导体管芯和密封剂上形成装配互连结构。
在另一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供包含多个半导体管芯的半导体晶片，在半导体晶片上形成第一绝缘层，在第一绝缘层上形成保护层，通过保护层单体化半导体晶片以分离半导体管芯同时保护半导体管芯的边缘，将半导体管芯安装到载体，在半导体管芯和载体上沉积密封剂，除去载体和保护层，以及在半导体管芯和密封剂上形成装配互连结构。
在另一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供半导体管芯，在半导体管芯上形成第一绝缘层，在第一绝缘层上形成保护层，以保护层为为首，将半导体管芯安装到载体，在半导体管芯和载体上沉积密封剂，除去载体和保护层，以及在半导体管芯和密封剂上形成装配互连结构。
在另一个实施例中，本发明是一种半导体器件，该半导体器件包括：半导体管芯和形成在半导体管芯上的第一绝缘层。保护层形成在第一绝缘层上。密封剂沉积在半导体管芯上。装配互连结构形成在半导体管芯和密封剂上。
附图说明
图1示出具有安装到其表面的不同类型封装的PCB；
图2a-2c示出安装到所述PCB的半导体封装的更多细节；
图3a-3i示出在不平坦的绝缘层上形成保护层以平面化半导体管芯并在单体化期间保护管芯边缘的过程；
图4a-4j示出利用包括具有牺牲保护层以平面化不平坦表面的半导体管芯的WLCSP的过程；
图5示出具有形成在RDL和凸块上的密封剂中的浅空腔的WLCSP；
图6示出具有形成在RDL和凸块上的密封剂中的浅圆形空腔和在半导体管芯周围的密封剂修整（trim）的WLCSP；
图7示出具有形成在RDL和凸块上和半导体管芯周围的密封剂中的浅空腔的WLCSP；
图8示出具有形成在密封剂中的浅空腔和在空腔下面的厚RDL的WLCSP。
具体实施方式
参考附图在下列描述中的一个或多个实施例中描述本发明，在附图中相似的数字表示相同或类似的元件。虽然根据用来实现本发明的目的的最佳方式描述本发明，但是本领域技术人员将理解的是，它旨在覆盖可以被包含在由被下列公开和各图所支持的所附权利要求及其等效物限定的本发明的精神和范围内的替代物、变型、和等效物。
一般利用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流的流动的能力。无源电部件，例如电容器、电感器、电阻器、和变压器，产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。所述掺杂工艺改变有源器件中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。
通过具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀、以及无电极电镀（electroless plating）工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。
可以利用光刻图案化所述层，所述光刻包括在将被图案化的层上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。在一个实施例中，利用溶剂将经受光的光致抗蚀剂图案部分除去，暴露将被图案化的下层的各部分。在另一个实施例中，利用溶剂将未经受光的光致抗蚀剂图案部分（负性光致抗蚀剂）除去，暴露将被图案化的下层的各部分。光致抗蚀剂的剩余物被除去，留下被图案化的层。可替换地，利用例如无电极电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。
在现有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间，磨料和腐蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品腐蚀作用除去了任何不规则的表面形貌（topography），产生均匀的平面。
后端制造指的是将已完成的晶片切割或单体化成单个管芯，并且然后封装管芯用于结构支撑和环境隔离。为单体化管芯，沿被叫做划片街区（saw street）或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后，单个管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块（stud bump）、导电胶、或线结合（wirebond）来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中并且半导体器件的功能可以用到其它系统部件。
图1示出具有芯片载体衬底或印刷电路板（PCB）52的电子器件50，所述芯片载体衬底或印刷电路板（PCB）52具有多个安装在它的表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图1中示出不同类型的半导体封装。
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件50可以是更大系统的子部件。例如，电子器件50可以是蜂窝电话、个人数字助理（PDA）、数码摄像机（DVC）或其它电子通信设备的一部分。可替换地，电子器件50可以是能被插入计算机中的图形卡、网络接口卡、或其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。对于这些将被市场接受的产品来说，小型化和重量减小是必要的。半导体器件之间的距离必须减小以获得更高的密度。
在图1中，PCB 52提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电极电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线（trace）54形成在PCB 52的表面上或各层内。信号迹线54提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线54也将电源和地连接提供给半导体封装中的每一个。
在一些实施例中，半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被以机械和电的方式直接安装到PCB。
为了说明的目的，几种第一级封装，包括结合线封装56和倒装芯片58，被示出在PCB 52上。另外，几种第二级封装，包括球栅阵列（BGA）60、凸块芯片载体（BCC）62、双列直插式封装（DIP）64、岸面栅格阵列（land grid array，LGA）66、多芯片模块（MCM）68、四侧无引脚扁平封装（quad flat non-leaded package，QFN）70、以及四侧扁平封装72被示出安装在PCB 52上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，虽然其它实施例要求多互连封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为所述半导体封装包括复杂功能，所以可以利用更便宜的部件和流水线制造工艺来制造电子器件。所得到的器件较少可能失效并且制造起来花费较少，对用户而言导致更低的成本。
图2a-2c示出示范性半导体封装。图2a示出安装在PCB 52上的DIP 64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为根据管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是导电材料（例如铝（AL）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、或银（Ag））的一个或多个层，并且电连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间，利用金硅共晶层或粘附材料（例如热的环氧或环氧树脂）将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和结合线82在半导体管芯74和PCB 52之间提供电互连。密封剂84被沉积在封装上用于通过防止湿气与粒子进入所述封装以及污染管芯74或结合线82来进行环境保护。
图2b示出安装在PCB 52上的BCC 62的更多细节。半导体管芯88利用底层填充材料或环氧树脂粘附材料92被安装到载体90上。结合线94在接触焊盘96和98之间提供第一级封装互连。模塑料或密封剂100被沉积在半导体管芯88和结合线94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用电解电镀或无电极电镀这样合适的金属沉积工艺形成在PCB 52的表面上以防止氧化。接触焊盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104被形成在BCC 62的接触焊盘98与PCB 52的接触焊盘102之间。
在图2c中，利用倒装芯片型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110被以机械和电的方式连接到载体106。
BGA 60 利用凸块112以机械和电的方式连接到具有BGA型第二级封装的PCB 52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯58可以在没有中间载体106的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB 52。
相对于图1和2a-2c，图3a-3i示出在不平坦的绝缘层上形成临时保护层以平面化半导体管芯并在单体化期间保护管芯边缘的过程。图3a示出具有基底衬底材料122的半导体晶片120，所述基底衬底材料例如是硅、锗、砷化镓、磷化铟或碳化硅，用于结构支撑。多个半导体管芯或部件124形成在晶片120上，如上所述那样被划片街区126分开。
图3b示出半导体晶片120的一部分的截面图。每个半导体管芯124具有后表面128和有源表面130，该有源表面130包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面130内的其它电路元件以实现模拟电路或数字电路，例如数字信号处理器（DSP）、ASIC、存储器、或其它信号处理电路。半导体管芯124也可以包括集成无源器件（IPD），例如电感器、电容器、和电阻器，用于RF信号处理。在一个实施例中，半导体管芯124可以是倒装芯片类型的半导体管芯。
利用PVD、CVD、电解电镀、无电极电镀工艺或其它适当的金属沉积工艺将导电层132形成在有源表面130上。导电层132可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。在一个实施例中，导电层132在有源表面130上延伸了0.6微米（μm）或更多。导电层132用作电连接到有源表面130上的电路的接触焊盘。
在图3c中，利用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化在有源表面130和导电层132上共形地施加绝缘或钝化层134。绝缘层134包含一层或多层的二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、聚酰亚胺、聚苯并恶唑（polybenzoxazole，PBO）、聚合物介电材料或具有类似绝缘和结构特性的其它材料。在一个实施例中，绝缘层134具有大于0.6 μm的厚度。绝缘层134被标注为具有在有源表面130上的第一部分134a和在导电层132上的第二部分134b。由于绝缘层134共形地施加在导电层132上，第二部分134b相对于有源表面130具有高表面形貌。因此，绝缘层134通常具有不平坦的表面形貌或非平面表面。绝缘层134b的一部分被除去以暴露导电层132，如图3d所示。绝缘层134b的一部分保留在导电层132上，引起绝缘层134的不平坦的表面形貌或非平面表面。
在图3e中，在晶片形式时使用丝网印刷、旋涂、喷涂和层压将毯式（blanket）临时保护平面化层136形成在绝缘层134和导电层132上。在沉积临时保护平面化层136之后，可以应用附加处理，例如UV曝光和加热工艺，以提供必要的粘附和机械特性。临时保护平面化层136包含一层或多层的光致抗蚀剂、液体涂覆材料、干膜、聚合物膜、聚合物复合材料、或具有顺应性、结构支撑、平面化能力、在110–160oC下达5到120分钟的热稳定性并且在密封过程之后容易脱模的特性的其它材料。保护平面化层136是用于平面化绝缘层134的不平坦的表面形貌的临时或牺牲层。临时保护平面化层136填充在绝缘层134的不平坦部分周围，以形成平面表面135。在一个实施例中，临时保护平面化层136厚度是5到25μm。
在一个实施例中，临时保护平面化层136覆盖半导体晶片或衬底120的整个表面（包括半导体管芯124和划片街区126）而没有图案化，如图3f所示。在图3g中，使用锯条或激光切割工具137通过绝缘层134、临时保护平面化层136和划片街区126将半导体晶片120单体化成单个半导体管芯124。
可替换地，临时保护平面化层136被图案化以具有形成在划片街区136上的沟槽或凹槽138，如图3h所示。沟槽138的宽度(WT)小于划片街区126的宽度(WS)，例如WT被制作成10μm，小于WS，且临时保护平面化层136在每一侧与划片街区126交叠至少5μm。锯条或激光切割工具137的宽度被示为尺寸WC。如果导电层139形成在划片街区126上，则WT被制作成10 μm，小于导电层139的最宽部分的宽度，且临时保护平面化层136在每一侧与导电层139交叠至少5 μm。
激光可用于通过利用2－7个轮回除去金属、绝缘材料和基底半导体材料而在划片街区126中形成沟槽或凹槽138。激光减少了绝缘材料的破裂，尤其是对于低介电常数（k）材料，所述破裂可能出现在利用锯条或切割工具137的机器切片期间。临时保护平面化层136在激光激发之前被沉积在划片街区126上。保护平面化层136提供对电介质厚度的方便控制以在可靠性测试过程中另外保护半导体管芯124。此外，临时保护平面化层136有助于防止在图4c的后期密封过程中的管芯移动和浮动管芯（flying die）问题。厚的临时保护平面化层136还有助于防止晶片表面在机器切片过程中遭受切片灰尘磨毁和损坏。
图3i示出具有凹口141的开口140的替换图案。在任何情况下，临时保护平面化层136都在单体化期间保护半导体管芯124的切口边缘免于破片和破裂，并且抑制沿划片街区126或管芯边缘的金属毛刺和分层。
相对于图1和2a-2c，图4a-4j示出形成包括具有牺牲保护层以平面化不平坦的表面的半导体管芯的WLCSP的过程。图4a示出包含临时或牺牲基底材料的衬底或载体142的一部分，所述基底材料例如是钢、铁合金、硅、聚合物、氧化铍、或其它适当的低成本、刚性材料，用于结构支撑。界面层或双面胶带144形成在载体142上，作为临时粘性结合膜或腐蚀停层。在一个实施例中，界面层144是可释放热或光的。
使用拾取和放置操作将图3a-3i的半导体管芯124安置在载体142上并安装到载体142。图4b示出安装到载体142的半导体管芯124，其中临时保护平面化层136的平面表面135取向朝向界面层144和载体142。临时保护平面化层136的平面表面135通过增加有效接触表面积并最小化形成在界面层144与半导体管芯124的表面之间的孔隙而增强了半导体管芯124与界面层144的粘附或结合强度。对于晶片级多管芯附着，载体142延伸到尺寸以外，图4b所示。多个半导体管芯124可以安装到载体142上。
在图4c中，在存在临时保护平面化层136的情况下，利用浆料印刷（paste printing）、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器（applicator）将密封剂或模塑料146沉积在半导体管芯124和界面层144上。密封剂146可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂146不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在图4d中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、激光扫描、或湿法脱模来除去载体142和界面层144以暴露临时保护平面化层136和密封剂146。
通过剥离除去临时保护平面化层136，如图4e所示。可替换地，可以利用去离子（DI）水喷射和漂洗或者通过溶剂或化学脱模来除去临时保护平面化层136。临时保护平面化层136为半导体管芯124提供多种有利特征，包括降低了晶片切片期间的管芯边缘破片和破裂，减少了密封期间的浮动管芯，降低了晶片切片期间的导电毛刺形成，容易控制电介质厚度，以及降低了晶片切片期间的有源表面130上的灰尘损伤。
在另一个实施例中，继续图4d，背面研磨胶带150被施加到密封剂146和临时保护平面化层136，如图4f所示。通过研磨器154除去密封剂146的表面152的一部分以平面化密封剂并暴露半导体管芯124的后表面128。然后在研磨操作之后利用背面研磨胶带150除去临时保护平面化层136，使绝缘层134和导电层132的后表面128暴露，如图4g所示。
在图4h中，利用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化在密封剂152的与表面128和152相对的表面158上形成绝缘或钝化层156。绝缘层156包含一层或多层的聚酰亚胺、苯并环丁烯（benzocyclobutene，BCB）、PBO、低温（<280oC）固化聚合物电介质、或其它具有类似绝缘和结构特性的材料。除去绝缘层156的一部分以暴露导电层132。
在图4i中，使用图案化和金属沉积工艺，例如PVD、CVD、溅射、电解电镀和无电极电镀，在绝缘层156和导电层132上形成导电层或再分布层（RDL）160。导电层160可以是一层或多层的Al、Cu、Ti/Cu、TiW/Cu、Sn、Ni、Au、 Ag、或其它适当的导电材料。导电层160电连接到导电层132。
利用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化在绝缘层156和导电层160上形成绝缘或钝化层162。绝缘层162包含一层或多层的聚酰亚胺、BCB、PBO、低温（<280oC）固化聚合物电介质、或其它具有类似绝缘和结构特性的材料。除去绝缘层162的一部分以暴露导电层160。按照设计要求可以建立另外的RDL层，包括导电层和绝缘层。
在图4j中，使用蒸发、电解电镀、无电极电镀、球滴（ball drop）或丝网印刷工艺在暴露的导电层160上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，或其组合，以及可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层160。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球形球或凸块164。在一些应用中，凸块164二次回流以改善到导电层160的电接触。所述凸块也可以被压缩结合到导电层160。凸块164表示一种可以形成在导电层160上的互连结构。所述互连结构也可以使用柱形凸块、微凸块、或其它电互连。
图5示出类似于图4j的另一实施例，其中在导电层160和凸块164下面的密封剂146中形成浅空腔或沟道170。浅空腔170可以通过在除去临时保护平面化层136之前对图4d中的密封剂146进行激光钻孔至5-50 μm的深度来形成。浅空腔170提供下坠测试（DT）和板上温度循环（TCoB）测试中的倾倒支持。浅空腔170还增强了利用绝缘层156的再钝化。
图6示出了类似于图4j的另一实施例，其中浅圆形空腔或沟道172形成在导电层160和164下面的半导体管芯124周围的密封剂146中。浅圆形空腔172可以通过在除去临时保护平面化层136之前对图4d中的密封剂进行激光钻孔至5-50 μm的深度来形成。浅圆形空腔172提供DT和TCoB测试中的倾倒支持。此外，在除去临时保护平面化层136之前，激光可以修整图4d中的半导体管芯142周围的密封剂146的边缘174。
图7示出了类似于图4j的另一实施例，其中浅空腔或沟道178形成在导电层160和164下面的半导体管芯124周围的密封剂146中。此外，浅空腔或沟道180形成在半导体管芯124的边缘周围的密封剂146中。浅空腔178-180可以通过在除去临时保护平面化层136之前对图4d中的密封剂146进行激光钻孔至5-50 μm的深度来形成。浅空腔178-180提供DT和TCoB测试中的倾倒支持。
图8示出了类似于图4j的另一实施例，其中浅空腔或沟道182形成在导电层160和164下面的半导体管芯124周围的密封剂146中。此外，浅空腔或沟道184形成在半导体管芯124的边缘周围的密封剂146中。浅空腔182-184可以通过在除去临时保护平面化层136之前对图4d中的密封剂146进行激光钻孔至5-50 μm的深度来形成。浅空腔182-184提供DT和TCoB测试中的倾倒支持。绝缘层156具有足够的厚度来在浅空腔182上形成凹坑（dishing）而不会完全平面化衬底表面。导电层160在浅空腔182和184下面具有较厚的圆顶状部分186。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变型和修改。

Claims (25)

1. 一种制造半导体器件的方法，包括：
提供包含被划片街区分开的多个半导体管芯的半导体晶片;
在半导体晶片上形成第一绝缘层;
沿划片街区在包括半导体管芯的边缘的第一绝缘层上形成保护层;
通过保护层和划片街区单体化半导体晶片以分离半导体管芯同时保护半导体管芯的边缘;
以保护层为首，将半导体管芯安装到载体;
在半导体管芯和载体上沉积密封剂;
除去载体和保护层;以及
在半导体管芯和密封剂上形成装配互连结构。
2. 根据权利要求1的方法，其中第一绝缘层具有非平面表面且保护层具有平面表面。
3. 根据权利要求1的方法，还包括除去密封剂的与第一绝缘层相对的部分。
4. 根据权利要求1的方法，还包括在半导体晶片的整个表面上形成保护层。
5. 根据权利要求1的方法，还包括在划片街区上的保护层中形成开口。
6. 根据权利要求1的方法，其中形成装配互连结构包括：
在密封剂和第一绝缘层上形成第二绝缘层；
在第二绝缘层上形成导电层；以及
在第二绝缘层和导电层上形成第三绝缘层。
7. 一种制造半导体器件的方法，包括：
提供包含多个半导体管芯的半导体晶片；
在半导体晶片上形成第一绝缘层；
在第一绝缘层上形成保护层；
通过保护层单体化半导体晶片以分离半导体管芯同时保护半导体管芯的边缘；
将半导体管芯安装到载体；
在半导体管芯和载体上沉积密封剂；
除去载体和保护层；以及
在半导体管芯和密封剂上形成装配互连结构。
8. 根据权利要求7的方法，其中第一绝缘层具有非平面表面且保护层具有平面表面。
9. 根据权利要求7的方法，还包括除去密封剂的与第一绝缘层相对的部分。
10. 根据权利要求7的方法，还包括在半导体晶片的整个表面上形成保护层。
11. 根据权利要求7的方法，其中保护层在划片街区上具有开口。
12. 根据权利要求7的方法，还包括在半导体管芯周围的密封剂中形成空腔。
13. 根据权利要求7的方法，还包括在除去保护层之前在密封剂中形成空腔。
14. 一种制造半导体器件的方法，包括：
提供半导体管芯；
在半导体管芯上形成第一绝缘层；
在第一绝缘层上形成保护层；
以保护层为为首，将半导体管芯安装到载体；
在半导体管芯和载体上沉积密封剂；
除去载体和保护层；以及
在半导体管芯和密封剂上形成装配互连结构。
15. 根据权利要求14的方法，其中第一绝缘层具有非平面表面。
16. 根据权利要求14的方法，其中保护层具有平面表面。
17. 根据权利要求14的方法，其中保护层保护半导体管芯的边缘。
18. 根据权利要求14的方法，进一步包括：
在密封剂和保护层上施加胶带；
除去密封剂的与第一绝缘层相对的部分；以及
利用胶带除去保护层。
19. 根据权利要求14的方法，还包括利用去离子水和漂洗或化学脱模来除去保护层。
20. 根据权利要求14的方法，还包括在半导体管芯周围的密封剂中形成空腔。
21. 一种半导体器件，包括：
半导体管芯；
形成在半导体管芯上的第一绝缘层；
形成在第一绝缘层上的保护层；
沉积在半导体管芯上的密封剂；
形成在半导体管芯和密封剂上的装配互连结构。
22. 根据权利要求21的半导体器件，其中第一绝缘层具有非平面表面。
23. 根据权利要求21的半导体器件，其中保护层具有平面表面。
24. 根据权利要求21的半导体器件，其中保护层保护半导体管芯的边缘。
25. 根据权利要求21的半导体器件，还包括形成在密封剂中的空腔。
CN201110058465.9A 2010-03-12 2011-03-11 半导体器件和形成牺牲保护层以在单体化期间保护半导体管芯边缘的方法 Active CN102683279B (zh)

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