CN102420147A - 形成保护结构用于绝缘层局部平坦化的方法和半导体器件 - Google Patents

形成保护结构用于绝缘层局部平坦化的方法和半导体器件 Download PDF

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CN102420147A
CN102420147A CN2011102938075A CN201110293807A CN102420147A CN 102420147 A CN102420147 A CN 102420147A CN 2011102938075 A CN2011102938075 A CN 2011102938075A CN 201110293807 A CN201110293807 A CN 201110293807A CN 102420147 A CN102420147 A CN 102420147A
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protection pattern
semiconductor element
conductive layer
insulating barrier
semiconductor
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CN102420147B (zh
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林耀剑
冯霞
陈康
方建敏
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及形成保护结构用于绝缘层局部平坦化的方法和半导体器件。一种半导体晶片包含被划片街区分离的多个半导体管芯。在半导体管芯的有源表面上形成接触焊盘。在半导体管芯的划片街区与接触焊盘之间的半导体管芯的有源表面上形成保护图案。该保护图案包括分段金属层或多个平行的分段金属层。在有源表面、接触焊盘和保护图案上形成绝缘层。去除绝缘层的一部分以使接触焊盘暴露。保护图案减少半导体管芯的划片街区与接触焊盘之间的绝缘层的腐蚀。保护图案可以在半导体管芯的拐角处成角度或遵循接触焊盘的轮廓。可以在半导体管芯的拐角处形成保护图案。

Description

形成保护结构用于绝缘层局部平坦化的方法和半导体器件
技术领域
本发明一般地涉及半导体器件，并且更特别地涉及用于在半导体管芯周围形成保护结构用于绝缘层的局部平坦化的方法和半导体器件。
背景技术
常常在现代电子产品中发现半导体器件。半导体器件在电部件的数目和密度方面变化。分立的半导体器件一般包含一种类型的电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件典型地包含几百个到数以百万的电部件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池以及数字微镜器件（DMD）。
半导体器件执行各种的功能，诸如信号处理、高速计算、发射和接收电磁信号、控制电子器件、将太阳光转变为电力以及产生用于电视显示的视觉投影。在娱乐、通信、功率转换、网络、计算机以及消费产品的领域中发现半导体器件。还在军事应用、航空、汽车、工业控制器和办公设备中发现半导体器件。
半导体器件利用半导体材料的电属性。半导体材料的原子结构允许通过施加电场或基电流（base current）或通过掺杂工艺而操纵其导电性。掺杂向半导体材料引入杂质以操纵和控制半导体器件的导电性。
半导体器件包含有源和无源电结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变掺杂水平和施加电场或基电流，晶体管要么促进要么限制电流的流动。包括电阻器、电容器和电感器的无源结构创建为执行各种电功能所必须的电压和电流之间的关系。无源和有源结构电连接以形成电路，这使得半导体器件能够执行高速计算和其他有用功能。
半导体器件一般使用两个复杂的制造工艺来制造，即，前端制造和和后端制造，每一个可能涉及成百个步骤。前端制造涉及在半导体晶片的表面上形成多个管芯。每个管芯典型地是相同的且包含通过电连接有源和无源部件而形成的电路。后端制造涉及从完成的晶片分割（singulate）各个管芯且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目的是生产较小的半导体器件。较小的器件典型地消耗较少的功率、具有较高的性能且可以更高效地生产。另外，较小的半导体器件具有较小的占位面积，这对于较小的终端产品而言是希望的。较小的管芯尺寸可以通过前端工艺中的改进来获得，该前端工艺中的改进导致管芯具有较小、较高密度的有源和无源部件。后端工艺可以通过电互连和封装材料中的改进而导致具有较小占位面积的半导体器件封装。
图1示出具有被划片街区（saw street）14分离的多个半导体管芯12的常规半导体晶片10的一部分。在半导体管芯12的有源表面上形成接触焊盘16。在有源表面和接触焊盘16上形成钝化层18。去除钝化层18的一部分以使接触焊盘16暴露以用于电互连。然而，在显影工艺期间，钝化层18可能腐蚀并变得不期望地薄，特别是在半导体管芯12和半导体晶片10的边缘和拐角处。图2示出晶片10或半导体管芯12的拐角或边缘20处的钝化层18的腐蚀。薄钝化层18能够引起缺陷并减少半导体管芯12在其最后封装结构中的可靠性。
发明内容
存在对半导体管芯的有源表面上的减少的钝化层腐蚀的需要。因此，在一个实施例中，本发明是一种制造半导体器件的方法，包括步骤：提供具有被划片街区分离的多个半导体管芯的半导体晶片、在半导体管芯的有源表面上形成接触焊盘、在接触焊盘与半导体管芯的划片街区之间的半导体管芯的有源表面上形成保护图案、在有源表面、接触焊盘和保护图案上形成绝缘层、以及去除绝缘层的一部分以使接触焊盘暴露。保护图案减少接触焊盘与半导体管芯的划片街区之间的绝缘层的腐蚀。
在另一实施例中，本发明是一种制造半导体器件的方法，包括步骤：提供半导体晶片、在半导体晶片的表面上形成导电层、在导电层与半导体晶片的边缘之间的半导体晶片的表面上形成保护图案、在半导体晶片的表面、导电层和保护图案上形成绝缘层、以及去除绝缘层的一部分以使导电层的一部分暴露。保护图案将绝缘层保持在导电层与半导体晶片的边缘之间。
在另一实施例中，本发明是一种制造半导体器件的方法，包括步骤：提供半导体管芯、在半导体管芯的表面上形成导电层、在邻近于导电层的半导体管芯的表面上形成保护图案、以及在半导体管芯的表面、导电层和保护图案上形成绝缘层。保护图案保持绝缘层邻近于导电层。
在另一实施例中，本发明是一种包括半导体管芯和在半导体管芯的表面上形成的导电层的半导体器件。在邻近于导电层的半导体晶片的表面上形成保护图案。在半导体管芯的表面、导电层和保护图案上形成绝缘层。保护图案保持绝缘层邻近于导电层。
附图说明
图1举例说明具有在半导体管芯上形成的钝化层的常规半导体晶片；
图2举例说明具有钝化层的腐蚀的常规半导体晶片的边缘；
图3举例说明具有安装到其表面的不同类型的封装的PCB；
图4a-4c举例说明被安装到PCB的代表性半导体封装的更多细节；
图5a-5d举例说明用于在半导体管芯周围形成保护图案以进行绝缘层的局部平坦化的工艺；
图6举例说明具有被以WLCSP安装到衬底的保护图案的半导体管芯；
图7a-7b举例说明用于绝缘层的局部平坦化的遵循接触焊盘的轮廓的保护图案；
图8a-8b举例说明用于绝缘层的局部平坦化的平行段的保护图案；
图9举例说明用RDL以WLCSP在重新布线钝化层上形成的保护图案；以及
图10举例说明用RDL以Fo-WLCSP在重新布线钝化层上形成的保护图案。
具体实施方式
在下面的描述中，参考图以一个或更多实施例描述本发明，在这些图中相似的标号代表相同或类似的元件。尽管就用于实现本发明目的的最佳模式描述本发明，但是本领域技术人员应当理解，其旨在覆盖可以包括在如下面的公开和图支持的所附权利要求及其等价物限定的本发明的精神和范围内的备选、修改和等价物。
半导体器件一般使用两个复杂制造工艺来制造：前端制造和后端制造。前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含有源和无源电部件，它们电连接以形成功能电路。诸如晶体管和二极管的有源电部件具有控制电流流动的能力。诸如电容器、电感器、电阻器和变压器的无源电部件创建为执行电路功能所必须的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、蚀刻和平坦化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过诸如离子注入或热扩散的技术将杂质引入到半导体材料中。掺杂工艺修改了有源器件中半导体材料的导电性，将半导体材料转变为绝缘体、导体，或者响应于电场或基电流而动态地改变半导体材料的导电性。晶体管包含不同类型和掺杂程度的区域，其按照需要被布置为使得当施加电场或基电流时晶体管能够促进或限制电流的流动。
通过具有不同电属性的材料层形成有源和无源部件。层可以通过部分由被沉积的材料类型确定的各种沉积技术来形成。例如，薄膜沉积可能涉及化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀和化学电镀工艺。每一层一般被图案化以形成有源部件、无源部件或部件之间的电连接的部分。
可以使用光刻对层进行图案化，光刻涉及例如光刻胶的光敏材料在待被图案化的层上的沉积。使用光，图案从光掩模转印到光刻胶。受光影响的光刻胶图案的部分使用溶剂来去除，露出待被图案化的底层的部分。光刻胶的剩余部分被去除，留下图案化层。备选地，一些类型的材料通过使用诸如化学电镀和电解电镀这样的技术来直接向原先沉积/蚀刻工艺形成的区域或空位沉积材料而被图案化。
在现有图案上沉积材料的薄膜可以放大底层图案且形成不均匀的平坦表面。需要均匀的平坦表面来生产更小且更致密堆叠的有源和无源部件。平坦化可以用于从晶片的表面去除材料且产生均匀的平坦表面。平坦化涉及使用抛光垫对晶片的表面进行抛光。研磨材料和腐蚀化学物在抛光期间被添加到晶片的表面。组合的研磨物的机械行为和化学物的腐蚀行为去除任何不规则外貌，导致均匀的平坦表面。
后端制造指将完成的晶片切割或分割为各个管芯且然后封装管芯以用于结构支撑和环境隔离。为了分割管芯，晶片沿着称为划片街区或划线的晶片的非功能区域被划片且折断。使用激光切割工具或锯条来分割晶片。在分割之后，各个管芯被安装到封装基板，该封装基板包括引脚或接触焊盘以用于与其他系统部件互连。在半导体管芯上形成的接触焊盘然后连接到封装内的接触焊盘。电连接可以使用焊料凸块、柱形凸块、导电胶或引线接合来制成。密封剂或其他成型材料沉积在封装上以提供物理支撑和电隔离。完成的封装然后被插入到电系统中且使得半导体器件的功能性对于其他系统部件可用。
图3举例说明具有芯片载体基板或印刷电路板（PCB）52的电子器件50，该芯片载体基板或印刷电路板（PCB）52具有安装在其表面上的多个半导体封装。取决于应用，电子器件50可以具有一种类型的半导体封装或多种类型的半导体封装。用于说明性目的，在图3中示出了不同类型的半导体封装。
电子器件50可以是使用半导体封装以执行一个或更多电功能的独立系统。备选地，电子器件50可以是较大系统的子部件。例如，电子器件50可以是蜂窝电话、个人数字助理（PDA）、数码摄像机（DVC）或其他电子通信器件的一部分。备选地，电子器件50可以是图形卡、网络接口卡或可以被插入到计算机中的其他信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件或其他半导体管芯或电部件。微型化和重量减小对于这些产品被市场接受是至关重要的。半导体器件之间的距离必须减小以实现更高的密度。
在图3中，PCB 52提供用于安装到PCB上的半导体封装的结构支撑和电互连的一般性基板。使用蒸发、电解电镀、化学电镀、丝网印刷或者其他合适的金属沉积工艺，导电信号迹线54在PCB 52的表面上或其层内形成。信号迹线54提供半导体封装、安装的部件以及其他外部系统部件中的每一个之间的电通信。迹线54还向半导体封装中的每一个提供功率和接地连接。
在一些实施例中，半导体器件具有两个封装级别。第一级封装是用于机械和电附连半导体管芯到中间载体的技术。第二级封装涉及机械和电附连中间载体到PCB。在其他实施例中，半导体器件可以仅具有第一级封装，其中管芯被直接机械和电地安装到PCB。
用于说明目的，在PCB 52上示出包括引线接合封装56和倒装芯片58的若干类型的第一级封装。另外，示出在PCB 52上安装的若干类型的第二级封装，包括球栅阵列（BGA）60、凸块芯片载体（BCC）62、双列直插式封装（DIP）64、岸面栅格阵列（LGA）66、多芯片模块（MCM）68、四方扁平无引脚封装（QFN）70以及方形扁平封装72。取决于系统需求，使用第一和第二级封装类型的任何组合配置的半导体封装以及其他电子部件的任何组合可以连接到PCB 52。在一些实施例中，电子器件50包括单一附连的半导体封装，而其他实施例需要多个互连封装。通过在单个基板上组合一个或更多半导体封装，制造商可以将预制部件结合到电子器件和系统中。因为半导体封装包括复杂的功能性，可以使用较廉价的部件和流水线制造工艺来制造电子器件。所得到的器件较不倾向于发生故障且对于制造而言较不昂贵，导致针对消费者的较少的成本。
图4a-4c示出示例性半导体封装。图4a说明安装在PCB 52上的DIP 64的进一步细节。半导体管芯74包括有源区域，该有源区域包含实现为根据管芯的电设计而在管芯内形成且电互连的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管、电感器、电容器、电阻器以及在半导体管芯74的有源区域内形成的其他电路元件。接触焊盘76是诸如铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）或银（Ag）的一层或多层导电材料，且电连接到半导体管芯74内形成的电路元件。在DIP 64的组装期间，半导体管芯74使用金-硅共熔层或者诸如热环氧物或环氧树脂的粘合剂材料而安装到中间载体78。封装体包括诸如聚合物或陶瓷的绝缘封装材料。导线80和引线接合82提供半导体管芯74和PCB 52之间的电互连。密封剂84沉积在封装上，以通过防止湿气和颗粒进入封装且污染管芯74或引线接合82而进行环境保护。
图4b举例说明安装在PCB 52上的BCC 62的进一步细节。半导体管芯88使用底层填料或者环氧树脂粘合剂材料92而安装在载体90上。引线接合94提供接触焊盘96和98之间的第一级封装互连。模塑料或密封剂100沉积在半导体管芯88和引线接合94上，从而为器件提供物理支撑和电隔离。接触焊盘102使用诸如电解电镀或化学电镀之类的合适的金属沉积工艺而在PCB 52的表面上形成以防止氧化。接触焊盘102电连接到PCB 52中的一个或更多导电信号迹线54。凸块104在BCC 62的接触焊盘98和PCB 52的接触焊盘102之间形成。
在图4c中，使用倒装芯片类型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区域108包含实现为根据管芯的电设计而形成的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管、电感器、电容器、电阻器以及有源区域108内的其他电路元件。半导体管芯58通过凸块110电和机械连接到载体106。
使用利用凸块112的BGA类型第二级封装，BGA 60电且机械连接到PCB 52。半导体管芯58通过凸块110、信号线114和凸块112电连接到PCB 52中的导电迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电迹线的短导电路径以便减小信号传播距离、降低电容且改善整体电路性能。在另一实施例中，半导体管芯58可以使用倒装芯片类型第一级封装来直接机械和电地连接到PCB 52而不使用中间载体106。
图5a示出具有用于结构支撑的基底基板材料122的半导体晶片120，该基底基板材料诸如是硅、锗、砷化镓、磷化铟或者碳化硅。如上所述，在晶片120上形成通过划片街区126分离的多个半导体管芯或部件124。
图5b示出半导体晶片120的一部分的剖视图。每个半导体管芯124具有有源表面130，该有源表面包含实现为在管芯内形成的且根据管芯的电设计和功能而电互连的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多个晶体管、二极管以及在有源表面130内形成的其他电路元件以实现诸如数字信号处理（DSP）、ASIC、存储器或其他信号处理电路之类的模拟电路或数字电路。半导体管芯124还可以包含集成无源器件（IPD），诸如电感器、电容器和电阻器，以进行RF信号处理。在一个实施例中，半导体管芯124是倒装芯片类型的半导体管芯。
使用PVD、CVD、电解电镀、化学电镀工艺或其它适当的金属沉积工艺在有源表面130和重新分配电介质钝化层上形成导电层132。导电层132可以是一层或多层Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层132的一部分充当被电连接到有源表面130上的电路和下一个层级封装互连的接触焊盘134，例如在接触焊盘134上形成凸块。
图5c示出组成两个相邻半导体管芯124的半导体晶片120的一部分的平面图。可以在半导体管芯124的周界周围和在半导体管芯内部形成接触焊盘134。导电层132的另一部分提供在有源表面130上形成且被电连接到接触焊盘134的信号迹线136，用于到有源表面上的电路的信号路由。
使用图案化和PVD、CVD、电解电镀、化学电镀工艺或其它适当的金属沉积工艺在有源表面130上形成保护和平坦化金属图案138。更具体地，沿着每个半导体管芯124的边缘，即沿着划片街区126或部分地在划片街区126上形成保护层138，邻近于周界接触焊盘134邻近于周界接触焊盘134以使边缘或拐角焊盘134周围的钝化层140平坦化，并使焊盘上的应力分布平衡以便改善可靠性。保护层138可以是一层或多层Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。在与导电层132相同的工艺序列期间对保护图案138进行图案化和沉积。使保护图案138与接触焊盘134和迹线136及有源表面130上的电路电隔离。
在一个实施例中，保护图案138a是在半导体管芯124的周界周围、在周界接触焊盘134外面且邻近于周界接触焊盘134的大体上径直的、假金属迹线图案，在半导体管芯的拐角处具有角度。可以根据需要将保护图案138a的径直迹线图案中断或分段以避免与信号迹线136或有源表面130的其它电敏感区域的电接触。另外，保护图案138b被以多边形或圆形形状（例如，三角形形状）设置在半导体管芯124的拐角处以遵循保护图案138a的角。
使用PVD、CVD、印刷、旋涂、喷涂、层压或热氧化在有源表面130、导电层132和保护图案138上形成绝缘或钝化层140。绝缘层140可以是一层或多层二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、聚合物电介质，诸如聚酰亚胺、PBO、WPR、基于聚合物的低温固化聚合物、焊剂掩膜或具有类似绝缘和结构性质的其它适当材料。用蚀刻工艺来去除绝缘层140的一部分以使接触焊盘134暴露。
保护图案138提供半导体管芯124的边缘周围、例如在区域142中的绝缘层140的改善的局部平坦化。也就是说，保护图案138在显影期间减少腐蚀并保持绝缘层140的厚度，使得区域142中的绝缘层140具有与在半导体管芯124的内部部分中基本上相同的厚度。区域142中的绝缘层140由于保护图案138a和138b的支撑而在曝光之后的显影期间耐腐蚀。另外，保护图案138帮助半导体管芯124的取向识别以及局部应力释放。
在图5d中，使用锯条或激光切割工具139通过划片街区126将半导体晶片120分割成单独的半导体管芯124。可以将半导体管芯124安装到衬底或以任何封装结构来堆叠。例如，图6示出被以晶片级芯片级封装（WLCSP）147安装到具有凸块144且被密封剂145覆盖的衬底143的半导体管芯124。保护图案138保持绝缘层140的均匀厚度和覆盖直至且包括半导体管芯124的边缘。
图7a是从图5b继续的保护图案的另一实施例的平面图，具有在有源表面130上形成的作为接触焊盘134的导电层132和信号迹线136。使用图案化和PVD、CVD、电解电镀、化学电镀工艺或其它适当的金属沉积工艺在有源表面130上形成保护图案146。更具体地，沿着每个半导体管芯124的边缘，即沿着划片街区126或部分地在划片街区126上、以及沿着半导体晶片120的边缘，邻近于周界接触焊盘134形成保护图案146。保护图案146可以是一层或多层Al、Cu、Sn、Ni、Au、Ag或其它适当的材料。可以在与导电层132相同的工艺序列期间对保护图案146进行图案化和沉积。使保护图案146与接触焊盘134和迹线136及有源表面130上的电路电隔离。
在这种情况下，保护图案146a是在半导体管芯124的周界周围、在周界接触焊盘134外面且邻近于周界接触焊盘134的假金属迹线图案。保护图案146a遵循接触焊盘134的轮廓。例如，保护图案146a在圆形接触焊盘134周围成圆形。可以根据需要将保护图案146a的迹线图案中断或分段以避免与信号迹线136或有源表面130的其它电敏感区域的电接触。另外，保护图案146b被以任何规则或不规则形状设置在半导体管芯124的拐角处，例如，十字形、菱形或多边形形状。
使用PVD、CVD、印刷、旋涂、喷涂或热氧化在有源表面130、导电层132和保护图案146上形成绝缘或钝化层148。绝缘层140可以是一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构性质的其它适当材料。用蚀刻工艺来去除绝缘层148的一部分以使接触焊盘134暴露。
如图7b所示，保护图案146提供半导体管芯124的边缘周围、例如在区域150中的绝缘层140的改善的局部平坦化。也就是说，保护图案146在显影期间减少腐蚀并保持绝缘层148的厚度，使得区域150中的绝缘层148具有与在半导体管芯124的内部部分中基本上相同的厚度。区域150中的绝缘层148由于保护图案146a和146b的支撑而在曝光之后的显影期间耐腐蚀。另外，保护图案146帮助半导体管芯124的取向识别以及局部应力释放。
图8a是从图5b继续的保护图案的另一实施例的平面图，具有在有源表面130上形成的作为接触焊盘134的导电层132和信号迹线136。使用图案化和PVD、CVD、电解电镀、化学电镀工艺或其它适当的金属沉积工艺在有源表面130上形成保护图案152。更具体地，沿着每个半导体管芯124的边缘、即沿着划片街区126或部分地在划片街区126上、以及沿着半导体晶片120的边缘、邻近于周界接触焊盘134形成保护图案152。保护图案152可以是一层或多层Al、Cu、Sn、Ni、Au、Ag或其它适当的材料。可以在与导电层132相同的工艺序列期间对保护图案152进行图案化和沉积。使保护图案152与接触焊盘134和迹线136及有源表面130上的电路电隔离。
在这种情况下，保护图案152a是在半导体管芯124的周界周围、在周界接触焊盘134外面且邻近于周界接触焊盘134的多个径直的、平行假金属迹线图案，在半导体管芯的拐角处具有角度。可以根据需要将保护图案152a的径直的、平行迹线图案中断或分段以避免与信号迹线136或有源表面130的其它电敏感区域的电接触。另外，保护图案152b被以多边形或圆形形状（例如，三角形形状）设置在半导体管芯124的拐角处以遵循保护图案152a的角。
使用PVD、CVD、印刷、旋涂、喷涂或热氧化在有源表面130、导电层132和保护图案152上形成绝缘或钝化层154。绝缘层154可以是一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构性质的其它适当材料。用蚀刻工艺来去除绝缘层154的一部分以使接触焊盘134暴露。
如图8b所示，保护图案152提供半导体管芯124的边缘周围、例如在区域156中的绝缘层154的改善的局部平坦化。也就是说，保护图案152在显影期间减少腐蚀并保持绝缘层154的厚度，使得区域156中的绝缘层154具有与在半导体管芯124的内部部分中基本上相同的厚度。区域156中的绝缘层154由于保护图案152a和152b的支撑而在曝光之后的显影期间耐腐蚀。另外，保护图案152帮助半导体管芯124的取向识别以及局部应力释放。
图9示出具有使用PVD、CVD、印刷、旋涂、喷涂或热氧化在半导体管芯124的有源表面130和导电层132上形成的绝缘或钝化层160的另一实施例。绝缘层160可以是一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构性质的其它适当材料。用蚀刻工艺来去除绝缘层160的一部分以使接触焊盘134暴露。
使用PVD、CVD、印刷、旋涂、喷涂或热氧化在绝缘层160和暴露接触焊盘134上形成绝缘或钝化层162。绝缘层162可以是一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构性质的其它适当材料。用蚀刻工艺来去除绝缘层162的一部分以使接触焊盘134暴露。
在绝缘层162和接触焊盘134上形成导电层或RDL 164。使用图案化和PVD、CVD、电解电镀、化学电镀工艺或其它适当的金属沉积工艺在绝缘层162上形成保护图案166。保护图案166可以是一层或多层Al、Cu、Sn、Ni、Au、Ag或其它适当的材料。可以在与导电层164相同的工艺序列期间对保护图案166进行图案化和沉积。将保护图案166与导电层164电隔离。
使用PVD、CVD、印刷、旋涂、喷涂或热氧化在绝缘层162和导电层164以及保护图案166上形成绝缘或钝化层168。绝缘层168可以是一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构性质的其它适当材料。用蚀刻工艺来去除绝缘层168的一部分以使导电层164暴露。在暴露的导电层164上形成凸块170。绝缘层168可以具有指定开口以限定划片街区。
保护图案166提供绝缘层168的改善的局部平坦化。也就是说，保护图案166由于保护图案的支撑而在显影期间减少腐蚀并保持绝缘层168的厚度。
图10示出具有在作为扇出晶片级芯片级封装（Fo-WLCSP）的衬底的半导体管芯124上形成的密封剂172的另一实施例。使用PVD、CVD、印刷、旋涂、喷涂或热氧化在半导体管芯124的有源表面130和导电层132上形成绝缘或钝化层174。绝缘层174可以是一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构性质的其它适当材料。用蚀刻工艺来去除绝缘层174的一部分以使接触焊盘134暴露。
使用PVD、CVD、印刷、旋涂、喷涂或热氧化在绝缘层174和暴露的接触焊盘134上形成绝缘或钝化层176。绝缘层176可以是一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构性质的其它适当材料。用蚀刻工艺来去除绝缘层176的一部分以使接触焊盘134暴露。
在绝缘层176和接触焊盘134上形成导电层或RDL 178。使用图案化和PVD、CVD、电解电镀、化学电镀工艺或其它适当的金属沉积工艺在绝缘层176上形成保护图案180。保护图案180可以是一层或多层Al、Cu、Sn、Ni、Au、Ag或其它适当的材料。可以在与导电层178相同的工艺序列期间对保护图案180进行图案化和沉积。将保护图案180与导电层178电隔离。
使用PVD、CVD、印刷、旋涂、喷涂或热氧化在绝缘层176和导电层178以及保护图案180上形成绝缘或钝化层182。绝缘层182可以是一层或多层SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有类似绝缘和结构性质的其它适当材料。用蚀刻工艺来去除绝缘层182的一部分以使导电层178暴露。在暴露的导电层178上形成凸块184。
保护图案180提供绝缘层182的改善的局部平坦化。也就是说，保护图案180由于保护图案的支撑而在显影期间减少腐蚀并保持绝缘层182的厚度。
虽然已详细地举例说明了本发明的一个或多个实施例，但技术人员将认识到在不脱离以下权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变更和修改。

Claims (25)

1.一种制造半导体器件的方法，包括： 
提供具有被划片街区分离的多个半导体管芯的半导体晶片； 
在半导体管芯的有源表面上形成接触焊盘； 
在半导体管芯的划片街区与接触焊盘之间的半导体管芯的有源表面上形成保护图案； 
在有源表面、接触焊盘和保护图案上形成第一绝缘层；以及 
去除第一绝缘层的一部分以使接触焊盘暴露，其中，所述保护图案减少半导体管芯的划片街区与接触焊盘之间的第一绝缘层的腐蚀。
2.权利要求1的方法，其中，所述保护图案包括金属层。
3.权利要求1的方法，其中，所述保护图案被分段。
4.权利要求1的方法，还包括在具有到接触焊盘的开口的半导体管芯的有源表面上形成第二绝缘层。
5.权利要求1的方法，其中，所述保护图案遵循接触焊盘的轮廓。
6.权利要求1的方法，其中，所述保护图案包括多个平行段。
7.权利要求1的方法，还包括在半导体管芯的拐角处形成保护图案。
8.一种制造半导体器件的方法，包括： 
提供半导体晶片； 
在半导体晶片的表面上形成导电层； 
在半导体晶片的边缘与导电层之间的半导体晶片的表面上形成保护图案； 
在半导体晶片的表面、导电层和保护图案上形成绝缘层；以及 
去除绝缘层的一部分以使导电层的一部分暴露，其中，所述保护图案保持半导体晶片的边缘与导电层之间的绝缘层。
9.权利要求8的方法，其中，所述保护图案包括金属层。
10.权利要求8的方法，其中，所述保护图案被分段。
11.权利要求8的方法，其中，所述保护图案遵循导电层的暴露部分的轮廓。
12.权利要求8的方法，其中，所述保护图案包括多个平行段。
13.权利要求8的方法，还包括在半导体管芯的拐角处形成保护图案。
14.一种制造半导体器件的方法，包括： 
提供半导体管芯； 
在半导体管芯的表面上形成导电层； 
在邻近于导电层的半导体管芯的表面上形成保护图案；以及 
在半导体管芯的表面、导电层和保护图案上形成第一绝缘层，其中，所述保护图案保持邻近于导电层的第一绝缘层。
15.权利要求14的方法，还包括去除绝缘层的一部分以使导电层的一部分暴露，其中，保护图案减少邻近于导电层的第一绝缘层的腐蚀。
16.权利要求14的方法，其中，所述保护图案包括金属层。
17.权利要求14的方法，其中，所述保护图案被分段。
18.权利要求14的方法，还包括在半导体管芯上形成密封剂。
19.权利要求14的方法，还包括在具有到导电层的开口的半导体管芯的表面上形成第二绝缘层。
20.权利要求14的方法，还包括在半导体管芯的拐角处形成保护图案。
21.一种半导体器件，包括： 
半导体管芯； 
在半导体管芯的表面上形成的导电层； 
在邻近于导电层的半导体晶片的表面上形成的保护图案；以及 
在半导体管芯的表面、导电层和保护图案上形成的绝缘层，其中，所述保护图案保持邻近于导电层的绝缘层。
22.权利要求21的半导体器件，其中，所述保护图案包括金属层。
23.权利要求21的半导体器件，其中，所述保护图案被分段。
24.权利要求21的半导体器件，其中，所述保护图案遵循导电层的暴露部分的轮廓。
25.权利要求21的半导体器件，其中，所述保护图案包括多个平行段。
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