SG10201705932QA - Semiconductor device with protective structurearound semiconductor die for localized planarization of insulatinglayer - Google Patents

Semiconductor device with protective structurearound semiconductor die for localized planarization of insulatinglayer

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Publication number
SG10201705932QA
SG10201705932QA SG10201705932QA SG10201705932QA SG10201705932QA SG 10201705932Q A SG10201705932Q A SG 10201705932QA SG 10201705932Q A SG10201705932Q A SG 10201705932QA SG 10201705932Q A SG10201705932Q A SG 10201705932QA SG 10201705932Q A SG10201705932Q A SG 10201705932QA
Authority
SG
Singapore
Prior art keywords
structurearound
insulatinglayer
protective
semiconductor device
semiconductor
Prior art date
Application number
SG10201705932QA
Inventor
Yaojian Lin
Xia Feng
Kang Chen
Jianmin Fang
Original Assignee
Stats Chippac Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Pte Ltd filed Critical Stats Chippac Pte Ltd
Publication of SG10201705932QA publication Critical patent/SG10201705932QA/en

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    • H01L23/585Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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US9224688B2 (en) * 2013-01-04 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Metal routing architecture for integrated circuits
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