CN103050476A - 形成用于导电互连结构的保护和支撑结构的器件和方法 - Google Patents

形成用于导电互连结构的保护和支撑结构的器件和方法 Download PDF

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CN103050476A
CN103050476A CN2012103534232A CN201210353423A CN103050476A CN 103050476 A CN103050476 A CN 103050476A CN 2012103534232 A CN2012103534232 A CN 2012103534232A CN 201210353423 A CN201210353423 A CN 201210353423A CN 103050476 A CN103050476 A CN 103050476A
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conductive
insulating barrier
semiconductor wafer
layer
hole
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CN103050476B (zh
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林耀剑
陈康
方建敏
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及形成用于导电互连结构的保护和支撑结构的器件和方法。半导体器件具有含有多个接触焊盘的半导体晶片。第一绝缘层在半导体晶片和接触焊盘上形成。第一绝缘层的一部分被移除，从而露出接触焊盘的第一部分，同时留下接触焊盘的第二部分被覆盖。凸块下金属化层和多个凸块在接触焊盘和第一绝缘层上形成。第二绝缘层在第一绝缘层、凸块下金属化层的侧壁、凸块的侧壁以及凸块的上表面上形成。覆盖凸块的上表面的第二绝缘层的一部分被移除，但是第二绝缘层维持在凸块的侧壁和凸块下金属化层的侧壁上。

Description

形成用于导电互连结构的保护和支撑结构的器件和方法
主张国内优先权 
本申请为2011年9月21日提交的美国专利申请No.13/239,080的部分继续申请，该美国专利申请通过引用结合于此。
技术领域
本发明一般涉及半导体器件，且更具体地涉及一种形成用于导电互连结构的保护和支撑结构的半导体器件和方法。 
背景技术
常常在现代电子产品中发现半导体器件。半导体器件在电部件的数目和密度方面变化。分立的半导体器件一般包含一种类型的电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件典型地包含几百个到数以百万的电部件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池以及数字微镜器件（DMD）。 
半导体器件执行各种的功能，诸如信号处理、高速计算、发射和接收电磁信号、控制电子器件、将太阳光转变为电力以及产生用于电视显示的视觉投影。在娱乐、通信、功率转换、网络、计算机以及消费产品的领域中发现半导体器件。还在军事应用、航空、汽车、工业控制器和办公设备中发现半导体器件。 
半导体器件利用半导体材料的电属性。半导体材料的原子结构允许通过施加电场或基电流（base current）或通过掺杂工艺而操纵其导电性。掺杂向半导体材料引入杂质以操纵和控制半导体器件的导电性。 
半导体器件包含有源和无源电结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变掺杂水平和施加电场或基电流，晶体管要么促进要么限制电流的流动。包括电阻器、电容器和电感器的无源结构创建为执行各种电功能所必须的电压和电流之间的关系。无源和有源结构电连接以形成电路，这使得半导体器件能够执行高速计算和其他有用功能。 
半导体器件一般使用两个复杂的制造工艺来制造，即，前端制造和和后端制造，每一个可能涉及成百个步骤。前端制造涉及在半导体晶片的表面上形成多个管芯。每个半导体管芯典型地是相同的且包含通过电连接有源和无源部件而形成的电路。后端制造涉及从完成的晶片分割（singulate）各个半导体管芯且封装管芯以提供结构支撑和环境隔离。此处使用的术语“半导体管芯”指该措词的单数和复数形式，并且相应地可以指单个半导体器件和多个半导体器件。 
半导体制造的一个目的是生产较小的半导体器件。较小的器件典型地消耗较少的功率、具有较高的性能且可以更高效地生产。另外，较小的半导体器件具有较小的覆盖区（footprint），这对于较小的终端产品而言是希望的。较小的半导体管芯尺寸可以通过前端工艺中的改进来获得，该前端工艺中的改进导致半导体管芯具有较小、较高密度的有源和无源部件。后端工艺可以通过电互联和封装材料中的改进而导致具有较小覆盖区的半导体器件封装。 
传统半导体器件可含有安装到半导体基板的半导体管芯以减小通常层叠基板中发现的翘曲问题。可以形成诸如导电凸块或导电通孔的导电互连结构从而将半导体管芯安装和电连接到半导体基板，而不是使用接合引线，这是由于形成与接合引线的电互连的成本和制造复杂性的原因。然而，形成导电凸块的工艺会导致金属间化合物(IMC)的生长，这可能干涉半导体管芯的可操作性和功能。另外，导电凸块典型地具有与半导体管芯不同的材料和热属性，这造成各材料随热以不同速率膨胀和收缩。导电凸块和半导体材料的不同的膨胀和收缩速率导致导电凸块和半导体管芯之间的电连接的早期故障。另外，导电凸块材料的施加和回流会导致相邻导电凸块之间的桥接或电短路。替换地，形成导电通孔得到非常小的导电接触面积，这限制了与导电通孔电连接的功能、对准容易度以及可靠性。 
发明内容
对于提供一种简单、成本有效并且可靠的用于半导体管芯的垂直电互连结构存在需求。因此，在一个实施例中，本发明为一种制作半导体器件的方法，该方法包括下述步骤：提供具有多个接触焊盘的半导体晶片，在半导体晶片和接触焊盘上形成第一绝缘层，移除第一绝缘层的一部分以露出接触焊盘的第一部分，同时留下第一绝缘层覆盖的接触焊盘的第二部分，在接触焊盘和第一绝缘层上形成凸块下金属化层，在凸块下金属化层上形成多个凸块，在半导体晶片上形成第二绝缘层以覆盖第一绝缘层、凸块下金属化层的侧壁、凸块的侧壁以及凸块的上表面，以及移除覆盖凸块的上表面的第二绝缘层的一部分，同时维持第二绝缘层覆盖在凸块的侧壁和凸块下金属化层的侧壁上，从而为凸块提供结构支撑并且防止金属间化合物的生长。 
在另一实施例中，本发明为一种制作半导体器件的方法，该方法包括下述步骤：提供半导体晶片，形成贯穿半导体晶片、具有在半导体晶片的表面上延伸的一部分的多个导电通孔，在半导体晶片和导电通孔上形成绝缘层，以及移除覆盖导电通孔的上表面的绝缘层的一部分，同时维持绝缘层覆盖在导电通孔的侧壁上从而为导电通孔提供结构支撑。 
在另一实施例中，本发明为一种制作半导体器件的方法，该方法包括下述步骤：提供半导体晶片，形成具有在半导体晶片的表面上延伸的高度的导电互连结构，在半导体晶片和导电互连结构上形成绝缘层，以及移除覆盖导电互连结构的上表面的绝缘层的一部分，同时维持绝缘层覆盖在导电互连结构的侧壁上。 
在另一实施例中，本发明为一种包括半导体晶片的半导体器件。导电互连结构在半导体晶片上形成，该导电互连结构具有在半导体晶片上延伸的高度。绝缘层在半导体晶片上形成，该绝缘层露出导电互连结构的上表面，同时维持覆盖在导电互连结构的侧壁上。 
附图说明
图1说明不同类型的封装安装到其表面的印刷电路板； 
图2a-2c说明安装到印刷电路板的代表性半导体封装的另外细节；
图3a-3m说明在半导体器件上形成具有支撑和保护结构的导电凸块的工艺；
图4说明具有导电凸块的半导体器件，该导电凸块具有支撑和保护结构；
图5a-5o说明形成贯穿半导体器件的、具有支撑和保护结构以及电连接的接触焊盘的导电通孔的工艺；以及
图6说明贯穿半导体器件的、具有支撑和保护结构和电连接的接触焊盘的导电通孔。
具体实施方式
在下面的描述中，参考图以一个或更多实施例描述本发明，在这些图中相似的标号代表相同或类似的元件。尽管就用于实现本发明目的的最佳模式描述本发明，但是本领域技术人员应当理解，其旨在覆盖可以包括在如下面的公开和图支持的所附权利要求及其等价物限定的本发明的精神和范围内的替换、修改和等价物。 
半导体器件一般使用两个复杂制造工艺来制造：前端制造和后端制造。前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含有源和无源电部件，它们电连接以形成功能电路。诸如晶体管和二极管的有源电部件具有控制电流流动的能力。诸如电容器、电感器、电阻器和变压器的无源电部件创建为执行电路功能所必须的电压和电流之间的关系。 
通过包括掺杂、沉积、光刻、蚀刻和平坦化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过诸如离子注入或热扩散的技术将杂质引入到半导体材料中。掺杂工艺修改了有源器件中半导体材料的导电性，将半导体材料转变为绝缘体、导体，或者响应于电场或基电流而动态地改变半导体材料的导电性。晶体管包含不同类型和掺杂程度的区域，其按照需要被布置为使得当施加电场或基电流时晶体管能够促进或限制电流的流动。 
通过具有不同电属性的材料层形成有源和无源部件。层可以通过部分由被沉积的材料类型确定的各种沉积技术来形成。例如，薄膜沉积可以涉及化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解镀覆和化学镀覆工艺。每一层一般被图案化以形成有源部件、无源部件或部件之间的电连接的部分。 
图案化是通过其移除在半导体晶片表面上的顶层的部分的基本操作。可以使用光刻、光掩蔽、掩蔽、氧化物或金属移除、摄影和制版、以及显微光刻移除半导体晶片的部分。光刻包括在中间掩模（reticle）或光掩模中形成图案并且将该图案转印到半导体晶片的表面层。光刻在两个步骤的工艺中形成半导体晶片的表面上的有源和无源部件的水平尺度。第一，中间掩模或掩模上的图案转印到光致抗蚀剂的层。光致抗蚀剂为在暴露于光时经受结构和属性变化的光敏材料。或者作为负性作用光致抗蚀剂或者作为正性作用光致抗蚀剂，发生所述改变光致抗蚀剂的结构和属性的过程。第二，光致抗蚀剂层转印到晶片表面。当蚀刻移除未被光致抗蚀剂覆盖的半导体晶片的顶层的部分时，发生该转印。光致抗蚀剂的化学性质使得光致抗蚀剂缓慢溶解并且抵抗通过化学蚀刻溶液的移除，同时未被光致抗蚀剂覆盖的半导体晶片的顶层的部分被更快速地移除。形成、曝光和移除光致抗蚀剂的工艺以及移除半导体晶片的一部分的工艺可以根据所使用的具体抗蚀剂以及期望的结果来修改。 
在负性作用光致抗蚀剂中，光致抗蚀剂暴露于光，并且在已知为聚合的过程中从可溶解状态改变为不可溶解状态。在聚合中，未聚合材料暴露于光或能量源并且聚合物形成耐蚀刻的交联材料。在大多数负性抗蚀剂中，聚合物为聚异戊二烯(polyisopremes)。利用化学溶剂或显影剂移除可溶解部分(即未暴露于光的部分)在抗蚀剂层中留下对应于中间掩模上不透明图案的孔。图案存在于不透明区域中的掩模称为明场掩模。 
在正性作用光致抗蚀剂中，光致抗蚀剂暴露于光，并且在已知为光溶解化的过程中从相对不溶解状态改变为更加可溶解的状态。在光溶解化中，相对不可溶解的抗蚀剂暴露于适当的光能量并且转变为更加可溶解的状态。在显影过程中可以通过溶剂移除抗蚀剂的光溶解化部分。基本的正性光致抗蚀剂聚合物为酚醛聚合物，也称为酚醛清漆树脂。利用化学溶剂或显影剂移除可溶解部分(即暴露于光的部分)在抗蚀剂层中留下对应于中间掩模上透明图案的孔。图案存在于透明区域中的掩模称为暗场掩模。 
在移除未被光致抗蚀剂覆盖的半导体晶片的顶部部分之后，光致抗蚀剂的剩余部分被移除，留下图案化层。替换地，一些类型的材料通过使用诸如化学镀覆和电解镀覆这样的技术来直接向原先沉积/蚀刻工艺形成的区域或空位沉积材料而被图案化。 
在现有图案上沉积材料的薄膜可以放大底层图案且形成不均匀的平坦表面。需要均匀的平坦表面来生产更小且更致密填塞的有源和无源部件。平坦化可以用于从晶片的表面移除材料且产生均匀的平坦表面。平坦化涉及使用抛光垫对晶片的表面进行抛光。研磨材料和腐蚀化学物在抛光期间被添加到晶片的表面。组合的研磨物的机械行为和化学物的腐蚀行为移除任何不规则外貌，导致均匀的平坦表面。 
后端制造指将完成的晶片切割或分割为各个半导体管芯且然后封装半导体管芯以用于结构支撑和环境隔离。为了分割半导体管芯，晶片沿着称为锯道或划线的晶片的非功能区域被划片且折断。使用激光切割工具或锯条来分割晶片。在分割之后，各个半导体管芯被安装到封装基板，该封装基板包括引脚或接触焊盘以用于与其他系统部件互连。在半导体管芯上形成的接触焊盘然后连接到封装内的接触焊盘。电连接可以使用焊料凸块、柱形凸块、导电膏料或引线接合来制成。密封剂或其他成型材料沉积在封装上以提供物理支撑和电隔离。完成的封装然后被插入到电系统中且使得半导体器件的功能性对于其他系统部件可用。 
图1说明具有芯片载体基板或印刷电路板（PCB）52的电子器件50，该芯片载体基板或印刷电路板（PCB）52具有安装在其表面上的多个半导体封装。取决于应用，电子器件50可以具有一种类型的半导体封装或多种类型的半导体封装。用于说明性目的，在图1中示出了不同类型的半导体封装。 
电子器件50可以是使用半导体封装以执行一个或更多电功能的独立系统。替换地，电子器件50可以是较大系统的子部件。例如，电子器件50可以是蜂窝电话、个人数字助理（PDA）、数码摄像机（DVC）或其他电子通信器件的一部分。替换地，电子器件50可以是图形卡、网络接口卡或可以被插入到计算机中的其他信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件或其他半导体管芯或电部件。微型化和重量减小对于这些产品被市场接受是至关重要的。半导体器件之间的距离必须减小以实现更高的密度。 
在图1中，PCB 52提供用于安装到PCB上的半导体封装的结构支撑和电互连的一般性基板。使用蒸发、电解镀覆、化学镀覆、丝网印刷或者其他合适的金属沉积工艺，导电信号迹线54在PCB 52的表面上或其层内形成。信号迹线54提供半导体封装、安装的部件以及其他外部系统部件中的每一个之间的电通信。迹线54还向半导体封装中的每一个提供功率和接地连接。 
在一些实施例中，半导体器件具有两个封装级别。第一级封装是用于机械和电附连半导体管芯到中间载体的技术。第二级封装涉及机械和电附连中间载体到PCB。在其他实施例中，半导体器件可以仅具有第一级封装，其中管芯被直接机械和电地安装到PCB。 
用于说明目的，在PCB 52上示出包括接合引线封装56和倒装芯片58的若干类型的第一级封装。另外，示出在PCB 52上安装的若干类型的第二级封装，包括球栅阵列（BGA）60、凸块芯片载体（BCC）62、双列直插式封装（DIP）64、岸面栅格阵列（LGA）66、多芯片模块（MCM）68、四方扁平无引脚封装（QFN）70以及方形扁平封装72。取决于系统需求，使用第一和第二级封装类型的任何组合配置的半导体封装以及其他电子部件的任何组合可以连接到PCB 52。在一些实施例中，电子器件50包括单一附连的半导体封装，而其他实施例需要多个互连封装。通过在单个基板上组合一个或更多半导体封装，制造商可以将预制部件结合到电子器件和系统中。因为半导体封装包括复杂的功能性，可以使用较不昂贵的部件和流水线制造工艺来制造电子器件。所得到的器件较不倾向于发生故障且对于制造而言较不昂贵，导致针对消费者的较少的成本。 
图2a-2c示出示例性半导体封装。图2a说明安装在PCB 52上的DIP 64的进一步细节。半导体管芯74包括有源区域，该有源区域包含实现为根据管芯的电设计而在管芯内形成且电互连的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管、电感器、电容器、电阻器以及在半导体管芯74的有源区域内形成的其他电路元件。接触焊盘76是诸如铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）或银（Ag）的一层或多层导电材料，且电连接到半导体管芯74内形成的电路元件。在DIP 64的组装期间，半导体管芯74使用金-硅共熔层或者诸如热环氧物或环氧树脂的粘合剂材料而安装到中间载体78。封装体包括诸如聚合物或陶瓷的绝缘封装材料。导线80和接合引线82提供半导体管芯74和PCB 52之间的电互连。密封剂84沉积在封装上，以通过防止湿气和颗粒进入封装且污染半导体管芯74或接合引线82而进行环境保护。 
图2b说明安装在PCB 52上的BCC 62的进一步细节。半导体管芯88使用底层填料或者环氧树脂粘合剂材料92而安装在载体90上。接合引线94提供接触焊盘96和98之间的第一级封装互连。模塑料或密封剂100沉积在半导体管芯88和接合引线94上，从而为器件提供物理支撑和电隔离。接触焊盘102使用诸如电解镀覆或化学镀覆之类的合适的金属沉积工艺而在PCB 52的表面上形成以防止氧化。接触焊盘102电连接到PCB 52中的一个或更多导电信号迹线54。凸块104在BCC 62的接触焊盘98和PCB 52的接触焊盘102之间形成。 
在图2c中，使用倒装芯片类型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区域108包含实现为根据管芯的电设计而形成的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管、电感器、电容器、电阻器以及有源区域108内的其他电路元件。半导体管芯58通过凸块110电和机械连接到载体106。 
使用利用凸块112的BGA类型第二级封装，BGA 60电且机械连接到PCB 52。半导体管芯58通过凸块110、信号线114和凸块112电连接到PCB 52中的导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容且改善整体电路性能。在另一实施例中，半导体管芯58可以使用倒装芯片类型第一级封装来直接机械和电地连接到PCB 52而不使用中间载体106。 
与图1和2a-2c相关联，图3a-3m说明在半导体器件上形成具有支撑和保护结构的导电凸块的工艺。图3a示出具有用于结构支撑的基底基板材料122的半导体晶片120，该基底基板材料诸如是硅、锗、砷化镓、磷化铟或者碳化硅。如上所述，在晶片120上形成通过非有源的管芯间晶片区域或锯道126分离的多个半导体管芯或组件124。锯道126提供切割区域以将半导体晶片120分割成各个半导体管芯124。 
图3b示出半导体晶片120的一部分的剖面图。每个半导体管芯124具有背表面128和有源表面130，该有源表面包含实现为在管芯内形成的且根据管芯的电设计和功能而电互连的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多个晶体管、二极管以及在有源表面130内形成的其它电路元件以实现诸如数字信号处理器（DSP）、ASIC、存储器或其它信号处理电路之类的模拟电路或数字电路。半导体管芯124还可以包含诸如电感器、电容器和电阻器的集成无源器件(IPD)以用于RF信号处理。在一个实施例中，半导体管芯124是倒装芯片类型的器件。 
使用PVD、CVD、电解镀覆、化学镀覆工艺或其它合适的金属沉积工艺而在有源表面130上形成导电层132。导电层132可以是Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料的一层或更多层。导电层132操作为电连接到有源表面130上的电路的接触焊盘。接触焊盘132可以距半导体管芯124的边缘第一距离而并排布置，如图3b所示。替换地，接触焊盘132可以在多个行中偏移，使得接触焊盘的第一行距管芯边缘第一距离布置，并且接触焊盘的与第一行交替的第二行距管芯边缘第二距离布置。 
图3c示出半导体晶片120的一部分的放大剖面图，其侧重于接触焊盘132和紧接地围绕接触焊盘的区域。使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化，在有源表面130和导电层132上形成绝缘或钝化层134。绝缘层134含有二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)或具有相似绝缘和结构属性的其它材料的一个或多个层。利用蚀刻工艺通过光致抗蚀剂层(未示出)移除绝缘层134的一部分以形成开口136并且露出导电层132。替换地，使用激光器138通过激光直接消融(LDA)形成开口136以移除绝缘层134的一部分并且露出导电层132。在一个实施例中，开口136具有15μm-80μm的宽度。接触焊盘132的另一部分仍被绝缘层134覆盖。 
在图3d中，使用诸如印刷、PVD、CVD、电解镀覆和化学镀覆的图案化和金属沉积工艺，在绝缘层134和导电层132上沉积毯状导电层148。在一个实施例中，毯状导电层148用作种子层。种子层148可以是任何合适的合金种子层，诸如钛铜(TiCu)、钛钨铜(TiWCu)或钽氮铜(TaNCu)。种子层148循着绝缘层134和导电层132的轮廓。种子层148电连接到导电层132。 
使用印刷、旋涂或喷涂在种子层148、绝缘层134以及导电层132上沉积图案化或光致抗蚀剂层140。在利用绝缘层用于图案化的一些实施例中，绝缘层可包括SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有相似结构属性的其它材料的一个或多个层。通过蚀刻工艺移除光致抗蚀剂层140的一部分以形成开口144。开口144露出种子层148的一部分，并且被定位在导电层132上。在一个实施例中，开口144具有圆形横截面积，其配置成形成包括圆形横截面的具有圆柱形的导电凸块。在另一实施例中，开口144具有矩形横截面积，其配置成形成包括矩形横截面的具有立方形的导电凸块。 
在图3e中，使用诸如印刷、PVD、CVD、溅射、电解镀覆和化学镀覆的图案化和金属沉积工艺，在开口144内在种子层148上共形地施加导电层152。导电层152可以是Al、Cu、Sn、Ti、Ni、Au、Ag或其它合适的导电材料的一个或多个层。在一个实施例中，导电层152作为屏障层操作并且可以是Ni、镍钒(NiV)、铂(Pt)、钯(Pd)、TiW或CrCu或其它合适的材料。导电层152循着种子层148的轮廓。导电层152电连接到种子层148和导电层132。 
使用诸如印刷、PVD、CVD、溅射、电解镀覆和化学镀覆的图案化和金属沉积工艺，在导电层152上共形地施加导电层156。导电层156可以是Al、Cu、Sn、Ti、Ni、Au、Ag或其它合适的导电材料的一个或多个层。在一个实施例中，导电层156作为粘合层操作并且可以是Ti、TiN、TiW、Al或铬(Cr)或其它合适的材料。导电层156循着导电层152的轮廓。导电层156电连接到导电层152、种子层148和导电层132。 
在图3f中，使用蒸发、电解镀覆、化学镀覆、球滴或丝网印刷工艺，在开口144内和导电层156上沉积导电膏料或凸块材料158。导电凸块材料158可以是具有可选助焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、铋(Bi)、Cu、铟(In)、焊料及其组合。例如，导电凸块材料158可以是共熔Sn/Pb、高铅焊料或无铅焊料。使用合适的附连或接合工艺将导电凸块材料158接合到导电层156。由光致抗蚀剂层140的厚度和开口144的横截面积或孔径尺寸控制沉积在开口144内的导电凸块材料158的体积，由此控制随后形成的导电凸块的最后尺寸。 
在图3g中，使用蚀刻工艺移除光致抗蚀剂层140以及位于导电层152和156的覆盖区外的种子层148的一部分。种子层148、导电层152和导电层156的剩余部分总体地构成凸块下金属化(UBM)层159。多个凸块162电连接到导电层132，所述凸块包括大量的导电凸块材料158和UBM层159。在一个实施例中，通过将凸块材料158加热高于其熔点而回流凸块材料。在一些应用中，凸块162被二次回流以改善与导电层156的接触。凸块162具有从绝缘层134的上表面延伸到凸块材料158的上表面的高度H1。 
在图3h中，使用PVD、CVD、印刷、旋涂、喷涂、丝网印刷或层压，在凸块162和绝缘层134上沉积绝缘层170。绝缘层170可以是下述的一个或多个层：SiO2、Si3N4、SiON、Ta2O5、Al2O3、BCB、聚酰亚胺(PI)、合适的电介质材料、光敏或非光敏聚合物电介质(诸如聚苯并恶唑(PBO))、低温固化聚合物电介质抗蚀剂(例如低于250°C)、SiN、SiON或SiO2、或者具有相似绝缘和结构属性的其它材料。 
在图3i中，使用等离子体工艺、湿化学蚀刻、LDA或光致抗蚀剂显影工艺，毯状蚀刻绝缘层170，从而减小绝缘层170的厚度并且移除覆盖凸块162的绝缘层170的部分。在一个实施例中，可以在光刻显影工艺之前应用可选的盲UV曝光。其余的绝缘层170构成支撑结构180。 
支撑结构180覆盖凸块162的侧壁的一部分、UBM层159的侧壁、UBM层159和绝缘层134之间的结、以及与UBM层159相邻的绝缘层134。支撑结构180为凸块162提供结构支撑并且在材料膨胀和收缩期间帮助维持凸块162和接触焊盘132之间的电连接。支撑结构180也在环境上密封UBM层159和绝缘层134之间的结以减小出现IMC生长。支撑结构180还含有凸块162，在凸块材料158回流期间减小出现相邻凸块162之间的桥接或电学短路。在一个实施例中，端点检测或时控蚀刻被用于确保与凸块162相邻的支撑结构180的部分具有比H1的四分之一大的高度。 
在图3j所示的另一实施例中，支撑结构180覆盖凸块162的侧壁的一部分、UBM层159的侧壁、UBM层159和绝缘层134之间的结，以及与UBM层159相邻的绝缘层134的部分。移除绝缘层170的一部分以形成支撑结构180的毯状蚀刻工艺也移除绝缘层134上的支撑结构180的一部分。 
图3k示出在支撑结构180形成于绝缘层134和接触焊盘132上之后，具有圆形横截面的凸块162的顶视图或俯视图。支撑结构180围绕凸块材料158。图3l示出在支撑结构180形成于绝缘层134和接触焊盘132上之后，具有矩形横截面的凸块162的顶视图或俯视图。支撑结构180围绕凸块材料158。 
在图3m所示的一个实施例中，通过将导电凸块材料158加热高于其熔点而回流凸块材料158，形成凸块的穹形上表面162。在一些应用中，多次回流凸块材料158以改善电和机械连接。支撑结构180在回流工艺期间含有凸块材料158，并且减小出现相邻凸块162之间的桥接或电学短路。支撑结构180还在回流工艺期间减小IMC的生长。支撑结构180还在材料的膨胀和收缩期间为凸块162以及凸块162和接触焊盘132之间的电连接提供结构支撑。利用锯条或激光切割工具200沿着锯道126分割该组件。 
图4示出来自图3a-3m的分割后的组件。接触焊盘132形成于半导体管芯124的有源表面130上，并且电连接到UBM层159和凸块材料158。凸块材料158和UBM层159总体地构成凸块162。凸块162具有从绝缘层134的上表面延伸到凸块162的上表面的高度H1。 
绝缘层170形成于凸块162和半导体管芯124上。蚀刻绝缘层170以移除覆盖凸块162的上表面的绝缘层170的一部分。其余的绝缘层170构成支撑结构180。支撑结构180覆盖凸块162的侧壁的一部分、UBM层159的侧壁、UBM层159和绝缘层134之间的结、以及与UBM层159相邻的绝缘层134。在一个实施例中，与凸块162相邻的支撑结构180的一部分具有比H1的四分之一大的高度。 
支撑结构180为凸块162提供结构支撑，并且在材料膨胀和收缩期间帮助维持凸块162和接触焊盘132之间的电连接。支撑结构180还在环境上密封UBM层159和绝缘层134之间的结以减小出现IMC的生长。支撑结构180在凸块材料158回流期间含有凸块162以减小出现相邻凸块162之间的桥接或电学短路。 
与图1和2a-2c相关联，图5a-5n说明形成贯穿半导体器件的、具有支撑结构以及电连接的接触焊盘的导电通孔的工艺。在图5a中，临时基板或载体212含有牺牲基底材料，诸如硅、聚合物、氧化铍、玻璃或用于结构支撑的其它合适的低成本刚性材料。界面层或双面胶带213在载体212上形成作为临时粘合剂结合膜、蚀刻停止层或释放层。半导体晶片或基板214含有用于结构支撑的基底材料，诸如硅、锗、砷化镓、磷化铟或碳化硅。作为半导体晶片，基板214可以含有嵌入式集成半导体管芯或分立的器件。基板214也可以是多层柔性层叠、陶瓷或引线框。基板214具有非有源管芯间晶片区域或锯道216，以提供切割区域从而如上所述将基板214分割为各个半导体管芯。基板214安装到载体212上的界面层213。使用激光器钻孔、机械钻孔或DRIE，形成贯穿基板214的多个盲孔222。在一个实施例中，盲孔222不延伸穿过整个基板214。 
在图5b中，使用PVD、CVD、印刷、旋涂或喷涂，用衬里层225涂敷盲孔222的侧壁。衬里层225可以是氮化硅(SiN)、SiON、Ta2O3或其它绝缘薄膜的一个或多个层，连同合适的导电胶或屏障层，并且可包括任何合适的导电衬里合金，诸如TaN或TiN或任何其它合适的导电衬里材料。使用电解镀覆、化学镀覆工艺或其它合适的金属沉积工艺，用Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅或其它合适的导电材料填充盲孔222，以形成z方向垂直导电盲孔226。 
在图5c中，在临时基板或载体228上形成界面层227。载体228含有牺牲基底材料，诸如硅、聚合物、氧化铍、玻璃或用于结构支撑的其它合适的低成本刚性材料。界面层227用作临时粘合剂结合膜、蚀刻停止层或释放层。基板214被反转并且用界面层227安装在载体228上。导电盲孔226的表面接触界面层227。通过化学蚀刻、机械剥离、CMP、机械研磨、热烘烤、UV光、激光扫描或湿法剥离移除载体212和界面层213以露出基板214的表面。 
在图5d中，通过机械研磨、化学蚀刻、化学机械平坦化或反应离子蚀刻(RIE)移除基板214的一部分，以露出基板214的上表面以及导电通孔226的上部分。导电盲孔226具有横截面宽度W1。在一个实施例中，宽度W1为10μm。导电盲孔226具有从基板214的上表面延伸到覆盖导电盲孔226的表面230的衬里层225的部分的高度H2。 
在图5e中，通过机械研磨、化学蚀刻、化学机械平坦化或RIE移除覆盖导电盲孔226的衬里层225的部分，以露出导电盲孔226的表面230。在衬里层225包括绝缘材料和胶或屏障层的实施例中，在移除衬里层225的一部分以露出导电盲孔226的表面230之后，表面230提供接触表面以得到改善的导电盲孔226和随后形成的导电层之间的电互连。 
在图5f所示另一实施例中，通过机械研磨、化学蚀刻、化学机械平坦化或RIE移除覆盖导电盲孔226的衬里层225的部分的绝缘薄膜，同时留下包括衬里层225的胶或屏障层的导电材料。衬里层225的其余部分维持覆盖在导电盲孔226的表面230上并且构成导电衬里层231。导电衬里层231包括衬里层225的导电胶或屏障层、导电衬里合金或导电衬里材料。移除衬里层225的绝缘薄膜以在导电盲孔226的表面230上形成导电衬里层231，这使能实现改善的导电盲孔226和随后形成的导电层之间的电互连。 
从图5f继续，使用PVD、CVD、印刷、旋涂、喷涂、丝网印刷或层压，在基板214和导电通孔226上沉积绝缘层232，如图5g所示。绝缘层232可以是下述的一个或多个层：SiO2、Si3N4、SiON、Ta2O5、Al2O3、BCB、聚酰亚胺(PI)、合适的电介质材料、光敏或非光敏聚合物电介质，诸如聚苯并恶唑(PBO)、低温固化聚合物电介质抗蚀剂(例如低于250°C)、SiN、SiON或SiO2、或者具有相似绝缘和结构属性的其它材料。 
在图5h中，使用等离子体工艺、湿法化学蚀刻、LDA或光致抗蚀剂显影工艺来毯状蚀刻绝缘层232，以减小绝缘层232的厚度并且移除覆盖导电通孔226的上表面的绝缘层232的一部分。在一个实施例中，绝缘层232的毯状蚀刻工艺也可以移除覆盖导电盲孔226的衬里层225的部分，从而露出导电盲孔226的表面230。在衬里层225为绝缘材料的实施例中，移除衬里层225的一部分以露出导电盲孔226的表面230，表面230为导电盲孔226和随后形成的导电层之间的电互连提供接触表面。在衬里层225为导电合金的实施例中，露出导电盲孔226的表面230使能实现改善的导电盲孔226和随后形成的导电层之间的电互连。在毯状蚀刻工艺之后，绝缘层232的剩余部分构成支撑结构236。 
支撑结构236覆盖导电通孔226的侧壁的一部分、导电通孔226之间的结、以及与导电通孔226相邻的基板214。支撑结构236在材料膨胀和收缩期间为导电通孔226提供结构支撑。支撑结构236还在环境上密封导电通孔236和基板214之间的结以减小出现IMC的生长。在一个实施例中，端点检测或时控蚀刻被用于确保支撑结构236的与导电通孔226相邻的部分具有比H2的四分之一大的高度。 
在图5i所示另一实施例中，支撑结构236覆盖导电通孔226的侧壁的一部分、导电通孔226和基板214之间的结，以及与导电通孔226相邻的基板214的部分。移除绝缘层232的一部分以形成支撑结构236的毯状蚀刻工艺也移除绝缘层232上的支撑结构236的一部分。 
从图5h继续，使用PVD、CVD、电解镀覆、化学镀覆工艺或其它合适的金属沉积工艺，在支撑结构236、基板214以及导电通孔226上形成导电层242，如图5j所示。导电层242可以是Al、Cu、Sn、Ni、Au、Ag或其它合适的导电材料的一个或多个层。导电层242作为接触焊盘操作，该接触焊盘电连接到导电通孔226，但是上表面积大于导电通孔226的上表面积。 
在图5k中，使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化，在基板214、支撑结构236以及导电层242上形成绝缘或钝化层244。绝缘层244含有SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有相似绝缘和结构属性的其它材料的一个或多个层。 
在图5l中，利用蚀刻工艺通过光致抗蚀剂层(未示出)移除绝缘层244的一部分，从而形成开口248并且露出导电层242。替换地，使用激光器249通过LDA形成开口248，从而移除绝缘层244的一部分并且露出导电层242。在一个实施例中，开口248具有大于宽度W1的横截面宽度。接触焊盘242的另一部分仍被绝缘层244覆盖。开口248的侧壁可以具有逐渐变小、直的或者台阶式廓形。在一个实施例中，开口248的横截面积大于导电通孔226的上表面的表面积。 
图5m示出来自图5l的组件的顶视图或俯视图，该组件含有具有圆形横截面的开口248以露出导电层242的上表面的一部分。在一个实施例中，导电层242的露出的表面的表面积大于导电通孔226的上表面的表面积。图5n示出来自图5l的组件的顶视图或俯视图，该组件含有具有矩形横截面的开口248以露出导电层242的上表面的一部分。在一个实施例中，导电层242的露出的表面的表面积大于导电通孔226的上表面的表面积。因为露出的导电表面大于导电通孔226的表面积，与附加电子器件的电连接的对准、功能和可靠性得到改善。 
在图5o中，利用锯条或激光切割工具250，贯穿绝缘层244、支撑结构236、基板214以及锯道216将来自图5k的组件分割为各个半导体封装252。 
图6示出在分割后的半导体封装252。导电通孔226贯穿基板214形成并且具有从基板214的上表面延伸到导电通孔226的上表面的高度H2。 
绝缘层232形成于导电通孔226和基板214上。绝缘层232被蚀刻以移除覆盖导电通孔226的上表面的绝缘层232的一部分。其余的绝缘层232构成支撑结构236。支撑结构236覆盖导电通孔226的侧壁的一部、导电通孔226和基板214之间的结以及与导电通孔226相邻的基板214。在一个实施例中，与导电通孔226相邻的支撑结构236的部分具有大于H2的四分之一的高度。 
在导电通孔226和基板214的膨胀和收缩期间，支撑结构236为导电通孔226提供结构支撑。支撑结构236还在环境上密封导电通孔226和基板214之间的结以减小出现IMC的生长。 
导电层242形成于支撑结构236、导电通孔226和基板214上，并且作为接触焊盘操作。导电层242以比导电通孔226的表面积大的表面积电连接到导电通孔226。绝缘层244形成于导电层242上并且绝缘层244的一部分通过蚀刻工艺被移除以形成开口248。在一个实施例中，开口248的横截面积大于导电通孔226的上表面。由于露出的导电表面大于导电通孔226的表面积，与附加电子器件的电连接的对准、功能和可靠性得到改善。 
尽管已经详细说明了本发明的一个或更多实施例，但是本领域技术人员应当意识到，可以在不偏离如随后的权利要求提及的本发明的范围的情况下对那些实施例做出修改和改写。 

Claims (20)

1.一种制作半导体器件的方法，该方法包括：
提供具有多个接触焊盘的半导体晶片；
在半导体晶片和接触焊盘上形成第一绝缘层；
移除第一绝缘层的一部分以露出接触焊盘的第一部分，同时留下第一绝缘层覆盖的接触焊盘的第二部分；
在接触焊盘和第一绝缘层上形成凸块下金属化层；
在凸块下金属化层上形成多个凸块；
在半导体晶片上形成第二绝缘层以覆盖第一绝缘层、凸块下金属化层的侧壁、凸块的侧壁以及凸块的上表面；以及
移除覆盖凸块的上表面的第二绝缘层的一部分，同时维持第二绝缘层覆盖在凸块的侧壁和凸块下金属化层的侧壁上，从而为凸块提供结构支撑并且防止金属间化合物的生长。
2.权利要求1所述的方法，其中移除第二绝缘层的部分进一步包括维持在凸块的侧壁处的第二绝缘层的厚度大于凸块的高度的四分之一。
3.权利要求1所述的方法，其中移除第二绝缘层的部分进一步包括维持第二绝缘层覆盖在凸块的覆盖区外的第一绝缘层上。
4.权利要求1所述的方法，其中形成凸块下金属化层进一步包括：
在多个接触焊盘上形成粘合层；
在粘合层上形成屏障层；以及
在屏障层上形成润湿层。
5.一种制作半导体器件的方法，包括：
提供半导体晶片；
形成贯穿半导体晶片、具有在半导体晶片的表面上延伸的一部分的多个导电通孔；
在半导体晶片和导电通孔上形成绝缘层；以及
移除覆盖导电通孔的上表面的绝缘层的一部分，同时维持绝缘层覆盖在导电通孔的侧壁上从而为导电通孔提供结构支撑。
6.权利要求5所述的方法，其中形成导电通孔进一步包括：
在半导体晶片上形成临时基板；
形成贯穿临时基板和半导体晶片的多个通孔；
在多个通孔中沉积导电材料；以及
移除临时基板。
7.权利要求6所述的方法，进一步包括：
在多个通孔中沉积衬里层；以及
移除衬里层的一部分以露出导电材料。
8.权利要求6所述的方法，进一步包括：
沉积包括绝缘薄膜和导电衬里材料的衬里层；以及
移除导电通孔上的绝缘薄膜的一部分以形成导电衬里层。
9.权利要求5所述的方法，其中移除绝缘层的部分包括维持绝缘层的厚度大于在半导体晶片的表面上延伸的导电通孔的部分的高度的四分之一。
10.权利要求5所述的方法，进一步包括：
形成位于导电通孔上并且电连接到导电通孔的导电层；
在半导体晶片和导电层上形成绝缘层；以及
移除在导电层上的绝缘层的一部分，以露出导电层的大于导电通孔的上表面的表面积的表面积。
11.一种制作半导体器件的方法，该方法包括：
提供半导体晶片；
形成具有在半导体晶片的表面上延伸的高度的导电互连结构；
在半导体晶片和导电互连结构上形成绝缘层；以及
移除覆盖导电互连结构的上表面的绝缘层的一部分，同时维持绝缘层覆盖在导电互连结构的侧壁上。
12.权利要求11所述的方法，其中形成导电互连结构进一步包括在半导体晶片上形成多个导电凸块。
13.权利要求11所述的方法，其中形成导电互连结构进一步包括形成贯穿半导体晶片的多个导电通孔。
14.权利要求11所述的方法，其中移除绝缘层的部分进一步包括维持绝缘层的厚度大于在半导体晶片的表面上延伸的导电互连结构的高度的四分之一。
15.权利要求11所述的方法，其中移除绝缘层的部分进一步包括维持位于导电互连结构周缘外的绝缘层。
16.一种半导体器件，包括：
半导体晶片；
在半导体晶片上形成的、具有在半导体晶片上延伸的高度的导电互连结构；以及
在半导体晶片上形成的绝缘层，该绝缘层露出导电互连结构的上表面，同时维持覆盖在导电互连结构的侧壁上。
17.权利要求16所述的半导体器件，还包括在导电互连结构的上表面上形成的导电层。
18.权利要求16所述的半导体器件，其中导电互连结构包括在半导体晶片上形成的多个导电凸块。
19.权利要求16所述的半导体器件，其中导电互连结构包括贯穿半导体晶片形成的多个导电通孔。
20.权利要求16所述的半导体器件，其中与导电互连结构相邻的绝缘层的厚度大于在半导体晶片的表面上延伸的互连结构的高度的四分之一。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104471680A (zh) * 2012-07-16 2015-03-25 美光科技公司 垫上柱体互连结构、半导体裸片及包含所述互连结构的裸片组合件及相关方法
CN108231728A (zh) * 2016-12-12 2018-06-29 英飞凌科技奥地利有限公司 半导体器件、电子组件及方法
CN108604571A (zh) * 2015-11-20 2018-09-28 德卡科技公司 全模制周边堆叠封装设备
CN112585772A (zh) * 2018-09-20 2021-03-30 国际商业机器公司 混合凸块下金属化部件

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9142517B2 (en) * 2012-06-05 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding mechanisms for semiconductor wafers
US20140327132A1 (en) * 2013-05-03 2014-11-06 National Center For Advanced Packaging (Ncap China) TSV Backside Reveal Structure and Exposing Process
WO2015047731A1 (en) * 2013-09-27 2015-04-02 Applied Materials, Inc. Method of enabling seamless cobalt gap-fill
US10163705B2 (en) 2014-04-28 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Profile of through via protrusion in 3DIC interconnect
US20150366081A1 (en) * 2014-06-15 2015-12-17 Unimicron Technology Corp. Manufacturing method for circuit structure embedded with electronic device
KR101706470B1 (ko) * 2015-09-08 2017-02-14 앰코 테크놀로지 코리아 주식회사 표면 마감층을 갖는 반도체 디바이스 및 그 제조 방법
KR102617086B1 (ko) 2018-11-15 2023-12-26 삼성전자주식회사 Ubm을 포함하는 웨이퍼-레벨 반도체 패키지
CN111952244B (zh) * 2020-08-24 2023-04-07 浙江集迈科微电子有限公司 一种柔性电路板侧壁互联工艺
JP2024515633A (ja) * 2021-04-22 2024-04-10 ティーディーケイ・エレクトロニクス・アクチェンゲゼルシャフト 金属化半導体ダイ及びその製造方法
FR3140475A1 (fr) * 2022-10-03 2024-04-05 Commissariat à l'Energie Atomique et aux Energies Alternatives Puce électronique comportant une métallisation de type UBM

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1304174A (zh) * 1999-07-02 2001-07-18 国际商业机器公司 具有高密度互连层的电子封装件
US20030071352A1 (en) * 1999-04-06 2003-04-17 Shinji Ohuchi Method of fabricating resin-encapsulated semiconductor device
US20110187000A1 (en) * 2009-09-03 2011-08-04 Texas Instruments Incorporated Integrated Circuits Having TSVS Including Metal Gettering Dielectric Liners

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS577141A (en) 1980-06-16 1982-01-14 Fujitsu Ltd Semiconductor device
JP2763020B2 (ja) 1995-04-27 1998-06-11 日本電気株式会社 半導体パッケージ及び半導体装置
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US6806578B2 (en) * 2000-03-16 2004-10-19 International Business Machines Corporation Copper pad structure
JP2003037129A (ja) 2001-07-25 2003-02-07 Rohm Co Ltd 半導体装置およびその製造方法
US6593220B1 (en) 2002-01-03 2003-07-15 Taiwan Semiconductor Manufacturing Company Elastomer plating mask sealed wafer level package method
TWI281718B (en) 2002-09-10 2007-05-21 Advanced Semiconductor Eng Bump and process thereof
JP4035066B2 (ja) 2003-02-04 2008-01-16 株式会社ルネサステクノロジ 半導体装置の製造方法
TWI239629B (en) 2003-03-17 2005-09-11 Seiko Epson Corp Method of manufacturing semiconductor device, semiconductor device, circuit substrate and electronic apparatus
TW594959B (en) 2003-05-02 2004-06-21 Yu-Nung Shen Semiconductor chip package structure and method
TWI228306B (en) 2003-07-21 2005-02-21 Advanced Semiconductor Eng Method for forming a bump protective collar
TWI225701B (en) 2003-09-17 2004-12-21 Advanced Semiconductor Eng Process for forming bumps in adhesive layer in wafer level package
WO2006070808A1 (ja) * 2004-12-28 2006-07-06 Rohm Co., Ltd. 半導体チップおよびその製造方法、半導体チップの電極構造およびその形成方法、ならびに半導体装置
US7390688B2 (en) * 2005-02-21 2008-06-24 Casio Computer Co.,Ltd. Semiconductor device and manufacturing method thereof
US20060192280A1 (en) 2005-02-28 2006-08-31 General Electric Company Method of forming electronic devices
JP4745007B2 (ja) * 2005-09-29 2011-08-10 三洋電機株式会社 半導体装置及びその製造方法
TWI273639B (en) 2005-10-13 2007-02-11 Advanced Semiconductor Eng Etchant and method for forming bumps
JP5222459B2 (ja) * 2005-10-18 2013-06-26 新光電気工業株式会社 半導体チップの製造方法、マルチチップパッケージ
US8409970B2 (en) 2005-10-29 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of making integrated passive devices
TWI298204B (en) 2005-11-21 2008-06-21 Advanced Semiconductor Eng Structure of bumps forming on an under metallurgy layer and method for making the same
JP2008016508A (ja) 2006-07-03 2008-01-24 Nec Electronics Corp 半導体装置およびその製造方法
US7563694B2 (en) 2006-12-01 2009-07-21 Atmel Corporation Scribe based bond pads for integrated circuits
JP4902558B2 (ja) * 2007-01-31 2012-03-21 三洋電機株式会社 半導体モジュールの製造方法
SG149807A1 (en) 2007-07-30 2009-02-27 Stats Chippac Ltd Semiconductor device and method of providing common voltage bus and wire bondable redistribution
US8049310B2 (en) 2008-04-01 2011-11-01 Qimonda Ag Semiconductor device with an interconnect element and method for manufacture
US8183087B2 (en) 2008-09-09 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming a fan-out structure with integrated passive device and discrete component
US7772081B2 (en) 2008-09-17 2010-08-10 Stats Chippac, Ltd. Semiconductor device and method of forming high-frequency circuit structure and method thereof
TW201019440A (en) 2008-11-03 2010-05-16 Int Semiconductor Tech Ltd Bumped chip and semiconductor flip-chip device applied from the same
US7910473B2 (en) 2008-12-31 2011-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon via with air gap
JP2011009363A (ja) 2009-06-24 2011-01-13 Nec Corp 半導体装置及びその製造方法並びにこれを用いた複合回路装置
US8263434B2 (en) * 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
JP5475363B2 (ja) * 2009-08-07 2014-04-16 ラピスセミコンダクタ株式会社 半導体装置およびその製造方法
US8324738B2 (en) 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure
US20110169158A1 (en) 2010-01-14 2011-07-14 Qualcomm Incorporated Solder Pillars in Flip Chip Assembly
US8368187B2 (en) * 2010-02-03 2013-02-05 Stats Chippac, Ltd. Semiconductor device and method of forming air gap adjacent to stress sensitive region of the die
US8378480B2 (en) 2010-03-04 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy wafers in 3DIC package assemblies
US20110291263A1 (en) * 2010-05-28 2011-12-01 Texas Instruments Incorporated Ic having dielectric polymeric coated protruding features having wet etched exposed tips

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030071352A1 (en) * 1999-04-06 2003-04-17 Shinji Ohuchi Method of fabricating resin-encapsulated semiconductor device
CN1304174A (zh) * 1999-07-02 2001-07-18 国际商业机器公司 具有高密度互连层的电子封装件
US20110187000A1 (en) * 2009-09-03 2011-08-04 Texas Instruments Incorporated Integrated Circuits Having TSVS Including Metal Gettering Dielectric Liners

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104471680A (zh) * 2012-07-16 2015-03-25 美光科技公司 垫上柱体互连结构、半导体裸片及包含所述互连结构的裸片组合件及相关方法
CN104471680B (zh) * 2012-07-16 2018-02-16 美光科技公司 垫上柱体互连结构、半导体裸片、裸片组合件及相关方法
CN108604571A (zh) * 2015-11-20 2018-09-28 德卡科技公司 全模制周边堆叠封装设备
CN108604571B (zh) * 2015-11-20 2023-02-17 美国德卡科技公司 全模制周边堆叠封装设备
CN108231728A (zh) * 2016-12-12 2018-06-29 英飞凌科技奥地利有限公司 半导体器件、电子组件及方法
US11380612B2 (en) 2016-12-12 2022-07-05 Infineon Technologies Austria Ag Semiconductor device, electronic component and method
CN112585772A (zh) * 2018-09-20 2021-03-30 国际商业机器公司 混合凸块下金属化部件
CN112585772B (zh) * 2018-09-20 2024-04-23 国际商业机器公司 混合凸块下金属化部件

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