CN112585772A - 混合凸块下金属化部件 - Google Patents
混合凸块下金属化部件 Download PDFInfo
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- CN112585772A CN112585772A CN201980052991.9A CN201980052991A CN112585772A CN 112585772 A CN112585772 A CN 112585772A CN 201980052991 A CN201980052991 A CN 201980052991A CN 112585772 A CN112585772 A CN 112585772A
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- 238000001465 metallisation Methods 0.000 title claims abstract description 244
- 229910000679 solder Inorganic materials 0.000 claims abstract description 222
- 238000000034 method Methods 0.000 claims abstract description 104
- 238000009736 wetting Methods 0.000 claims abstract description 68
- 230000008878 coupling Effects 0.000 claims description 68
- 238000010168 coupling process Methods 0.000 claims description 68
- 238000005859 coupling reaction Methods 0.000 claims description 68
- 239000000463 material Substances 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 29
- 238000000151 deposition Methods 0.000 claims description 22
- 238000005476 soldering Methods 0.000 claims description 11
- 238000003466 welding Methods 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 6
- 229910000765 intermetallic Inorganic materials 0.000 claims description 2
- 230000001737 promoting effect Effects 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 61
- 230000015572 biosynthetic process Effects 0.000 description 33
- 230000003647 oxidation Effects 0.000 description 25
- 238000007254 oxidation reaction Methods 0.000 description 25
- 238000012545 processing Methods 0.000 description 25
- 238000004519 manufacturing process Methods 0.000 description 24
- 229920002120 photoresistant polymer Polymers 0.000 description 24
- 238000003860 storage Methods 0.000 description 23
- 230000008901 benefit Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 17
- 238000005516 engineering process Methods 0.000 description 15
- 238000005240 physical vapour deposition Methods 0.000 description 15
- 230000006870 function Effects 0.000 description 14
- 238000001704 evaporation Methods 0.000 description 13
- 230000008020 evaporation Effects 0.000 description 13
- 238000004544 sputter deposition Methods 0.000 description 13
- 230000008569 process Effects 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 11
- 230000004888 barrier function Effects 0.000 description 8
- 230000006872 improvement Effects 0.000 description 8
- 239000002096 quantum dot Substances 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 7
- 238000004590 computer program Methods 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 7
- 239000010949 copper Substances 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 238000007789 sealing Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 239000000835 fiber Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000004070 electrodeposition Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 230000005055 memory storage Effects 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000001902 propagating effect Effects 0.000 description 2
- 230000005233 quantum mechanics related processes and functions Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000002887 superconductor Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910020658 PbSn Inorganic materials 0.000 description 1
- 101150071746 Pbsn gene Proteins 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- PSMFTUMUGZHOOU-UHFFFAOYSA-N [In].[Sn].[Bi] Chemical compound [In].[Sn].[Bi] PSMFTUMUGZHOOU-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- CFJRGWXELQQLSA-UHFFFAOYSA-N azanylidyneniobium Chemical compound [Nb]#N CFJRGWXELQQLSA-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- -1 but not limited to Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000012993 chemical processing Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005520 electrodynamics Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 230000003340 mental effect Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000001393 microlithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000001127 nanoimprint lithography Methods 0.000 description 1
- 238000005329 nanolithography Methods 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- RJSRQTFBFAJJIL-UHFFFAOYSA-N niobium titanium Chemical compound [Ti].[Nb] RJSRQTFBFAJJIL-UHFFFAOYSA-N 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001690 polydopamine Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76891—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by using superconducting materials
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/0361—Physical or chemical etching
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- H01L2224/03622—Manufacturing methods by patterning a pre-deposited material using masks
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- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
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- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Abstract
提供了可以促进混合凸块下金属化部件的器件和方法。根据实施例,器件包括凸块下金属化部件(124B),其包括超导互连部件和焊料润湿部件(112)。该器件还包括焊料凸块(122),该焊料凸块耦合到超导互连部件和焊料润湿部件。在一些实施例中,超导互连部件包括气密密封的超导互连部件。
Description
背景技术
本发明涉及超导器件,更具体地,涉及在半导体衬底上制造的超导且机械上鲁棒的凸块下金属化部件。
量子计算通常是为了执行计算和信息处理功能的目的而使用量子力学现象。量子计算可以被看作与经典计算相反,经典计算通常利用晶体管对二进制值进行操作。即,虽然经典计算机可以对0或1的位值进行操作,但是量子计算机对包括0和1的叠加的量子位进行操作,可以纠缠多个量子位,并且使用干扰。
量子计算硬件可以不同于经典计算硬件。特别地,量子计算硬件通常包括超导量子电路,其可以在半导体器件中制造并且在可以在这样的量子计算硬件中使用的倒装芯片封装的量子器件中采用。这样的量子计算硬件(例如,超导量子处理器)可以执行计算和信息处理功能,这些计算和信息处理功能实质上比经典计算装置(例如,通用计算机、专用计算机等)可以执行的更复杂。
与设计可以在倒装芯片封装的量子器件中实现的这种超导量子电路相关联的挑战包括但不限于:在这种超导量子电路和/或倒装芯片封装的量子器件的不同部件之间提供超导互连和机械上鲁棒的互连;以及在这种电路和/或器件的各种部件之间提供气密密封的超导互连。现有的超导量子电路和/或倒装芯片封装的量子器件试图克服以上列出的一个或多个挑战;然而,这种现有技术电路和/或器件不能这样做,或者它们产生设计折衷、制造折衷和/或其它问题,例如缺乏性能可靠性和/或过度的功耗。
例如,一些现有技术的超导量子电路和/或倒装芯片封装的量子器件在这种电路和/或器件的各种部件之间提供超导互连。这种现有技术的问题包括但不限于:它们不提供气密密封的超导互连;和/或这种电路和/或器件的各种部件的机械耦合较弱。在另一示例中,一些现有技术的电路和/或器件提供集成电路和/或倒装芯片封装器件的各种部件的强机械耦合。这种现有技术的问题包括但不限于:它们不提供这种集成电路和/或倒装芯片封装器件的各种部件之间的超导互连;和/或它们不提供这些各种部件之间的气密密封的超导互连。
因此,在本领域中需要解决上述问题。
发明内容
从第一方面来看,本发明提供了一种器件,包括:包括超导互连部件和焊料润湿(solder wetting)部件的凸块下金属化部件;以及耦合到超导互连部件和焊料润湿部件的焊料凸块。
从另一方面来看,本发明提供了一种方法,包括:在凸块下金属化部件上沉积焊料;以及基于所述沉积在所述凸块下金属化部件上形成超导互连部件和金属间化合物层。
从另一方面来看,本发明提供了一种器件,包括:具有超导层和金属间化合物层的衬底;以及焊料凸块,其耦合到超导层和金属间化合物层。
从另一方面来看,本发明提供了一种器件,包括:第一凸块下金属化部件,其包括超导互连部件和金属间化合物层;以及焊料凸块,其耦合到所述超导互连部件、所述金属间化合物层和第二凸块下金属化部件。
从另一方面来看,本发明提供了一种方法,包括:将第一凸块下金属化部件耦合到包括超导互连部件和金属间化合物层的第二凸块下金属化部件;以及基于所述耦合在第一凸块下金属化部件上形成气密密封的超导互连部件。
以下给出了概述以提供对本发明的一个或多个实施例的基本理解。本概述不旨在标识关键或重要元素,或描绘特定实施例的任何范围或权利要求的任何范围。其唯一目的是以简化形式呈现概念,作为稍后呈现的更详细描述的序言。在本文所述的一个或多个实施例中,描述了促进混合凸块下金属化部件的器件、系统、计算机实现的方法、装置和/或计算机程序产品。
根据实施例,器件可以包括凸块下金属化部件,该凸块下金属化部件可以包括超导互连部件和焊料润湿部件。该器件还可以包括焊料凸块,该焊料凸块可以耦合到超导互连部件和焊料润湿部件。这种器件的优点是它可以促进超导量子电路和/或倒装芯片封装的量子器件的各种部件之间的超导互连以及它们的鲁棒机械耦合。
在另一个实施例中,超导互连部件可包括气密密封的超导互连部件。这种器件的优点是它可以消除在超导量子电路和/或倒装芯片封装的量子器件的各种部件之间的氧化物形成(例如,氧化),这些部件可以通过这种气密密封的超导互连部件耦合,由此促进在这些部件之间的改进的电耦合。
根据一个实施例,一种方法可包括在凸块下金属化部件上沉积焊料。该方法还可以包括基于沉积在凸块下金属化部件上形成超导互连部件和金属间化合物层。这种方法的优点在于,它可以用于制造混合凸块下金属化部件,其可以促进超导量子电路和/或倒装芯片封装的量子器件的各种部件之间的超导互连和各种部件的鲁棒机械耦合。
在另一实施例中,该方法还可包括基于沉积在凸块下金属化部件上形成气密密封的超导互连部件。这种方法的优点在于,它可以用于制造混合凸块下金属化部件,该部件可以消除在超导量子电路和/或倒装芯片封装量子器件的各种部件之间的氧化物形成(例如,氧化),这些部件可以由这种气密密封的超导互连部件耦合,由此促进这些部件之间的改进的电耦合。
根据一个实施例,一种器件可以包括衬底,该衬底可以具有超导层和金属间化合物层。该器件可进一步包括可耦合到所述超导层及所述金属间化合物层的焊料凸块。这种器件的优点是它可以促进超导量子电路和/或倒装芯片封装的量子器件的各种部件之间的超导互连以及它们的鲁棒机械耦合。
在另一实施例中,超导层可以被金属间化合物层或焊料凸块中的至少一个气密密封。这种器件的优点是它可以消除在超导量子电路和/或倒装芯片封装的量子器件的各种部件之间的氧化物形成(例如,氧化),这些部件可以通过这种气密密封的超导层耦合,从而促进这种部件之间的改进的电耦合。
根据实施例,一种器件可以包括第一凸块下金属化部件,该第一凸块下金属化部件可以包括超导互连部件和金属间化合物层。该器件还可以包括焊料凸块,该焊料凸块可以耦合到超导互连部件、金属间化合物层和第二凸块下金属化部件。这种器件的优点是它可以促进超导量子电路和/或倒装芯片封装的量子器件的各种部件之间的超导互连以及它们的鲁棒机械耦合。
在另一个实施例中,超导互连部件可包括气密密封的超导互连部件。这种器件的优点是它可以消除在超导量子电路和/或倒装芯片封装的量子器件的各种部件之间的氧化物形成(例如,氧化),这些部件可以通过这种气密密封的超导互连部件耦合,由此促进在这些部件之间的改进的电耦合。
根据一个实施例,一种方法可包括将第一凸块下金属化部件耦合到包括超导互连部件和金属间化合物层的第二凸块下金属化部件。该方法还可包括基于该耦合在第一凸块下金属化部件上形成气密密封的超导互连部件。这种方法的优点在于,它可以用于制造倒装芯片器件,其可以促进这种倒装芯片器件的各种部件之间的超导互连以及这些部件的鲁棒机械耦合。这种方法的另一个优点是,它可用于制造倒装芯片器件,其可以消除在可通过这种气密密封的超导互连部件耦合的这种倒装芯片器件的各种部件之间的氧化物形成(例如,氧化),从而促进这种部件之间的改进的电耦合。
附图说明
现在将参考附图仅通过示例的方式描述本发明的实施例,在附图中:
图1A示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的截面侧视图。
图1B示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的截面侧视图。
图1C示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的截面侧视图。
图1D示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的截面侧视图。
图2A示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的截面侧视图。
图2B示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的截面侧视图。
图2C示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的截面侧视图。
图2D示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的实例非限制性装置的截面侧视图。
图3A示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的顶视图。
图3B示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的顶视图。
图3C示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的顶视图。
图3D示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的顶视图。
图4A示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的截面侧视图。
图4B示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的截面侧视图。
图5A示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的截面侧视图。
图5B示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的截面侧视图。
图5C示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的截面侧视图。
图5D示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的截面侧视图。
图6A示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的截面侧视图。
图6B示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的截面侧视图。
图7A示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的截面侧视图。
图7B示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件的截面侧视图。
图8示出了根据本文所述的一个或多个实施例的促进实现混合凸块下金属化部件的示例非限制性方法的流程图。
图9示出了根据本文所述的一个或多个实施例的促进实现混合凸块下金属化部件的示例非限制性方法的流程图。
图10示出了其中可促进本文所述的一个或多个实施例的示例非限制性操作环境的框图。
具体实施方式
以下详细描述仅是说明性的,并且不旨在限制实施例和/或实施例的应用或使用。此外,并不意图被前面的背景技术或发明内容部分或具体实施方式部分中呈现的任何明示或暗示的信息所限制。
现在参考附图描述一个或多个实施例,其中相同的附图标记始终用于表示相同的元件。在以下描述中,出于解释的目的,阐述了许多具体细节以便提供对一个或多个实施例的更透彻理解。然而,在各种情况下,显然可在没有这些特定细节的情况下实践所述一个或多个实施例。
鉴于现有超导量子电路和/或倒装芯片封装的量子器件的上述问题不利于这种电路和/或器件的各种部件之间的超导互连和它们的鲁棒机械耦合两者,本公开可以被实施以产生对这个问题的解决方案,其形式为可以包括超导互连部件和金属间化合物层的混合凸块下金属化部件。这种器件的优点是它可以促进超导量子电路和/或倒装芯片封装的量子器件的各种部件之间的超导互连以及它们的鲁棒机械耦合。
此外,考虑到现有超导量子电路和/或倒装芯片封装的量子器件的不包括在这种电路和/或器件的各种部件之间的气密密封的超导互连和鲁棒机械耦合的上述问题,本公开可以被实施以产生对该问题的解决方案,其形式为可以包括气密密封的超导互连部件和金属间化合物层的混合凸块下金属化部件。这种器件的优点是它可以消除在超导量子电路和/或倒装芯片封装的量子器件的各种部件之间的氧化物形成(例如,氧化),这些部件可以通过这种气密密封的超导互连部件耦合,由此促进在这些部件之间的改进的电耦合。
图1A-1D示出了示例非限制性的多步骤制造序列,其可以被实施以制造本文所描述的和/或附图中所示出的本公开的一个或多个实施例。例如,图1A-1D中所示的非限制性多步骤制造序列可被实施以制造器件100D(图1D中所示),其可包括根据本文所述的一个或多个实施例的凸块下金属化部件124B。
根据多个实施例,在此描述的和/或在附图中示出的本公开(例如,器件100D、凸块下金属化部件124B等)可以构成超导量子电路和/或超导量子器件(例如,量子计算器件、量子计算硬件等)的一个或多个部件。在一些实施例中,本文所述和/或附图所示的本公开(例如,器件100D、凸块下金属化部件124B等)可以利用用于制造集成电路的一种或多种技术在半导体器件中制造。
如以下参照图1A-1D所述,本文所述和/或附图所示的本发明的各实施例(例如,器件100D、凸块下金属化部件124B等)的制造可包括例如光刻和/或化学处理步骤的多步骤序列,其促进在一个或多个衬底层上逐渐形成基于电子(例如,基于微电子)的系统、器件、部件和/或电路。例如,本文描述和/或在附图中示出的本公开的各种实施例(例如,器件100D、凸块下金属化部件124B等)可以通过采用包括但不限于以下各项的技术来制造:光刻、微光刻、纳米光刻、纳米压印光刻、光掩蔽技术、图案化技术、光刻胶技术、蚀刻技术(例如,反应离子蚀刻(RIE)、干法蚀刻、湿法蚀刻等)、蒸发技术、溅射技术、等离子体灰化技术、热处理(例如,快速热退火、炉退火、热氧化等)、化学气相沉积(CVD)、物理气相沉积(PVD)、分子束外延(MBE)、电化学沉积(ECD)、化学机械平坦化(CMP)、背面研磨技术和/或用于制造集成电路的另一种技术。
如以下参照图1A-1D所述,可使用各种材料来制造本文所述和/或附图所示的本发明的各种实施例(例如,器件100D、凸块下金属化部件124B等)的制造。例如,可以使用一种或多种不同材料类别的材料来制造本文描述和/或附图中示出的本公开的各种实施例(例如,器件100D、凸块下金属化部件124B等),所述材料类别包括但不限于:导电材料、半导体材料、超导材料、介电材料、聚合物材料、有机材料、无机材料、非导电材料和/或可与上述用于制造集成电路的一种或多种技术一起使用的另一种材料。
图1A示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件100A的截面侧视图。根据若干实施例,器件100A可以包括衬底102、第一超导层104、第二超导层106(其可以保护第一超导层104的氧化)、第三超导层108(其可以改善第二超导层106和焊料扩散层110之间的粘附力)、焊料扩散层110和/或焊料润湿层112。
根据多个实施例,衬底102可包括半导体材料。例如,衬底102可以包括硅(Si)、蓝宝石(例如,氧化铝(Al2O3))和/或另一种半导体材料。例如,衬底102可以包括硅(Si)、蓝宝石(例如,氧化铝(Al2O3))和/或能够降低低温下的介电损耗角正切的另一种半导体材料。
在一些实施例中,衬底102可以包括确保耦合到衬底102的所有材料层和/或部件的机械稳定性的任何厚度。例如,可将衬底102研磨(例如,经由背面研磨)至10微米(μm)-1,000μm范围内的厚度(例如,高度)。
根据多个实施例,第一超导层104可以包括超导材料。例如,第一超导层104可以包括铌(Nb)、铝(Al)、铼(Re)、钨(W)、金刚石和/或另一种超导材料。
在一些实施例中,第一超导层104可以耦合到衬底102。例如,第一超导层104可以耦合(例如,电、机械、操作、化学等)到衬底102的顶侧。在一些实施例中,为了促进这种耦合,第一超导层104可以沉积在衬底102的顶侧上。例如,第一超导层104可以通过采用包括但不限于物理气相沉积(PVD)、溅射、蒸发的技术和/或另一将第一超导层104沉积在衬底102上的技术,沉积在衬底102的顶侧上,如图1A所示。在一些实施例中,第一超导层104可以沉积(例如,经由PVD、溅射、蒸发等)到衬底102上,使得第一超导层104可以包括范围例如从50纳米(nm)-500nm的厚度(例如,高度)。
在一些实施例中,第一超导层104可包括超导互连部件。例如,第一超导层104可以包括可以将衬底102耦合(例如,电耦合、可操作地耦合等)到第二超导层106的超导互连部件。
根据多个实施例,第二超导层106可以包括超导材料。例如,第二超导层106可以包括氮化钛(TiN)、氮化铌(NbN)、氮化钛铌(TiNbN)、硅化物和/或另一种超导材料。
在一些实施例中,第二超导层106可以耦合到第一超导层104。例如,第二超导层106可以耦合(例如,电耦合、机械耦合、操作耦合、化学耦合等)到第一超导层104的顶侧。在一些实施例中,为了促进这种耦合,可以在不破坏真空的情况下在第一超导层104的顶侧上沉积第二超导层106,从而防止第一超导层104的氧化。例如,可以通过采用包括但不限于PVD、溅射、蒸发的技术和/或另一将第二超导层106沉积到第一超导层104上的技术,来将第二超导层106沉积在第一超导层104的顶侧上,如图1A所示。在一些实施例中,第二超导层106可以沉积(例如,经由PVD、溅射、蒸发等)到第一超导层104上,使得第二超导层106可以包括范围例如从1nm至100nm的厚度(例如,高度)。
在一些实施例中,第二超导层106可以包括超导互连部件。例如,第二超导层106可以包括可以将第一超导层104耦合(例如,电耦合、操作耦合等)到第三超导层108的超导互连部件。在另一示例中,第二超导层106可以包括可以将第一超导层104耦合(例如,电耦合、操作耦合等)到焊料凸块122的超导互连部件(例如,如下面参考图2A-2D所述)。
在一些实施例中,第二超导层106可以包括导线接合层。例如,第二超导层106可以包括可以将第一超导层104耦合(例如,电耦合、操作耦合等)到第三超导层108的导线接合层。在另一示例中,第二超导层106可以包括可以将第一超导层104耦合(例如,电耦合、操作耦合等)到焊料凸块122的导线接合层(例如,如下面参考图2A-2D所述)。
在一些实施例中,第二超导层106可以包括氧化阻挡层。例如,第二超导层106可以包括可以防止第一超导层104的氧化的氧化阻挡层。
根据多个实施例,第三超导层108可包括超导材料。例如,第三超导层108可以包括超导材料,包括但不限于钛(Ti)、钽(Ta)、钨(W)、铝(Al)和/或另一种超导材料。
在一些实施例中,第三超导层108可以耦合到第二超导层106。例如,第三超导层108可以耦合(例如,电、机械、操作、化学等)到第二超导层106的顶侧。在一些实施例中,为了促进这种耦合,第三超导层108可以沉积在第二超导层106的顶侧上。例如,可以通过采用包括但不限于PVD、溅射、蒸发的技术和/或另一将第三超导层108沉积到第二超导层106上的技术,来将第三超导层108沉积在第二超导层106的顶侧上,如图1A所示。在一些实施例中,第三超导层108可以沉积(例如,经由PVD、溅射、蒸发等)到第二超导层106上,使得第三超导层108可以包括范围例如从5nm至500nm的厚度(例如,高度)。
在一些实施例中,第三超导层108可包括超导互连部件。例如,第三超导层108可以包括可以将第二超导层106耦合(例如,电耦合、操作耦合等)到焊料扩散层110和/或焊料凸块122的超导互连部件,如下面参考图1C和1D所述。在一些实施例中,第三超导层108可以包括粘附层。例如,第三超导层108可以包括能够提供第二超导层106和焊料扩散层110之间的改进的粘附层。
根据多个实施例,焊料扩散层110可以包括能够与焊料反应以形成金属间化合物层的材料,其中焊料扩散层110可以通过与焊料反应而被部分消耗(不完全消耗)。例如,焊料扩散层110可以包括这样的材料,包括但不限于铂(Pt)、钯(Pd)、镍(Ni)、铜(Cu)、铟(In)、锡(Sn)和/或另一种材料,其可以与焊料(例如,下面参考图1C描述的焊料凸块122)反应以形成金属间化合物层(例如,下面参考图1C描述的金属间化合物层120),但在与焊料反应之后不被完全消耗(例如,在形成金属间化合物层120之后,焊料扩散层110的一部分仍然在图1C中示出)。
在一些实施例中,焊料扩散层110可以耦合到第三超导层108。例如,焊料扩散层110可以耦合(例如,电、机械、操作、化学等)到第三超导层108的顶侧。在一些实施例中,为了促进这种耦合,焊料扩散层110可以沉积在第三超导层108的顶侧上。例如,可以通过采用包括但不限于PVD、溅射、蒸发的技术和/或如图1A所示的将焊料扩散层110沉积到第三超导层108上的另一技术,将焊料扩散层110沉积在第三超导层108的顶侧上。在一些实施例中,焊料扩散层110可以沉积(例如,经由PVD、溅射、蒸发等)到第三超导层108上,使得焊料扩散层110可以包括范围例如从5nm至1000nm的厚度(例如,高度)。
在一些实施例中,焊料扩散层110可以包括氧化阻挡层。例如,焊料扩散层110可以包括氧化阻挡层,其可以防止第三超导层108的氧化。在一些实施例中,焊料扩散层110可以包括焊料润湿层,其可以与焊料反应以形成金属间化合物层。例如,焊料扩散层110可以包括焊料润湿层,其可以与焊料(例如,如下面参考图1C描述的焊料凸块122)反应以形成金属间化合物层(例如,如下面参考图1C描述的金属间化合物层120)。
根据多个实施例,焊料润湿层112可以包括焊料润湿材料,该焊料润湿材料可以与熔融焊料反应以混合到焊料中。在一些实施例中,焊料润湿层112在接触焊料之前不应被氧化。例如,焊料润湿层112可以包括金(Au)和/或另一种焊料润湿材料,其可以与熔融焊料(例如,如下面参考图1C描述的焊料凸块122)反应以混合到焊料中并且允许在焊料凸块122和焊料扩散层110之间形成金属间化合物层(例如,图1B中的焊料润湿层112在图1C中未示出)。在一些实施例中,焊料润湿层112可以耦合到焊料扩散层110。例如,焊料润湿层112可以耦合(例如,电、机械、操作、化学等)到焊料扩散层110的顶侧。在一些实施例中,为了促进这种耦合,可以在焊料扩散层110的顶侧上沉积焊料润湿层112。例如,如图1A所示,可以通过采用包括但不限于PVD、溅射、蒸发的技术和/或将焊料润湿层112沉积到焊料扩散层110上的其它技术,将焊料润湿层112沉积在焊料扩散层110的顶侧上。在一些实施例中,焊料润湿层112可沉积(例如,通过PVD、溅射、蒸发等)到焊料扩散层110上,使得焊料润湿层112可包括例如范围从5nm-1000nm的厚度(例如,高度)。
在一些实施例中,焊料润湿层112可以包括氧化阻挡层。例如,焊料润湿层112可以包括氧化阻挡层,其可以防止焊料扩散层110的氧化。
图1B示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件100B的截面侧视图。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。根据若干实施例,装置100B可包括一个或多个沟道114、光致抗蚀剂层116、开口118及/或凸块下金属化部件124A。
根据多个实施例,沟道114可以穿过器件100A的焊料润湿层112和焊料扩散层110形成,以形成器件100B。例如,沟道114可以穿过焊料润湿层112和焊料扩散层110形成,使得第三超导层108的顶表面暴露(例如,如图1B中描述的实施例中所示)。在一些实施例中,通过在器件100A上采用一种或多种光刻胶技术、光掩模技术、构图技术和/或蚀刻技术,可以穿过焊料润湿层112和焊料扩散层110形成沟道114。例如,可以通过以下步骤形成穿过焊料润湿层112和焊料扩散层110的沟道114:将光掩模和/或光致抗蚀剂施加到焊料润湿层112的顶表面,使得可以将期望的沟道114的几何图案(例如,沟道114的二维(2D)形状)叠加在焊料润湿层112的顶表面上;以及蚀刻(例如,通过RIE、干法蚀刻、湿法蚀刻等)沟道114的期望几何图案进入并穿过焊料润湿层112和焊料扩散层110,使得第三超导层108的顶表面被暴露(例如,如图1B中描述的实施例中所示)。
在一些实施例中,沟道114可包括多种形状。例如,沟道114的形状可以限定在沿图1A-1D的X轴和Z轴延伸的2D平面中,这可以在器件100B的顶视图中观察到(例如,如图3A-3D中所示的示例性实施例所呈现的)。在一些实施例中,可以以形成包括但不限于环形、正方形、矩形、圆形、六边形、八边形、菱形和/或可以在沿图1A-1D的X轴和Z轴延伸的这种2D平面中限定的其它形状的方式穿过焊料润湿层112和焊料扩散层110蚀刻沟道114。
根据多个实施例,光致抗蚀剂层116可包括各种类型的光致抗蚀剂材料。例如,光致抗蚀剂层116可以包括光致抗蚀剂材料,包括但不限于干膜光致抗蚀剂、液体光致抗蚀剂和/或另一类型的光致抗蚀剂。
在一些实施例中,光致抗蚀剂层116可以被施加到衬底102,使得光致抗蚀剂层116可以形成围绕(例如,包围、包含等)沉积在衬底102上的各种材料层(例如,第一超导层104、第二超导层106、第三超导层108、焊料扩散层110和/或焊料润湿层112)的壁结构。在一些实施例中,光致抗蚀剂层116可以被施加到衬底102,使得光致抗蚀剂层116可以形成围绕沉积在衬底102和开口118上的各种材料层的壁结构(例如,如图1B中描绘的实施例中所示)。在一些实施方式中,可将光致抗蚀剂层116施加至衬底102,使得光致抗蚀剂层116的厚度(例如,高度)可在例如10μm至200μm的范围内。
根据多个实施例,凸块下金属化部件124A可包括器件100B的一个或多个材料层。例如,凸块下金属化部件124A可以包括第三超导层108、焊料扩散层110和/或焊料润湿层112。
图1C示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件100C的截面侧视图。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。根据若干实施例,器件100C可包括一个或多个金属间化合物层120、焊料凸块122及/或凸块下金属化部件124B。
根据多个实施例,熔融焊料,例如注射成型焊料(IMS),可以被注入到器件100B上并注入到沟道114中以形成器件100C。例如,通过使用填充头器件(图1A-1D中未示出),可以将注射成型的焊料(IMS)注射到器件100B上和沟道114中,该填充头器件可以将该IMS注射到器件100B的开口118中,以填充由光致抗蚀剂层116包围的体积(例如,如图1B和1C中描述的实施例所示)。在一些实施例中,IMS可以包括各种类型的焊料材料。例如,IMS可以包括焊接材料,包括但不限于铟(In)、铋(Bi)、锡(Sn)、铅锡(PbSn)、铟-铋-锡合金(InBiSn)、铟-锡合金(InSn)和/或其他材料。在一些实施例中,IMS可包括低温(cryogenic)相当的焊料。
在一些实施例中,将熔融焊料(例如IMS)注射到装置100B上且注射到沟道114中(例如,如上文所描述)可促进金属间化合物层120的形成。例如,焊料润湿层112和焊料扩散层110可以与IMS反应以促进金属间化合物层120的形成。例如,焊料润湿层112可以包括金(Au),其可以扩散到IMS中,并且焊料扩散层110可以包括铂(Pt)、钯(Pd)、镍(Ni)和/或另一种材料,其可以与例如IMS的铟(In)反应以促进金属间化合物层120的形成。
在一些实施例中,焊料润湿层112可以被可以注入到器件100B上和注入到沟道114中的熔融焊料(例如IMS)完全消耗(例如,如上所述),这可以促进金属间化合物层120的形成。例如,焊料润湿层112的所有材料(例如Au)可以扩散到IMS中以促进金属间化合物层120的形成。在一些实施例中,焊料扩散层110可以被可以注入到器件100B上并且注入到沟道114中的熔融焊料(例如IMS)部分地消耗(例如,如上所述),这可以进一步促进金属间化合物层120的形成。例如,焊料扩散层110的一些材料(例如,Pt、Pd、Ni等)可以与IMS(例如,IMS中的铟(In))反应以促进金属间化合物层120的形成。在一些实施例中,基于IMS到器件100B上和到沟道114中的注入(例如,如上文所描述),金属间化合物层120可因此包括例如IMS、焊料扩散层110、焊料润湿层112和/或焊料凸块122的材料,其可由IMS形成(例如,如下文所描述)。
在一些实施例中,将熔融焊料(例如IMS)注入到器件100B上和注入到沟道114中(例如如上所述)可以促进形成焊料凸块122。例如,注入到器件100B上和注入到沟道114中的IMS可以如图1C所示固化,从而由于IMS的表面张力而促进形成焊料凸块122。
在一些实施例中,将熔融焊料(例如IMS)注入到器件100B上和注入到沟道114中(例如如上所述)可以促进形成凸块下金属化部件124B。例如,注入到器件100B上和注入到沟道114中的IMS可以促进金属间化合物层120的形成(例如,如上所述)。在该示例中,基于金属间化合物层120的这种形成,可以完成凸块下金属化部件124B的形成,因为凸块下金属化部件124B可以包括第三超导层108、焊料扩散层110和/或金属间化合物层120。
在一些实施例中,凸块下金属化部件124B可包括混合凸块下金属化部件。例如,凸块下金属化部件124B可以包括混合凸块下金属化部件,该混合凸块下金属化部件可以包括机械互连部件(例如,如下所述的焊料扩散层110、焊料润湿层112和/或金属间化合物层120)和气密性密封的超导互连部件(例如,如下所述通过焊料凸块122对第三超导层108的气密性密封)。
在一些实施例中,金属间化合物层120可构成可将焊料凸块122机械耦合到器件100C的一个或多个部件的机械互连组件。例如,金属间化合物层120可以将焊料凸块122机械耦合到第三超导层108、焊料扩散层110、焊料润湿层112和/或凸块下金属化部件124B。应当理解,这种机械耦合可以促进器件100C(和/或器件100D)的改进的机械完整性,这可以是本公开相对于现有技术的优点。还应了解,此机械耦合可促进焊料凸块122到凸块下金属化部件124B的机械连接的强度的改进,借此促进这些部件的电耦合的改进(例如,电连接一致性的改进),此可为本发明的优于现有技术的优点。
在一些实施例中,凸块下金属化部件124B可包括气密密封的超导互连部件。例如,基于IMS到器件100B上和到沟道114中的注入(例如,如上所述),填充沟道114的IMS可以气密地密封第三超导层108的顶表面,其由此可以构成气密密封的超导互连部件(例如,由焊料凸块122气密密封)。应当理解,这种气密密封可以防止在第三超导层108和焊料凸块122之间形成氧化物(例如,氧化),从而促进改善这些部件的电耦合,这可以是本公开相对于现有技术的优点。
图1D示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件100D的截面侧视图。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
根据多个实施例,器件100D可以包括没有光致抗蚀剂层116的器件100C。例如,基于促进金属间化合物层120、焊料凸块122和/或凸块下金属化部件124B(例如,如上所述)的形成的IMS的固化,可从器件100C剥离(例如,经由RIE、干法蚀刻、湿法蚀刻等)光致抗蚀剂层116以形成器件100D。
图2A-2D示出了示例性的、非限制性的多步骤制造序列,其可以被实施以制造本文所描述的和/或附图中所示出的本公开的一个或多个实施例。例如,图2A-2D中所示的非限制性多步骤制造序列可被实施以制造器件200D(图2D中描绘),其可包括根据本文所述的一个或多个实施例的凸块下金属化部件204B。
根据多个实施例,图2A-2D中示出的示例性、非限制性多步骤制造序列可以包括以上参考图1A-1D描述的制造序列的替代示例性制造序列。例如,图2A-2D中所示的制造序列可以被实施以制造器件100A、100B、100C和/或100D的替代示例实施例(例如,如下所述)。
图2A示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件200A的截面侧视图。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
根据若干实施例,器件200A可以包括器件100A的替代示例实施例,其中器件200A不包括焊料润湿层112。另外或替代地,在一些实施例中,上文参看图1A描述的可经实施以制造器件100A的制造序列也可经实施以制造器件200A,其中可从此制造序列省略焊料润湿层112的沉积以形成器件200A。
图2B示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件200B的截面侧视图。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
根据若干实施例,器件200B可包括上文参看图1B描述的器件100B的替代示例性实施例。在一些实施例中,器件200B可以包括一个或多个沟道202。在一些实施例中,器件200B可以包括沉积在焊料扩散层110和第二超导层106上的焊料润湿层112(例如,如图2B中所描绘的实施例中所图示的)。在一些实施例中,器件200B可包括凸块下金属化部件204A,其可包括图1B的凸块下金属化部件124A的替代示例性实施例。
根据多个实施例,沟道202可以包括以上参考器件100B和图1B描述的沟道114的替代示例实施例,其中沟道202可以形成为穿过器件200A的焊料扩散层110和第三超导层108以暴露第二超导层106的顶表面。例如,可以通过以下步骤穿过焊料扩散层110和第三超导层108形成沟道202:将光掩模和/或光致抗蚀剂施加到焊料扩散层110的顶表面,使得沟道202的期望几何图案(例如,沟道202的二维(2D)形状)可以叠加在焊料扩散层110的顶表面上;以及蚀刻(例如,通过RIE、干法蚀刻、湿法蚀刻等)沟道202的期望几何图案进入并穿过焊料扩散层110和第三超导层108,使得第二超导层106的顶表面被暴露。在一些实施例中,基于沟道202的形成,焊料润湿层112可以沉积在焊料扩散层110的顶表面和第二超导层106的顶表面上。例如,基于沟道202的形成,可以通过采用包括但不限于PVD、溅射、蒸发的技术和/或另一种技术将焊料润湿层112沉积到焊料扩散层110和第二超导层106上,来将焊料润湿层112沉积在焊料扩散层110的顶表面和第二超导层106的顶表面上,如图2B所示。在一些实施例中,焊料润湿层112可以沉积(例如,经由PVD、溅射、蒸发等)到焊料扩散层110和第二超导层106上,使得焊料润湿层112可以包括例如范围从5nm-1000nm的厚度(例如,高度)。
在一些实施例中,焊料润湿层112可以包括氧化阻挡层。例如,焊料润湿层112可以包括氧化阻挡层,其可以防止焊料扩散层110和/或第二超导层106的氧化。
图2C示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件200C的截面侧视图。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
根据若干实施例,器件200C可包括器件100C的替代示例性实施例,其中器件200C包括凸块下金属化部件204B,其可包括图1C的凸块下金属化部件124B的替代示例性实施例。另外或替代地,在一些实施例中,上文参看图1C描述的可经实施以制造器件100C的制造序列也可经实施以制造器件200C。例如,熔融焊料(例如IMS)可以被注入到器件200B上和注入到沟道202中,以促进形成器件200C的金属间化合物层120、焊料凸块122和/或凸块下金属化部件204B。
在一些实施例中,凸块下金属化部件204B的金属间化合物层120可以构成机械互连部件,该机械互连部件可以将焊料凸块122机械地耦合到例如第二超导层106、第三超导层108、焊料扩散层110、焊料润湿层112和/或凸块下金属化部件204B。在一些实施例中,基于IMS到器件200B上和到沟道202中的注入(例如,如上所述),填充沟道202的IMS可以气密地密封第三超导层108的一个或多个侧表面和第二超导层106的顶表面,由此可以构成气密密封的超导互连部件(例如,由焊料凸块122气密密封)。
图2D示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件200D的截面侧视图。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
根据多个实施例,器件200D可以包括没有光致抗蚀剂层116的器件200C。例如,基于促进金属间化合物层120、焊料凸块122和/或凸块下金属化部件204B(例如,如上所述)的形成的IMS的固化,可从器件200C剥离(例如,经由RIE、干法蚀刻、湿法蚀刻等)光致抗蚀剂层116以形成器件200D。
图3A示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件300A的顶视图。根据多个实施例,器件300A可以分别包括图1B和图2B的器件100B或器件200B,其中为了清楚起见,在图3A中未示出光致抗蚀剂层116。在图3A中,虚线304指示相对于器件300A出现的器件100A和器件100B的截面侧视图的位置。
为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
根据多个实施例,器件300A可以包括层302,其可以包括第三超导层108或焊料润湿层112。例如,器件300A可以包括图1B的器件100B,并且在这样的实施例中,层302可以包括第三超导层108。在另一示例中,器件300A可以包括图2B的器件200B,并且在这样的实施例中,层302可以包括焊料润湿层112。
图3B示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件300B的顶视图。根据多个实施例,器件300B可以包括图1B的器件100B、图2B的器件200B和/或图3A的器件300A的替代示例实施例。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
图3C示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件300C的顶视图。根据多个实施例,器件300C可以包括图1B的器件100B、图2B的器件200B和/或图3A的器件300A的替代示例实施例。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
图3D示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件300D的俯视图。根据多个实施例,器件300D可以包括图1B的器件100B、图2B的器件200B和/或图3A的器件300A的替代示例实施例。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
在一些实施例中,凸块下金属化部件124B和/或凸块下金属化部件204B可包括与各种技术相关联的混合凸块下金属化部件、器件、系统和/或工艺。例如,可以与量子位(qubit)技术、量子电路技术、超导电路技术、电路量子电动力学(cQED)技术、量子计算技术、量子处理器技术、超导体器件制造技术、半导体器件制造技术、倒装芯片器件技术、半导体器件封装技术、超导体器件封装技术、量子硬件技术和/或其它技术相关联。
在一些实施例中,凸块下金属化部件124B和/或凸块下金属化部件204B可提供对与以上列出的各种技术相关联的系统、器件、部件、操作步骤和/或处理步骤的技术改进。例如,凸块下金属化部件124B和/或凸块下金属化部件204B可以提供气密密封的超导互连(例如,由焊料凸块122气密密封的第二超导层106和/或第三超导层108),其可以防止在耦合到这样的气密密封的超导互连的部件之间(例如,在第二超导层106和/或第三超导层108与焊料凸块122之间)形成氧化物(例如,氧化),由此促进这样的部件的改进的电耦合。在另一示例中,凸块下金属化部件124B和/或凸块下金属化部件204B可以提供凸块下金属化部件124B和/或凸块下金属化部件204B到焊料凸块122的改进的机械耦合(例如,经由焊料扩散层110、焊料润湿层112和/或金属间化合物层120)。在该示例中,这种改进的机械耦合可促进包括凸块下金属化部件124B和/或凸块下金属化部件204B的倒装芯片器件(例如,量子位(qubit)芯片、量子硬件、超导量子处理器、量子计算器件等)的改进的机械完整性。
在一些实施例中,凸块下金属化部件124B和/或凸块下金属化部件204B可对与凸块下金属化部件124B和/或凸块下金属化部件204B相关联的处理单元提供技术改进。例如,由凸块下金属化部件124B和/或凸块下金属化部件204B(例如,如上所述)提供的改进的电和机械耦合可以促进执行与凸块下金属化部件124B和/或凸块下金属化部件204B(例如,量子处理器)相关联的处理单元的处理工作负荷所必需的改进的电连接性。在该示例中,这种改进的电连接性可促进完成给定处理工作量所需的处理周期更少,由此促进改善包括凸块下金属化部件124B和/或凸块下金属化部件204B的处理单元(例如,超导量子处理器)的处理效率和/或性能,这可降低这种处理单元的功耗。
在一些实施例中,凸块下金属化部件124B和/或凸块下金属化部件204B可采用硬件和/或软件来解决本质上是高度技术性的、非抽象的且不能由人类作为一组脑力活动来执行的问题。例如,凸块下金属化部件124B和/或凸块下金属化部件204B可促进超导互连的气密密封,该超导互连可在用于实现可基于量子力学现象处理信息和/或执行计算的量子计算装置的倒装芯片装置中采用。
应了解,凸块下金属化部件124B和/或凸块下金属化部件204B可促进利用不能在人的头脑中复制或由人执行的电组件、机械组件和电路(例如,超导量子电路)的各种组合的超导互连工艺。例如,促进可以使能一个量子计算装置(例如,量子处理器、量子计算机等)的操作的超导互连是大于人类头脑的能力的操作。例如,在某一时间段内由凸块下金属化部件124B及/或凸块下金属化部件204B处理的数据量、处理此类数据的速度及/或数据类型可大于、快于及/或不同于在相同时间段内可由人类头脑处理的量、速度及/或数据类型。
根据若干实施例,凸块下金属化部件124B和/或凸块下金属化部件204B也可以完全可操作以执行一个或多个其它功能(例如,完全通电、完全执行等),同时还执行以上提及的超导互连工艺。还应当理解,这种同时多操作执行超出了人类头脑的能力。还应了解,凸块下金属化部件124B及/或凸块下金属化部件204B可包含不可能由实体(例如,人类用户)手动获得的信息。例如,包括在凸块下金属化部件124B和/或凸块下金属化部件204B中的信息的类型、数量和/或种类可以比由人类用户手动获得的信息更复杂。
图4A示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件400A的截面侧视图。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
根据多个实施例,器件400A可包括器件406和图2D的器件200D。在一些实施例中,器件406可包括图1B的器件100B、图2B的器件200B和/或图3A的器件300A的替代示例实施例。在一些实施例中,器件406可以包括衬底402,其可以包括衬底102。在一些实施例中,衬底402可以包括量子位(量子位)芯片。
在一些实施例中,器件406可包括凸块下金属化部件404A,其可包括以上参照图2B描述的器件200B的凸块下金属化部件204A的替代示例实施例。在一些实施例中,凸块下金属化部件404A可以(例如,电、机械、操作、化学等)耦合到凸块下金属化部件204B。例如,为了促进将凸块下金属化部件404A耦合到凸块下金属化部件204B,器件406可以(例如,电、机械、操作、化学等)耦合到器件200D以形成器件400B(例如,如下面参考图4B所描述的)。
图4B示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件400B的截面侧视图。
为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。根据多个实施例,器件400B可包括凸块下金属化部件404B,其可包括凸块下金属化部件204B的替代示例实施例。
根据多个实施例,可以通过将器件406耦合(例如,电、机械、操作、化学等)到器件200D来形成器件400B。例如,器件406可以通过采用回流焊接技术耦合(例如,电、机械、操作、化学等)到器件200D。例如,可以通过热源(图4A和4B中未示出)向器件200D的焊料凸块122施加热量,使得焊料凸块122从固态转变为液态和/或半液态(例如,焊料回流状态)。在此示例中,基于实施此回流焊接技术,器件406的凸块下金属化部件404A可插入至焊料凸块122中,藉此促进凸块下金属化部件404B及器件400B的形成。在此示例中,实施此回流焊接技术并将凸块下金属化部件404A插入焊料凸块122中可促进凸块下金属化部件404B的金属间化合物层120的形成,如图4B中所描绘的实施例中所说明。
在一些实施例中,器件400B可以包括倒装芯片器件。例如,器件400B可以包括倒装芯片器件,该倒装芯片器件包括一个或多个气密密封的超导互连部件(例如,第二超导层106、第三超导层108、焊料凸块122等)和/或一个或多个机械互连部件(例如,焊料扩散层110、焊料润湿层112、金属间化合物层120、焊料凸块122等)。
图5A示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件500A的截面侧视图。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
根据多个实施例,器件500A可以包括图2D的器件502和器件200D。在一些实施例中,器件502可包括图1B的器件100B、图2B的器件200B和/或图3A的器件300A的替代示例实施例。在一些实施例中,器件502可包括凸块下金属化部件504,其可包括上文参看图2B描述的器件200B的凸块下金属化部件204A的替代示例实施例。在一些实施例中,凸块下金属化部件504可以(例如,电、机械、操作、化学等)耦合到凸块下金属化部件204B。例如,为了促进将凸块下金属化部件504耦合到凸块下金属化部件204B,器件502可以(例如,电、机械、操作、化学等)耦合到器件200D以形成器件500B(例如,如下面参考图5B所描述的)。
图5B示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件500B的截面侧视图。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
根据多个实施例,可以通过将器件502耦合(例如,电、机械、操作、化学等)到器件200D来形成器件500B。例如,器件502可以通过采用冷焊技术(也称为接触焊接)而(例如,电、机械、操作、化学等)耦合到器件200D。在此实例中,基于实施此冷焊技术,器件502的凸块下金属化部件504可插入且耦合到焊料凸块122,借此促进器件500B的形成及将凸块下金属化部件504耦合(例如,电、机械、操作、化学等)到凸块下金属化部件204A。
在一些实施例中,器件500B可以包括倒装芯片器件。例如,器件500B可以包括倒装芯片器件,该倒装芯片器件包括一个或多个气密密封的超导互连部件(例如,第二超导层106、第三超导层108、焊料凸块122等)和/或一个或多个机械互连部件(例如,焊料扩散层110、焊料润湿层112、金属间化合物层120、焊料凸块122等)。
图5C示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件500C的截面侧视图。为了简洁起见,省略了对在此描述的其他实施例中采用的类似元件的重复描述。
根据多个实施例,器件500C可以包括器件506和图2D的器件200D。在一些实施例中,器件506可包括图1B的器件100B、图2B的器件200B和/或图3A的器件300A的替代示例实施例。在一些实施例中,器件506可包括凸块下金属化部件508,其可包括以上参照图2B描述的器件200B的凸块下金属化部件204A的替代示例实施例。在一些实施例中,凸块下金属化部件508可耦合(例如,电、机械、操作、化学等)到凸块下金属化部件204B。例如,为了促进将凸块下金属化部件508耦合到凸块下金属化部件204B,器件506可以耦合(例如,电、机械、操作、化学等)到器件200D以形成器件500D(例如,如下面参考图5D所描述的)。
图5D示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件500D的截面侧视图。
为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
根据多个实施例,可以通过将器件506耦合(例如,电、机械、操作、化学等)到器件200D来形成器件500D。例如,器件506可通过采用冷焊技术(也称为接触焊接)而(例如,电、机械、操作、化学等)耦合到器件200D。在此实例中,基于实施此冷焊技术,可将器件506的凸块下金属化部件508插入并耦合到焊料凸块122,借此促进器件500D的形成以及将凸块下金属化部件508耦合(例如,电、机械、操作、化学等)到凸块下金属化部件204A。
在一些实施例中,器件500D可以包括倒装芯片器件。例如,器件500D可以包括倒装芯片器件,该倒装芯片器件包括一个或多个气密密封的超导互连部件(例如,第二超导层106、第三超导层108、焊料凸块122等)和/或一个或多个机械互连部件(例如,焊料扩散层110、焊料润湿层112、金属间化合物层120、焊料凸块122等)。
图6A示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件600A的截面侧视图。
为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
根据多个实施例,器件600A可以包括器件602和图2D的器件200D。在一些实施例中,器件602可以包括图1B的器件100B、图2B的器件200B和/或图3A的器件300A的替代示例实施例。在一些实施例中,器件602可包括凸块下金属化部件604,其可包括以上参照图2B描述的器件200B的凸块下金属化部件204A的替代示例实施例。在一些实施例中,器件602和/或凸块下金属化部件604可以包括柱形凸块606。
根据多个实施例,柱形凸块606可以包括导电材料。例如,柱形凸块606可以包括金(Au)和/或另一种导电材料。在一些实施例中,可以通过采用例如改进的导线接合工艺或使用导线接合器的柱形凸块工艺(也称为柱形凸块接合)在焊料润湿层112上形成柱形凸块606。
在一些实施例中,凸块下金属化部件604可以(例如,电、机械、操作、化学等)耦合到凸块下金属化部件204B。例如,为了促进将凸块下金属化部件604耦合到凸块下金属化部件204B,器件602可以耦合(例如,电、机械、操作、化学等)到器件200D以形成器件600B(例如,如下面参考图6B所描述的)。
图6B示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件600B的截面侧视图。
为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
根据多个实施例,可以通过将器件602耦合(例如,电、机械、操作、化学等)到器件200D来形成器件600B。例如,器件602可以通过采用冷焊技术(也称为接触焊接)而(例如,电、机械、操作、化学等)耦合到器件200D。在此实例中,基于实施此冷焊技术,装置602的凸块下金属化部件604可插入且耦合到焊料凸块122,借此促进器件600B的形成及将凸块下金属化部件604耦合(例如,电、机械、操作、化学等)到凸块下金属化部件204A。应当理解,柱形凸块606可以在器件602冷焊到器件200D期间用作支座,并且可以进一步促进器件602到器件200D的改进的机械耦合。
在一些实施例中,器件600B可以包括倒装芯片器件。例如,器件600B可以包括倒装芯片器件,该倒装芯片器件包括一个或多个气密密封的超导互连部件(例如,第二超导层106、第三超导层108、焊料凸块122等)和/或一个或多个机械互连部件(例如,焊料扩散层110、焊料润湿层112、金属间化合物层120、焊料凸块122、柱形凸块606等)。
图7A示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件700A的截面侧视图。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
根据多个实施例,设备700A可以包括设备702和图2D的设备200D。在一些实施例中,设备702可以包括图1B的设备100B、图2B的设备200B和/或图3A的设备300A的替代示例实施例。在一些实施例中,器件702可包括凸块下金属化部件704,其可包括以上参照图2B描述的器件200B的凸块下金属化部件204A的替代示例实施例。在一些实施例中,器件702和/或凸块下金属化部件704可以包括电镀基座706。
根据多个实施例,电镀基座706可包括导电材料。例如,电镀基座706可以包括铜(Cu)和/或另一种导电材料。在一些实施例中,可以通过采用例如电镀工艺在焊料润湿层112上形成电镀基座706。
在一些实施例中,凸块下金属化部件704可以(例如,电、机械、操作、化学等)耦合到凸块下金属化部件204B。例如,为了促进将凸块下金属化部件704耦合到凸块下金属化部件204B,器件702可以耦合(例如,电、机械、操作、化学等)到器件200D以形成器件700B(例如,如下面参考图7B所描述的)。
图7B示出了根据本文所述的一个或多个实施例的促进混合凸块下金属化部件的示例非限制性器件700B的截面侧视图。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
根据多个实施例,可以通过将器件702耦合(例如,电、机械、操作、化学等)到器件200D来形成器件700B。例如,器件702可以通过采用冷焊技术(也称为接触焊接)而(例如,电、机械、操作、化学等)耦合到器件200D。在此实例中,基于实施此冷焊技术,可将器件702的凸块下金属化部件704插入并耦合到焊料凸块122,借此促进器件700B的形成及将凸块下金属化部件704耦合(例如,电、机械、操作、化学等)到凸块下金属化部件204A。应当理解,电镀基座706可以在器件702冷焊到器件200D期间用作隔离物,并且可以进一步促进器件702到器件200D的改进的机械耦合。
在一些实施例中,器件700B可以包括倒装芯片器件。例如,器件700B可以包括倒装芯片器件,该倒装芯片器件包括一个或多个气密密封的超导互连部件(例如,第二超导层106、第三超导层108、焊料凸块122等)和/或一个或多个机械互连部件(例如,焊料扩散层110、焊料润湿层112、金属间化合物层120、焊料凸块122、电镀基座706等)。图8示出了根据本文所述的一个或多个实施例的促进实现混合凸块下金属化部件的示例非限制性方法800的流程图。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
在一些实施例中,方法800可由计算系统(例如,图10中所示并在以下描述的操作环境1000)和/或计算设备(例如,图10中所示并在以下描述的计算机1012)来实现。在非限制性示例实施例中,这样的计算系统(例如,操作环境1000)和/或这样的计算设备(例如,计算机1012)可以包括一个或多个处理器和可以在其上存储可执行指令的一个或多个存储器设备,当由一个或多个处理器执行时,可执行指令可以促进本文描述的操作的执行,包括图8中图示的方法800的非限制性操作。作为非限制性示例,一个或多个处理器可以通过引导或控制可操作以执行半导体制造的一个或多个系统和/或设备来促进执行本文描述的操作,例如方法800。
在802处,在凸块下金属化部件(例如,凸块下金属化部件124A、凸块下金属化部件124B、凸块下金属化部件204A和/或凸块下金属化部件204B)上沉积(例如,经由计算机1012)焊料(例如,注入熔融焊料(IMS)和/或焊料凸块122)。
在804,基于沉积在凸块下金属化部件上形成(例如,经由计算机1012)超导互连部件(例如,第二超导层106、第三超导层108和/或焊料凸块122)和金属间化合物层(例如,金属间化合物层120)。
在一些实施例中,这种沉积操作802和形成操作804可以通过采用以上参考图1A-1D和/或图2A-2D描述的一个或多个集成电路制造技术来执行(例如,经由计算机1012)。应当理解,这种沉积操作802和形成操作804可以促进超导互连部件(例如,经由焊料凸块122)的气密密封,这可以防止在超导互连部件(例如,第二超导层106、第三超导层108等)和另一导电部件(例如,焊料凸块122)之间形成氧化物(例如,氧化),从而促进这些部件的改进的电耦合。还应了解,这种沉积操作802和形成操作804可促进凸块下金属化部件(例如,凸块下金属化部件124A、凸块下金属化部件124B、凸块下金属化部件204A和/或凸块下金属化部件204B)的机械完整性的改进,以及凸块下金属化部件到焊料凸块122的机械连接的强度的改进。还应当理解,上述这种气密密封、改进的电耦合、改进的机械完整性和改进的机械互连可以是本公开优于现有技术的优点。
图9示出了根据本文所述的一个或多个实施例的促进实现混合凸块下金属化部件的示例非限制性方法900的流程图。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
在一些实施例中,方法900可以由计算系统(例如,图10中所示并在下面描述的操作环境1000)和/或计算设备(例如,图10中所示并在下面描述的计算机1012)来实现。在非限制性示例实施例中,这样的计算系统(例如,操作环境1000)和/或这样的计算设备(例如,计算机1012)可以包括一个或多个处理器和可以在其上存储可执行指令的一个或多个存储器设备,当由一个或多个处理器执行时,可执行指令可以促进本文描述的操作的执行,包括图9中图示的方法900的非限制性操作。作为非限制性示例,一个或多个处理器可以通过引导或控制可操作以执行半导体制造的一个或多个系统和/或设备来促进执行本文描述的操作,例如方法900。
在902,将第一凸块下金属化部件(例如,凸块下金属化部件404A、凸块下金属化部件404B、凸块下金属化部件504、凸块下金属化部件508、凸块下金属化部件604和/或凸块下金属化部件704)耦合(例如,经由计算机1012)到包括超导互连部件(例如,第二超导层106、第三超导层108和/或焊料凸块122)和金属间化合物层(例如,金属间化合物层120)的第二凸块下金属化部件(例如,凸块下金属化部件124B和/或凸块下金属化部件204B)。
在904,基于该耦合在第一凸块下金属化部件上形成(例如,经由计算机1012)气密密封的超导互连部件(例如,由焊料凸块122气密密封的第二超导层106和/或第三超导层108)。
在一些实施例中,这种耦合操作902和形成操作904可以通过采用以上参考图4A和4B、图5A-5D、图6A和6B和/或图7A和7B描述的一种或多种集成电路制造技术(例如,回流焊接、冷焊等)来执行(例如,经由计算机1012)。应当理解,这种耦合操作902和形成操作904可以提供包括一个或多个气密密封的超导互连部件(例如,由焊料凸块122气密密封的第二超导层106和/或第三超导层108)的倒装芯片设备,其可以防止气密密封的超导互连部件(例如,第二超导层106、第三超导层108等)和另一导电部件(例如,焊料凸块122)之间的氧化物形成(例如,氧化),从而促进这样的部件的改进的电耦合。还应了解,这种耦合操作902和形成操作904可提供倒装芯片器件,所述倒装芯片器件具有此倒装芯片器件的各种部件之间(例如,第一凸块下金属化部件与焊料凸块122之间、第二凸块下金属化部件与焊料凸块122之间等)的改进的机械完整性及改进的机械连接强度。还应当理解,上述这种气密密封、改进的电耦合、改进的机械完整性和改进的机械互连可以是本公开优于现有技术的优点。
为了解释的简单起见,本文描述的方法(例如,计算机实现的方法)被描绘和描述为一系列动作。可以理解和明白,本发明不受所示动作和/或动作次序的限制,例如,动作可以按各种次序和/或并发地发生,并且可以与本文未呈现和描述的其它动作一起发生。此外,根据所公开的主题,并非所有示出的动作都是实现本文所描述的方法(例如,计算机实现的方法)所必需的。此外,本领域技术人员将理解和明白,这样的方法可以经由状态图或事件而被替换地表示为一系列相互关联的状态。另外,还应当理解,下文中以及本说明书通篇公开的方法(例如,计算机实现的方法)能够被存储在制品上,以促进将这些方法(例如,计算机实现的方法)传输和转移到计算机。如本文所使用的术语制品旨在涵盖可从任何计算机可读设备或存储介质访问的计算机程序。
为了提供所公开的主题的各个方面的上下文,图10以及以下讨论旨在提供对其中可实现所公开的主题的各个方面的合适环境的一般描述。图10示出了其中可促进此处所描述的一个或多个实施例的示例、非限制性操作环境的框图。例如,操作环境1000可用于实现图8的示例非限制性方法800和/或图9的非限制性方法900,这两者都促进实现本文描述的主题公开的各种实施例。为了简洁,省略了在这里描述的其它实施例中采用的类似元件的重复描述。
参考图10,用于实现本公开的各方面的合适的操作环境1000还可包括计算机1012。计算机1012还可以包括处理单元1014、系统存储器1016和系统总线1018。系统总线1018将包括但不限于系统存储器1016的系统组件耦合到处理单元1014。处理单元1014可以是各种可用处理器中的任一种。双微处理器和其它多处理器体系结构也可用作处理单元1014。系统总线1018可以是若干类型的总线结构中的任何一种,包括存储器总线或存储器控制器、外围总线或外部总线、和/或使用任何各种可用总线体系结构的局部总线,这些总线体系结构包括但不限于工业标准体系结构(ISA)、微沟道体系结构(MSA)、扩展ISA(EISA)、智能驱动电子设备(IDE)、VESA局部总线(VLB)、外围部件互连(PCI)、卡总线、通用串行总线(USB)、高级图形端口(AGP)、火线(IEEE 1394)、和小型计算机系统接口(SCSI)。
系统存储器1016还可以包括易失性存储器1020和非易失性存储器1022。基本输入/输出系统(BIOS)包含诸如在启动期间在计算机1012内的元件之间传输信息的基本例程,它被存储在非易失性存储器1022中。计算机1012还可包括可移动/不可移动、易失性/非易失性计算机存储介质。例如,图10示出了盘存储1024。盘存储1024还可包括但不限于,诸如磁盘驱动器、软盘驱动器、磁带驱动器、Jaz驱动器、Zip驱动器、LS-100驱动器、闪存卡、或记忆棒等设备。盘存储1024还可以包括单独的存储介质或与其他存储介质组合的存储介质。为了促进将盘存储1024连接到系统总线1018,通常使用诸如接口1026等可移动或不可移动接口。图10还描绘了充当用户和在合适的操作环境1000中描述的基本计算机资源之间的中介的软件。这样的软件还可以包括例如操作系统1028。可存储在盘存储1024上的操作系统1028用于控制和分配计算机1012的资源。
系统应用程序1030利用操作系统1028通过例如存储在系统存储器1016或盘存储1024上的程序模块1032和程序数据1034对资源的管理。应当理解,本公开可以用各种操作系统或操作系统的组合来实现。用户通过输入设备1036把命令或信息输入到计算机1012中。输入设备1036包括但不限于诸如鼠标、跟踪球、指示笔、触摸垫等定点设备、键盘、话筒、操纵杆、游戏手柄、圆盘式卫星天线、扫描仪、TV调谐卡、数码相机、数码摄像机、web摄像头等等。这些和其它输入设备通过系统总线1018经由接口端口1038连接到处理单元1014。接口端口1038包括,例如,串行端口、并行端口、游戏端口、以及通用串行总线(USB)。(一个或多个)输出设备1040使用与(一个或多个)输入设备1036相同类型的端口中的一些端口。因此,例如,USB端口可用于向计算机1012提供输入,并从计算机1012向输出设备1040输出信息。提供输出适配器1042来说明存在某些输出设备1040,如监视器、扬声器和打印机,以及其它输出设备1040,它们需要专用适配器。作为示例而非限制,输出适配器1042包括提供输出设备1040和系统总线1018之间的连接手段的显卡和声卡。应当注意,其它设备和/或设备的系统提供输入和输出能力,诸如远程计算机1044。
计算机1012可使用至一个或多个远程计算机,诸如远程计算机1044的逻辑连接在网络化环境中操作。远程计算机1044可以是计算机、服务器、路由器、网络PC、工作站、基于微处理器的电器、对等设备或其它常见的网络节点等,且通常还可包括相对于计算机1012所描述的许多或所有元件。为了简洁起见,仅存储器存储设备1046与远程计算机1044一起示出。远程计算机1044通过网络接口1048被逻辑地连接到计算机1012,然后经由通信连接1050被物理地连接。网络接口1048包括有线和/或无线通信网络,例如局域网(LAN)、广域网(WAN)、蜂窝网络等。LAN技术包括光纤分布式数据接口(FDDI)、铜线分布式数据接口(CDDI)、以太网、令牌环等。WAN技术包括,但不限于,点对点链路、像综合业务数字网(ISDN)及其变体那样的电路交换网络、分组交换网络、以及数字用户线(DSL)。通信连接1050是指用于将网络接口1048连接到系统总线1018的硬件/软件。虽然为了清楚地说明,通信连接1050被示为在计算机1012内部,但是它也可以在计算机1012外部。仅出于示例性目的,用于连接到网络接口1048的硬件/软件还可以包括内部和外部技术,诸如包括常规电话级调制解调器、电缆调制解调器和DSL调制解调器的调制解调器、ISDN适配器和以太网卡。
本发明可以是任何可能的技术细节集成水平的系统、方法、装置和/或计算机程序产品。计算机程序产品可以包括其上具有计算机可读程序指令的计算机可读存储介质(或多个介质),所述计算机可读程序指令用于使处理器执行本发明的各方面。计算机可读存储介质可以是能够保留和存储由指令执行设备使用的指令的有形设备。计算机可读存储介质可以是例如但不限于电子存储设备、磁存储设备、光存储设备、电磁存储设备、半导体存储设备或前述的任何合适的组合。计算机可读存储介质的更具体示例的非穷举列表还可以包括以下:便携式计算机磁盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM或闪存)、静态随机存取存储器(SRAM)、便携式光盘只读存储器(CD-ROM)、数字多功能盘(DVD)、记忆棒、软盘、诸如上面记录有指令的打孔卡或凹槽中的凸起结构的机械编码装置,以及上述的任何适当组合。如本文所使用的计算机可读存储介质不应被解释为暂时性信号本身,诸如无线电波或其他自由传播的电磁波、通过波导或其他传输介质传播的电磁波(例如,通过光纤线缆的光脉冲)、或通过导线传输的电信号。本文描述的计算机可读程序指令可以从计算机可读存储介质下载到相应的计算/处理设备,或者经由网络,例如因特网、局域网、广域网和/或无线网络,下载到外部计算机或外部存储设备。网络可以包括铜传输电缆、光传输光纤、无线传输、路由器、防火墙、交换机、网关计算机和/或边缘服务器。每个计算/处理设备中的网络适配卡或网络接口从网络接收计算机可读程序指令,并转发计算机可读程序指令以存储在相应计算/处理设备内的计算机可读存储介质中。用于执行本发明的操作的计算机可读程序指令可以是汇编指令、指令集架构(ISA)指令、机器相关指令、微代码、固件指令、状态设置数据、集成电路的配置数据,或者以一种或多种编程语言(包括面向对象的编程语言,例如Smalltalk、C++等)和过程编程语言(例如“C”编程语言或类似的编程语言)的任何组合编写的源代码或目标代码。计算机可读程序指令可以完全在用户的计算机上执行,部分在用户的计算机上执行,作为独立的软件包执行,部分在用户的计算机上并且部分在远程计算机上执行,或者完全在远程计算机或服务器上执行。在后一种情况下,远程计算机可以通过任何类型的网络连接到用户的计算机,包括局域网(LAN)或广域网(WAN),或者可以连接到外部计算机(例如,使用因特网服务提供商通过因特网)。在一些实施例中,为了执行本发明的各方面,包括例如可编程逻辑电路、现场可编程门阵列(FPGA)或可编程逻辑阵列(PLA)的电子电路可以通过利用计算机可读程序指令的状态信息来执行计算机可读程序指令以使电子电路个性化。
在此参考根据本发明实施例的方法、装置(系统)和计算机程序产品的流程图和/或框图描述本发明的各方面。将理解,流程图和/或框图的每个框以及流程图和/或框图中的框的组合可以由计算机可读程序指令来实现。这些计算机可读程序指令可以被提供给通用计算机、专用计算机或其他可编程数据处理装置的处理器以产生机器,使得经由计算机或其他可编程数据处理装置的处理器执行的指令创建用于实现流程图和/或框图的一个或多个框中指定的功能/动作的装置。这些计算机可读程序指令还可以存储在计算机可读存储介质中,其可以引导计算机、可编程数据处理装置和/或其他设备以特定方式工作,使得其中存储有指令的计算机可读存储介质包括制品,该制品包括实现流程图和/或框图的一个或多个框中指定的功能/动作的各方面的指令。计算机可读程序指令还可以被加载到计算机、其他可编程数据处理装置或其他设备上,以使得在计算机、其他可编程装置或其他设备上执行一系列操作动作,以产生计算机实现的过程,使得在计算机、其他可编程装置或其他设备上执行的指令实现流程图和/或框图的一个或多个框中指定的功能/动作。
附图中的流程图和框图示出了根据本发明的各种实施例的系统、方法和计算机程序产品的可能实现的架构、功能和操作。在这点上,流程图或框图中的每个框可以表示指令的模块、段或部分,其包括用于实现指定的逻辑功能的一个或多个可执行指令。在一些替代实施方案中,框中所注明的功能可不按图中所注明的次序发生。例如,连续示出的两个框实际上可以基本上同时执行,或者这些框有时可以以相反的顺序执行,这取决于所涉及的功能。还将注意,框图和/或流程图图示的每个框以及框图和/或流程图图示中的框的组合可以由执行指定功能或动作或执行专用硬件和计算机指令的组合的专用的基于硬件的系统来实现。
尽管以上在运行在一个和/或多个计算机上的计算机程序产品的计算机可执行指令的一般上下文中描述了本主题,但是本领域的技术人员将认识到,本公开也可以结合其它程序模块来实现或可以结合其它程序模块来实现。通常,程序模块包括执行特定任务和/或实现特定抽象数据类型的例程、程序、组件、数据结构等。此外,本领域的技术人员可以理解,本发明的计算机实现的方法可以用其它计算机系统配置来实施,包括单处理器或多处理器计算机系统、小型计算设备、大型计算机、以及计算机、手持式计算设备(例如,PDA、电话)、基于微处理器的或可编程的消费或工业电子产品等。所示的各方面也可以在其中任务由通过通信网络链接的远程处理设备执行的分布式计算环境中实践。然而,本公开的一些方面,如果不是所有方面,可以在独立计算机上实践。在分布式计算环境中,程序模块可以位于本地和远程存储器存储设备中。
如本申请中所使用的,术语“组件”、“系统”、“平台”、“接口”等可以指代和/或可以包括计算机相关的实体或与具有一个或多个特定功能的操作机器相关的实体。这里公开的实体可以是硬件、硬件和软件的组合、软件、或执行中的软件。例如,组件可以是,但不限于,在处理器上运行的进程、处理器、对象、可执行文件、执行线程、程序和/或计算机。作为说明,在服务器上运行的应用程序和服务器都可以是组件。一个或多个组件可以驻留在进程和/或执行的线程内,并且组件可以位于一个计算机上和/或分布在两个或更多计算机之间。在另一示例中,相应组件可从其上存储有各种数据结构的各种计算机可读介质执行。这些组件可以经由本地和/或远程进程进行通信,例如根据具有一个或多个数据分组的信号(例如,来自一个组件的数据,该组件经由该信号与本地系统、分布式系统中的另一个组件进行交互和/或通过诸如因特网之类的网络与其它系统进行交互)。作为另一个示例,组件可以是具有由电气或电子电路操作的机械部件提供的特定功能的装置,该电气或电子电路由处理器执行的软件或固件应用程序操作。在这种情况下,处理器可以在装置的内部或外部,并且可以执行软件或固件应用的至少一部分。作为又一示例,组件可以是通过电子组件而不是机械部件来提供特定功能的装置,其中电子组件可以包括处理器或其他装置以执行至少部分地赋予电子组件的功能的软件或固件。在一方面,组件可经由虚拟机来仿真电子组件,例如在云计算系统内。
此外,术语“或”旨在表示包含性的“或”而不是排他性的“或”。也就是说,除非另外指定,或者从上下文中清楚,否则“X采用A或B”旨在表示任何自然的包含性排列。也就是说,如果X采用A;X采用B;或者X采用A和B两者,则在任何前述实例下都满足“X采用A或B”。此外,除非另外指定或从上下文中清楚是指单数形式,否则如在本说明书和附图中使用的冠词“一”和“一个”一般应被解释为表示“一个或多个”。如本文所使用的,术语“示例”和/或“示例性的”用于表示用作示例、实例或说明。为了避免疑惑,本文公开的主题不受这些示例限制。此外,本文中描述为“示例”和/或“示例性”的任何方面或设计不一定被解释为比其它方面或设计优选或有利,也不意味着排除本领域普通技术人员已知的等效示例性结构和技术。
如在本说明书中所采用的,术语“处理器”可以指基本上任何计算处理单元或设备,包括但不限于单核处理器;具有软件多线程执行能力的单处理器;多核处理器;具有软件多线程执行能力的多核处理器;具有硬件多线程技术的多核处理器;平行平台;以及具有分布式共享存储器的并行平台。另外,处理器可以指被设计为执行本文描述的功能的集成电路、专用集成电路(ASIC)、数字信号处理器(DSP)、现场可编程门阵列(FPGA)、可编程逻辑控制器(PLC)、复杂可编程逻辑器件(CPLD)、分立门或晶体管逻辑、分立硬件组件或其任意组合。此外,处理器可以采用纳米级架构,例如但不限于基于分子和量子点的晶体管、开关和门,以便优化空间使用或增强用户设备的性能。处理器也可以实现为计算处理单元的组合。在本公开中,诸如“存储”、“存储器”、“数据存储”、“数据存储器”、“数据库”以及与组件的操作和功能相关的基本上任何其他信息存储组件之类的术语被用来指代“存储器组件”、在“存储器”中体现的实体或包括存储器的组件。应了解,本文所描述的存储器和/或存储器组件可为易失性存储器或非易失性存储器,或可包括易失性和非易失性存储器两者。作为说明而非限制,非易失性存储器可包括只读存储器(ROM)、可编程ROM(PROM)、电可编程ROM(EPROM)、电可擦除ROM(EEPROM)、闪存或非易失性随机存取存储器(RAM)(例如,铁电RAM(FeRAM),易失性存储器可包括RAM,RAM可用作外部高速缓存存储器,例如作为说明而非限制,RAM可以许多形式获得,诸如同步RAM(SRAM)、动态RAM(DRAM)、同步DRAM(SDRAM)、双倍数据率(DDR SDRAM)、增强型SDRAM(ESDRAM)、同步链路DRAM(SLDRAM)、直接Rambus RAM(DRRAM)、直接Rambus动态RAM(DRDRAM)和Rambus动态RAM(RDRAM)。另外,这里所公开的系统或计算机实现的方法的存储器组件意图包括而不限于这些以及任何其他合适类型的存储器。
以上描述的内容仅包括系统和计算机实现的方法的示例。当然,不可能为了描述本公开而描述组件或计算机实现的方法的每个可想到的组合,但是本领域的普通技术人员可以认识到,本公开的许多进一步的组合和置换是可能的。此外,就在详细描述、权利要求书、附录和附图中使用术语“包括”、“具有”、“拥有”等来说,这些术语旨在以与术语“包含”在权利要求书中用作过渡词时所解释的类似的方式为包含性的。
已经出于说明的目的呈现了对各种实施例的描述,但是不旨在是穷举的或限于所公开的实施例。在不背离所描述的实施例的范围的情况下,许多修改和变化对于本领域的普通技术人员将是显而易见的。选择本文所使用的术语以最好地解释实施例的原理、实际应用或对市场上存在的技术改进,或使本领域的其他普通技术人员能够理解本文所公开的实施例。
Claims (25)
1.一种器件,包括:
包括超导互连部件和焊料润湿部件的凸块下金属化部件;以及
焊料凸块,所述焊料凸块耦合到所述超导互连部件和所述焊料润湿部件。
2.根据权利要求1所述的器件,其中,所述焊料润湿部件包围所述超导互连部件。
3.根据前述权利要求中任一项所述的器件,其中所述焊料润湿部件包括与焊料反应以形成金属间化合物层的材料,从而促进所述焊料凸块与所述凸块下金属化部件的改进的机械耦合。
4.根据前述权利要求中任一项所述的器件,其中所述超导互连部件包括气密密封的超导互连部件。
5.根据前述权利要求中任一项所述的器件,其中所述凸块下金属化部件耦合到至少一个超导层,所述至少一个超导层耦合到衬底。
6.根据前述权利要求中任一项所述的器件,其中,所述焊料凸块包括至少一种超导材料。
7.一种方法,包括:
在凸块下金属化部件上沉积焊料;以及
基于所述沉积,在所述凸块下金属化部件上形成超导互连部件和金属间化合物层。
8.根据权利要求7所述的方法,还包括基于所述沉积在所述凸块下金属化部件上形成气密密封的超导互连部件,从而促进所述焊料与所述凸块下金属化部件的改进的电耦合。
9.根据权利要求7或8所述的方法,其中,所述沉积包括在所述凸块下金属化部件的超导层和焊料润湿层上沉积焊料。
10.根据权利要求7至9中任一项所述的方法,其中,所述沉积包括将熔融焊料注入到所述凸块下金属化部件上。
11.根据权利要求7至10中任一项所述的方法,还包括将所述焊料电耦合或机械耦合至所述凸块下金属化部件中的至少一种。
12.根据权利要求7至11中任一项所述的方法,还包括将所述凸块下金属化部件耦合到至少一个超导层,所述至少一个超导层耦合到衬底。
13.一种器件,包括:
具有超导层和金属间化合物层的衬底;以及
焊料凸块,其耦合到所述超导层和所述金属间化合物层。
14.根据权利要求13所述的器件,其中,所述超导层由所述金属间化合物层或所述焊料凸块中的至少一个气密密封。
15.根据权利要求13或14所述的器件,还包括焊料润湿层,所述焊料润湿层耦合到所述金属间化合物层和所述超导层,从而促进所述焊料凸块与所述超导层的改进的机械耦合或改进的电耦合中的至少一个。
16.一种器件,包括:
第一凸块下金属化部件,其包括超导互连部件和金属间化合物层;以及
焊料凸块,其耦合到所述超导互连部件、所述金属间化合物层及第二凸块下金属化部件。
17.根据权利要求16所述的器件,其中,所述焊料凸块耦合到所述第二凸块下金属化部件的第二超导互连部件。
18.如权利要求16或17所述的器件,其特征在于,所述超导互连部件包括气密密封的超导互连部件。
19.根据权利要求16至18中任一项所述的器件,还包括机械互连部件,所述机械互连部件耦合到所述第一凸块下金属化部件和所述第二凸块下金属化部件,所述机械互连部件包括柱形凸块或电镀基座中的至少一个。
20.一种方法,包括:
将第一凸块下金属化部件耦合到包括超导互连部件和金属间化合物层的第二凸块下金属化部件;以及
基于所述耦合在所述第一凸块下金属化部件上形成气密密封的超导互连部件。
21.根据权利要求20所述的方法,还包括将所述第一凸块下金属化部件电耦合或机械耦合到所述第二凸块下金属化部件中的至少一种。
22.根据权利要求20或21中任一项所述的方法,还包括在所述第一凸块下金属化部件上形成柱形凸块。
23.根据权利要求20至22中任一项所述的方法,还包括在所述第一凸块下金属化部件上形成镀柱。
24.根据权利要求20至23中任一项所述的方法,其中,所述耦合包括将所述第一凸块下金属化部件冷焊到所述第二凸块下金属化部件。
25.根据权利要求20至24中任一项所述的方法,其中,所述耦合包括将所述第一凸块下金属化部件回流焊接至所述第二凸块下金属化部件。
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US16/136,808 US10937735B2 (en) | 2018-09-20 | 2018-09-20 | Hybrid under-bump metallization component |
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US (2) | US10937735B2 (zh) |
EP (1) | EP3853914B1 (zh) |
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CN105591016A (zh) * | 2014-11-10 | 2016-05-18 | 三星电子株式会社 | 互连凸块、半导体器件、半导体器件封装件和照明设备 |
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WO2023056701A1 (zh) * | 2021-10-08 | 2023-04-13 | 腾讯科技(深圳)有限公司 | 量子比特组件、量子比特组件制备方法、芯片及设备 |
US11917927B2 (en) | 2021-10-08 | 2024-02-27 | Tencent Technology (Shenzhen) Company Limited | Qubit assembly, qubit assembly preparation method, chip, and device |
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JP2022501808A (ja) | 2022-01-06 |
WO2020058370A1 (en) | 2020-03-26 |
JP2024054259A (ja) | 2024-04-16 |
CN112585772B (zh) | 2024-04-23 |
JP7536000B2 (ja) | 2024-08-19 |
EP3853914A1 (en) | 2021-07-28 |
US11749605B2 (en) | 2023-09-05 |
EP3853914B1 (en) | 2024-05-01 |
US20200098695A1 (en) | 2020-03-26 |
US10937735B2 (en) | 2021-03-02 |
US20210118808A1 (en) | 2021-04-22 |
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