CN1930672A - 允许使用高含锡量焊块的凸块下金属化层 - Google Patents
允许使用高含锡量焊块的凸块下金属化层 Download PDFInfo
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- CN1930672A CN1930672A CNA200580006974XA CN200580006974A CN1930672A CN 1930672 A CN1930672 A CN 1930672A CN A200580006974X A CNA200580006974X A CN A200580006974XA CN 200580006974 A CN200580006974 A CN 200580006974A CN 1930672 A CN1930672 A CN 1930672A
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Abstract
制造包括邻接导电焊盘的粘附层、邻接粘附层的含钼阻挡层、邻接含钼阻挡层的润湿层以及邻接润湿层的高含锡量焊接材料的凸块下金属化结构的装置和方法。可将润湿层基本包含于高含锡量焊料中以形成金属间复合层。含钼阻挡层防止高含锡量焊接材料中的锡的移动向邻接导电焊盘的电介质层迁移并可能引起分层和/或腐蚀任何底层结构,尤其是可能存在的铜结构。
Description
发明背景
发明领域:本发明涉及微电子器件加工,尤其涉及允许使用纯锡或高含锡量倒装芯片凸块的凸块下金属化层。
现有技术:微电子器件产业持续看到在允许增加的电路密度和复杂性的技术方面的巨大进步,以及在功耗和封装尺寸方面同样引人注目的降低。现在,目前的半导体技术允许具有数百万个晶体管的、以数十(或者甚至数百)MIPS(每秒百万条指令)的速度工作的单芯片微处理器被封装在相对较小的、经空气冷却的微电子器件封装中。微电子器件的这一高密度和高功能的结果已成为对微电子管芯外部存在日益增多的外部电连接以将微电子管芯连接到诸如内插器等其它部件。
用于这种高密度连接的连接机制一般是球栅阵列(BGA),因为阵列的球或凸块的尺寸能制作得比较小以提供其较高的密度,从而从微电子管芯上形成较大数量的连接。BGA是通过在微电子管芯焊盘上放置一定量的焊料并将焊料加热到熔点来形成的。与液体焊料相关联的表面张力使焊料形成焊球。焊球在其冷却时保持其形状以形成固体焊球或凸块。
如图8所示,一个示例性微电子封装包括安装到诸如内插器、母板等的衬底404的微电子管芯402,衬底通过导电路径(未示出)的层次将微电子管芯402在功能上连接到其它电子部件(未示出)。所示的用于将微电子管芯402电子地安装到衬底404的方法被称为倒装芯片键合。在这种安装方法中,使用焊块或焊球416将微电子管芯402的有源表面408上的导电端子或焊盘406直接附连到衬底404的表面414上对应的接点412,焊块或焊球416被回流以形成上述两者之间的附连。
最常用于形成焊块多的材料是铅/锡合金。然而,政府要求用于形成凸块所使用的焊料是无铅的,当然这是因为已知铅对人类是有毒的。因此,已经有了从凸块加工中去除铅的进展。当前,基本纯锡或诸如锡/铋合金、低共熔锡/银、三元锡/银/铜、低共熔锡/铜等的高含锡量合金(90%或更多的锡)是用于无铅焊块的最合适的材料。基本纯锡或高含锡量合金形成于沉积在微电子管芯焊盘406上的凸块下金属化层(UBM)(未示出)上。UBM提供了微电子管芯焊盘406和焊块416之间的可靠的电和机械接口。用于含铜的微电子管芯焊盘和铅/锡焊球的典型的UBM包括三层:用于附连到微电子焊盘的粘附层、粘附层之上用于防止焊球和微电子管芯之间的污染的阻挡层、以及阻挡层和焊块之间用于“润湿”或粘附到焊块材料的润湿层。粘附层可包括钛、镍钒合金等。阻挡层可包括铬、氮化钛等。润湿层通常是镍、铜、钴、金或其合金。
然而,如本领域的技术人员将理解的,使用纯锡或高含锡量合金是有问题的,因为锡易于与通常在铅/锡凸块工艺中使用的凸块下金属化叠层反应,并且在回流过程中过度的反应导致凸块-衬底分层和/或腐蚀下面的铜结构(焊盘和迹线)。
当前用于解决锡-凸块下金属化层反应问题的方法是使润湿层非常厚(例如,>5μm厚的镍润湿层),使得微电子封装在制造期间以及使用期间必须承受的随后热应力期间润湿层不被全部消耗。然而,这种方法与机械上易碎、低介电常数(低k)的层间电介质(ILD)材料(即,介电常数低于二氧化硅的电介质材料)不兼容,因为封装引起的应力被传递到凸块底部的硬的、厚的镍材料,并且随后被引导到微电子管芯。然后,应力导致低k ILD粘着失效和/或低k ILD-刻蚀停止层(etchstop)的粘合失效。
这种与低k ILD材料的不兼容性是一个重大的问题,因为由于集成电路已经变得越来越小,在其加工中使用低k ILD材料以获得互连之间的低电容已经变得必需。减小互连之间的这一电容导致几个优点,包括减小的RC延迟、减小的功率耗散和互连之间减小的串扰。
因此,有利的是开发用于形成防止锡污染的凸块下金属化结构的装置和技术,该凸块下金属化结构不会将非常大的应力转移到邻接凸块下金属化层的结构。
附图简述
尽管说明书以具体指出和清楚要求保护被视为本发明的权利要求书来结束,但当结合附图阅读时能够更容易地从本发明的以下描述中确定本发明的优点,附图中:
图1是根据本发明的金属化层的侧横截面图;
图2是根据本发明的金属化层的横截面扫描电子显微照片;
图3是根据本发明的焊料回流后的图1的金属化层的侧横截面图;
图4是根据本发明的用于在微电子管芯上制造凸块下金属化和焊料的工艺的流程图;
图5是根据本发明的附连到衬底的微电子管芯的侧视图;
图6是根据本发明的具有集成于其中的微电子组件的手持式设备的斜视图;
图7是根据本发明的具有集成于其中的微电子组件的计算机系统的斜视图;以及
图8是本领域中已知的附连到衬底的微电子管芯的侧视图。
所示实施例的详细描述
在以下详细描述中对附图进行参考,附图作为说明示出了可实施本发明的具体实施例。足够详细地描述了这些实施例以使本领域的技术人员能够实施本发明。
将会理解,本发明的各种实施例尽管是不同的,但未必是互斥的。例如,这里结合一个实施例所描述的特定特征、结构或特性可在其它实施例中实现而不背离本发明的精神和范围。此外,将理解,每个公开的实施例中的个别元件的位置或布置可被修改而不背离本发明的精神和范围。因此,以下详细描述不应在限制的意义上理解,并且本发明的范围仅由适当解释的所附权利要求书来连同授权的全范围的等效技术方案一起来定义。在附图中,同样的标号在所有几个图中指的是相同的或类似的功能。
图1示出倒装芯片组件100,包括导电焊盘102上形成的凸块下金属化结构120。在互连结构104中或上制造导电焊盘102。导电焊盘102能用任何适当的导电材料制成,包括但不限于铜、铝及其合金。互连结构104可以是微电子管芯(未示出)上制造的多个层间电介质层,被示出为元件106a、106b和106c。层间电介质层106a、106b和106c可由任何适当的电介质材料制成,包括但不限于氧化硅、氮化硅等,以及诸如掺杂碳的氧化物等低k电介质。
导电焊盘102经由导电通孔112连接到导电迹线108。如本领域的技术人员将理解的,导电迹线108的路线定为至微电子管芯(未示出)。诸如氮化硅等钝化层114沉积在互连结构104上,并且被形成图案以露出至少一部分导电焊盘102。
通过形成粘附层122、阻挡层124和润湿层126,制作凸块下金属化结构120以接触导电焊盘102。粘附层122可形成于钝化层114和导电焊盘102的一部分上。选择粘附层122以良好地粘附到导电焊盘102和钝化层114,并且粘附层122可包括但不限于钛及其合金。阻挡层124形成于粘附层122上,以限制要在凸块下金属化结构120上形成的焊块扩散到粘附层122、导电焊盘102和互连结构104,并且阻挡层124包含钼及其合金。在一个实施例中,阻挡层124包含至少约90%(原子)的钼。润湿层126形成于阻挡层124上,以在组装期间为熔化的焊块提供易于润湿的表面,用于将焊料良好地键合到阻挡层124,并且阻挡层124包括但不限于镍、金、铜、钴及其合金。粘附层122、阻挡层124和润湿层126可由本领域中已知的任何方法形成,包括但不限于通过磁控溅射的沉积、蒸镀和离子束沉积。
焊塞128形成于润湿层126上,且可包含基本纯锡或高含锡量合金,如锡/铋、低共熔锡/银、三元锡/银/铜、低共熔锡/铜等。在下文中,包含基本纯锡或高含锡量合金的焊料将被简称为“高含锡量焊料”。高含锡量焊料是至少含有约75%重量的锡的材料。在一个实施例中,焊塞128包含至少约90%重量的锡。焊塞128可通过本领域中已知的任何方法制造,包括但不限于电镀和焊膏丝网印刷。
当焊塞128随后回流时,高含锡量焊塞128与润湿层126(特别是含镍、铜、钴或金的润湿层)容易地反应,并基本被包含以形成金属间复合层132。然而,当高含锡量焊塞128中的锡接触含钼的阻挡层124时,与凸块下金属化结构120的反应几乎减慢为零。如图2所示,在锡/钼界面134上没有明显的空隙出现,且一旦润湿层126被包含,只发生含钼的阻挡层124的轻微消耗。如本领域的技术人员所理解的,本发明允许在回流期间在含钼的阻挡层和熔化的锡焊塞之间形成有限的、有粘着力的金属间复合物。金属间复合物减缓了锡向含钼的阻挡层的进一步扩散及金属间复合物的增长。因此,本发明将基本防止高含锡量焊接材料中的锡的移动向邻接导电焊盘的电介质层迁移并可能引起分层和/或腐蚀任何底层结构,尤其是可能存在的铜结构。这种独特的组合产生了金属化结构120,它与高含锡量焊料相兼容,且与诸如低k ILD等结构上脆弱的电介质层相兼容。
图3示出图1的倒装芯片组件100在焊接材料128回流后形成焊块136。
图4示出制造金属化层和焊块的方法的示意图。步骤150包括提供具有至少一个邻接的导电焊盘的至少一个层间电介质。步骤152包括在至少一个导电焊盘的至少一部分上形成粘附层。步骤154包括在粘附层的至少一部分上形成含钼阻挡层。步骤156包括在含钼阻挡层的至少一部分上形成润湿层。粘附层、阻挡层和润湿层可通过本领域中已知的任何技术来形成,包括但不限于磁控溅射(优选的)、蒸镀、沉积(诸如离子束沉积)等。步骤158包括在润湿层的至少一部分上形成高含锡量焊塞。焊塞可通过本领域中已知的任何方法形成,包括但不限于电镀或丝网印刷。步骤160包括将焊塞回流以形成焊块。
图5示出根据本发明的示例性微电子封装170,它包括安装到诸如内插板、母板等的衬底174上的微电子管芯172,衬底174通过导电路径(未示出)的层次将微电子管芯功能上连接到其它电子部件(未示出)。微电子管芯172的有源表面176上的导电焊盘102具有置于其上的凸块下金属化层120,如之前所讨论的。凸块下金属化层120利用焊块136直接附连到衬底174的表面184上的相应连接盘182,焊块136被回流以形成上述两者之间的附连。
通过本发明形成的封装可在诸如蜂窝电话或个人数据助理(PDA)等手持式设备210中使用,如图6所示。在外壳240内,手持式设备210可包括带有至少一个微电子设备组件230的外部衬底220,包括但不限于,具有至少一个如上所述的凸块下金属化层120的中央处理器(CPU)、芯片组、存储器件、ASIC等。外部衬底220可附连到各种外围设备,包括诸如键盘250等输入装置和诸如LCD显示器260等显示装置。
通过本发明形成的微电子器件组件还可在如图7所示的计算机系统310中使用。在外壳或机箱340中,计算机系统310可包括带有至少一个微电子器件组件330的外部衬底或母板320,包括但不限于具有至少一个如上所述的凸块下金属化层120的中央处理器(CPU)、芯片组、存储器件、ASIC等。外部衬底或母板320可附连到各种外围设备,包括诸如键盘350和/或鼠标360等输入装置及诸如CRT监视器370等显示装置。
如此详细描述了本发明的实施例之后,可以理解,由所附权利要求书定义的本发明不受以上描述中陈述的具体细节限制,因为其很多变化都是可能的,而不背离其精神和范围。
Claims (20)
1.一种装置,包括:
邻接导电焊盘的粘附层;
邻接所述粘附层的含钼阻挡层;
邻接所述含钼阻挡层的润湿层;以及
邻接所述润湿层的高含锡量焊接材料。
2.如权利要求1所述的装置,其特征在于,所述含钼阻挡层包含至少含约90%(原子)的钼的材料。
3.如权利要求1所述的装置,其特征在于,所述高含锡量焊接材料包含至少含约90%(重量)的锡的材料。
4.如权利要求1所述的装置,其特征在于,还包括邻接至少一层低k电介质材料的所述导电焊盘。
5.如权利要求4所述的装置,其特征在于,所述至少一层低k电介质材料包括至少一层掺杂碳的氧化物。
6.如权利要求1所述的装置,其特征在于,所述润湿层基本被包含于所述高含锡量焊接材料中,从而形成金属间复合层。
7.一种方法,包括:
提供具有至少一个邻接的导电焊盘的至少一个层间电介质;
在所述至少一个导电焊盘的至少一部分上形成粘附层;
在所述粘附层的至少一部分上形成含钼阻挡层;
在所述含钼阻挡层的至少一部分上形成润湿层;以及
在所述润湿层的至少一部分上形成高含锡量焊塞。
8.如权利要求7所述的方法,其特征在于,形成所述含钼阻挡层包括形成至少含约90%(原子)的钼的含钼阻挡层。
9.如权利要求7所述的方法,其特征在于,形成所述高含锡量焊塞包括至少含约90%(重量)的锡的高含锡量焊塞。
10.如权利要求7所述的方法,其特征在于,还包括邻接至少一层低k电介质材料的所述导电焊盘。
11.如权利要求7所述的方法,其特征在于,提供至少一个层间电介质包括提供至少一层掺杂碳的氧化物。
12.如权利要求7所述的方法,其特征在于,还包括回流所述高含锡量焊塞以形成焊块。
13.如权利要求12所述的方法,其特征在于,在所述回流期间,所述润湿层被基本包含于所述高含锡量焊块中。
14.如权利要求7所述的方法,其特征在于,形成所述含钼阻挡层包括溅射沉积含钼材料。
15.一种电子系统,包括:
外壳内的外部衬底;以及
附连到所述外部衬底的至少一个微电子器件封装,所述微电子器件封装具有至少一个凸块下金属化层,包括:
邻接导电焊盘的粘附层;
邻接所述粘附层的含钼阻挡层;
邻接所述含钼阻挡层的润湿层;以及
邻接所述润湿层的高含锡量焊接材料;以及
与所述外部衬底接口的输入装置;以及
与所述外部衬底接口的显示装置。
16.如权利要求15所述的系统,其特征在于,所述含钼阻挡层包括至少含约90%(原子)的钼的材料。
17.如权利要求15所述的系统,其特征在于,所述高含锡量焊接材料包括至少含约90%(重量)的锡的材料。
18.如权利要求15所述的系统,其特征在于,还包括邻接至少一层低k电介质材料的所述导电焊盘。
19.如权利要求18所述的系统,其特征在于,所述至少一层低k电介质材料包括至少一层掺杂碳的氧化物。
20.如权利要求15所述的装置,其特征在于,所述润湿层基本被包含于所述高含锡量焊接材料中,从而形成金属间复合层。
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US7410833B2 (en) * | 2004-03-31 | 2008-08-12 | International Business Machines Corporation | Interconnections for flip-chip using lead-free solders and having reaction barrier layers |
JP4327656B2 (ja) * | 2004-05-20 | 2009-09-09 | Necエレクトロニクス株式会社 | 半導体装置 |
JP4327657B2 (ja) * | 2004-05-20 | 2009-09-09 | Necエレクトロニクス株式会社 | 半導体装置 |
US7325716B2 (en) * | 2004-08-24 | 2008-02-05 | Intel Corporation | Dense intermetallic compound layer |
JP4322189B2 (ja) * | 2004-09-02 | 2009-08-26 | 株式会社ルネサステクノロジ | 半導体装置 |
US7087521B2 (en) * | 2004-11-19 | 2006-08-08 | Intel Corporation | Forming an intermediate layer in interconnect joints and structures formed thereby |
US7541681B2 (en) * | 2006-05-04 | 2009-06-02 | Infineon Technologies Ag | Interconnection structure, electronic component and method of manufacturing the same |
JP2008042077A (ja) * | 2006-08-09 | 2008-02-21 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US7727876B2 (en) * | 2006-12-21 | 2010-06-01 | Stats Chippac, Ltd. | Semiconductor device and method of protecting passivation layer in a solder bump process |
US8314500B2 (en) * | 2006-12-28 | 2012-11-20 | Ultratech, Inc. | Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers |
US20090140401A1 (en) * | 2007-11-30 | 2009-06-04 | Stanley Craig Beddingfield | System and Method for Improving Reliability of Integrated Circuit Packages |
US10074553B2 (en) * | 2007-12-03 | 2018-09-11 | STATS ChipPAC Pte. Ltd. | Wafer level package integration and method |
US9460951B2 (en) * | 2007-12-03 | 2016-10-04 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of wafer level package integration |
US7964965B2 (en) * | 2008-03-31 | 2011-06-21 | Intel Corporation | Forming thick metal interconnect structures for integrated circuits |
EP2304783A1 (en) * | 2008-05-28 | 2011-04-06 | MVM Technologies, Inc. | Maskless process for solder bumps production |
US20100029074A1 (en) * | 2008-05-28 | 2010-02-04 | Mackay John | Maskless Process for Solder Bump Production |
JP5438114B2 (ja) * | 2008-09-18 | 2014-03-12 | アイメック | 材料ボンディングのための方法およびシステム |
US7928534B2 (en) * | 2008-10-09 | 2011-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bond pad connection to redistribution lines having tapered profiles |
US8736050B2 (en) | 2009-09-03 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Front side copper post joint structure for temporary bond in TSV application |
US8759949B2 (en) * | 2009-04-30 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer backside structures having copper pillars |
US8492892B2 (en) | 2010-12-08 | 2013-07-23 | International Business Machines Corporation | Solder bump connections |
EP2761651B1 (en) | 2011-09-30 | 2019-05-29 | Intel Corporation | Method for handling a very thin device wafer with a solder bump using a support substrate with a planar wetting surface and a layer of thermosetting material |
RU2494492C1 (ru) * | 2012-06-07 | 2013-09-27 | Общество с ограниченной ответственностью "Компания РМТ" | Способ создания токопроводящих дорожек |
KR102233334B1 (ko) | 2014-04-28 | 2021-03-29 | 삼성전자주식회사 | 주석 도금액, 주석 도금 장치 및 상기 주석 도금액을 이용한 반도체 장치 제조 방법 |
US9653381B2 (en) | 2014-06-17 | 2017-05-16 | Micron Technology, Inc. | Semiconductor structures and die assemblies including conductive vias and thermally conductive elements and methods of forming such structures |
US9960135B2 (en) * | 2015-03-23 | 2018-05-01 | Texas Instruments Incorporated | Metal bond pad with cobalt interconnect layer and solder thereon |
US11610861B2 (en) * | 2020-09-14 | 2023-03-21 | Infineon Technologies Austria Ag | Diffusion soldering with contaminant protection |
US20220246508A1 (en) * | 2021-01-29 | 2022-08-04 | Mediatek Inc. | Ball pad design for semiconductor packages |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0165883B1 (ko) * | 1988-09-16 | 1999-02-01 | 존 엠. 클락 | 테이프 자동화 본딩 프로세스용의 금/주석 공정 본딩 |
US5234153A (en) * | 1992-08-28 | 1993-08-10 | At&T Bell Laboratories | Permanent metallic bonding method |
JP3682758B2 (ja) * | 1998-12-24 | 2005-08-10 | 富士通株式会社 | 半導体装置及びその製造方法 |
TW449813B (en) * | 2000-10-13 | 2001-08-11 | Advanced Semiconductor Eng | Semiconductor device with bump electrode |
US6783589B2 (en) * | 2001-01-19 | 2004-08-31 | Chevron U.S.A. Inc. | Diamondoid-containing materials in microelectronics |
KR100384135B1 (ko) * | 2001-07-06 | 2003-05-14 | 한국과학기술원 | 선형 열절단 시스템을 이용한 단속적 재료 공급식가변적층 쾌속조형 공정 및 장치 |
US6689680B2 (en) * | 2001-07-14 | 2004-02-10 | Motorola, Inc. | Semiconductor device and method of formation |
US20030060041A1 (en) * | 2001-09-21 | 2003-03-27 | Intel Corporation | Dual-stack, ball-limiting metallurgy and method of making same |
TW536766B (en) * | 2002-02-19 | 2003-06-11 | Advanced Semiconductor Eng | Bump process |
TW556293B (en) * | 2002-02-21 | 2003-10-01 | Advanced Semiconductor Eng | Bump process |
US7095121B2 (en) * | 2002-05-17 | 2006-08-22 | Texas Instrument Incorporated | Metallic strain-absorbing layer for improved fatigue resistance of solder-attached devices |
US6750133B2 (en) * | 2002-10-24 | 2004-06-15 | Intel Corporation | Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps |
JP2005011838A (ja) * | 2003-06-16 | 2005-01-13 | Toshiba Corp | 半導体装置及びその組立方法 |
-
2004
- 2004-03-29 US US10/812,464 patent/US7064446B2/en not_active Expired - Fee Related
-
2005
- 2005-03-24 WO PCT/US2005/009660 patent/WO2005098933A1/en active Application Filing
- 2005-03-24 KR KR1020067020142A patent/KR100876485B1/ko not_active IP Right Cessation
- 2005-03-24 CN CN200580006974A patent/CN100578746C/zh not_active Expired - Fee Related
- 2005-03-25 TW TW094109496A patent/TWI287264B/zh not_active IP Right Cessation
- 2005-07-13 US US11/181,610 patent/US20050250323A1/en not_active Abandoned
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Also Published As
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CN100578746C (zh) | 2010-01-06 |
TW200534404A (en) | 2005-10-16 |
KR20060130688A (ko) | 2006-12-19 |
KR100876485B1 (ko) | 2008-12-31 |
WO2005098933A1 (en) | 2005-10-20 |
US20050250323A1 (en) | 2005-11-10 |
US20050212133A1 (en) | 2005-09-29 |
TWI287264B (en) | 2007-09-21 |
US7064446B2 (en) | 2006-06-20 |
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