CN101894814A - 焊料凸块ubm结构 - Google Patents

焊料凸块ubm结构 Download PDF

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CN101894814A
CN101894814A CN2010101365480A CN201010136548A CN101894814A CN 101894814 A CN101894814 A CN 101894814A CN 2010101365480 A CN2010101365480 A CN 2010101365480A CN 201010136548 A CN201010136548 A CN 201010136548A CN 101894814 A CN101894814 A CN 101894814A
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layer
metal
metal alloy
ubm structure
joint sheet
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CN101894814B (zh
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刘颂初
程子玶
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Younison (Malaysia) Co., Ltd.
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Unisem Advanced Technologies Sdn Bhd
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Abstract

本发明涉及焊料凸块UBM结构。公开了一种包括形成在芯片接合垫上的多个金属或金属合金层的凸块下金属化结构。因为基于铜的层的厚度被降低到大约0.3微米和10微米之间,优选在大约0.3微米和2微米之间,因此所公开的UBM结构具有对半导体器件上的应力改善。纯锡层的存在防止了基于镍的层的氧化和污染。也为随后的工艺形成了良好的可焊接表面。还公开了具有所公开的UBM结构的半导体器件及制造该半导体器件的方法。

Description

焊料凸块UBM结构
技术领域
本公开通常涉及半导体器件及其形成方法,更具体地,涉及具有多个金属或金属合金层的可靠的凸块下金属化(under bump metallization,UBM)。
背景技术
基于半导体的集成电路(通常称为“芯片”)与封装引线之间的互连通过引线接合、焊料凸块或载带自动接合(TAB)来实现。其中,引线接合技术由于其低成本而最常使用。然而,当芯片-封装互连的尺寸按比例降低时,由于引线接合要求将所有输入/输出(I/O)连接都路由到芯片的边缘,因此引线接合的性能和可靠性可能受到影响。
焊料凸块法是利用可回流的焊料球来接合芯片上的触点与封装上的对应触点。提供了相对传统引线接合技术的有效替代。通常在位于承载芯片的基板顶面的接合垫(bond pad)上沉积焊料凸块。然而,在焊料凸块和芯片之间典型地存在UBM结构。在美国专利No.6,878,465中公开了一种这样的UBM。
该UBM结构用作接合垫和焊料凸块之间的电气和机械接口。其在焊料凸块和接合垫之间提供必要的粘接并且也作为两者之间的扩散阻挡物。
大多数UBM结构包括多个金属或金属合金层。在这种UBM结构中,铜是通常使用的金属。其增加了焊料的可接合性和可浸润性。
已知:通过在回流期间或芯片使用期间产生的热量,焊料凸块中的锡与UBM结构中的铜反应,形成金属间化合物。由于形成的金属间化合物易碎,因此如果铜与焊料凸块直接接触,将大大危及焊料凸块和接合垫之间的接合强度。另外,为了防止由这种反应导致的铜的自熄,通常使用非常厚的铜层,根据美国专利公布2004/0217482,在4-8微米级的量级。由于铜具有高的热膨胀系数(CTE),因此在使用更多铜的时候,将引起更多的热应力。
镍相比铜而言与锡的反应速度慢,并且已被引入UBM结构中来保护铜层。然而,包括镍层的UBM结构遇到与镍的焊接能力差和镍层中固有的残余应力相关的问题。
美国专利No.6,716,738公开了在焊料凸块和镍层之间形成另一铜或金层,以增加该UBM结构的可浸润性和可接合性。然而,金不是成本有效的,而且在使用铜时,由于铜将与焊料凸块直接接触,因此将形成金属间材料。
对于UBM结构还需要具有薄的铜层,同时需要具有好的可浸润性和可接合性。
发明内容
本公开提供了一种凸块下金属化结构,其包括设置在芯片接合垫上方的基于钛的层、设置在基于钛的层上方的基于铜的层、设置在基于铜的层上方的基于镍的层、和设置在基于镍的层上方的纯锡层或锡合金层(例如锡银(tin-silver))。
因为基于铜的层的厚度被降低到大约0.3微米和10微米之间,优选在大约0.3微米和2微米之间,因此所公开的UBM结构具有对半导体器件的应力改善。纯锡或锡合金层的存在防止了基于镍的层的氧化和污染。也为随后的工艺形成了良好的可焊接表面。
本公开还提供了一种具有所公开的UBM结构的半导体器件及其制造方法。
附图说明
图1示出了根据本公开一个实施例的半导体器件隔离部分的横截面图。
图2示出了具有重新分布的接合垫的半导体器件隔离部分的横截面图。
具体实施方式
图1是根据本公开的一个实施例形成在基板1上的半导体结构隔离部分的横截面图。如图1所示,在基板1的表面2上有接合垫3。接合垫3可以经由任何常规手段形成。其是由导电材料制成的。最常使用的是Al或Cu。
至少有一个钝化层4形成在基板1和接合垫3上方。图1中的钝化层4通常是由绝缘材料形成的,例如氧化硅和氮化硅。电绝缘是钝化层4的主要功能。其还用来将尘埃和湿气排除在外,以保护芯片不受腐蚀和其它损害。钝化层4之上的电介质层5由有机材料制成,优选聚酰亚胺。电介质层5是柔顺的(compliant),并可用作应力缓冲层。
在电介质层中形成有孔,以至少暴露一部分接合垫3。该孔可以是任何形状和尺寸。当使用多个钝化层时,也至少暴露每个钝化层的一部分。
该UBM结构由形成在接合垫3上的多个金属层组成,其中没有两个相邻层由相同金属或金属合金形成。设置在接合垫3和部分钝化层4和5上的第一金属或金属合金层6优选是基于钛的。“基于”意思是该合金的至少50%是指定的金属,在这种情况下,为钛。其提供了接合垫3和第二金属或金属合金层7之间的良好粘合,并且具有大约500至3000A的厚度。
设置在层6上方的层7优选是基于铜的。该层提供了焊料凸块10和接合垫3之间的良好电气连接。其具有大约0.3至10微米的厚度,优选为0.3至2微米。与常规UBM结构相比,根据本公开的铜层是薄的。因为铜具有高的CTE并且应力水平是CTE差和厚度的函数,所以具有薄铜层的UBM大大降低了热应力,由此提高了焊料凸块与接合垫连接的可靠性。
第三金属或金属合金层,即层8,设置在层7上方。其优选由基于镍制成,并且具有大约1.0微米到5.0微米的厚度。层8用作对于在层7和焊料凸块10之间金属间化合物形成的良好阻挡物。即使根据本公开的铜层非常薄,但是因为所公开的厚度的镍层的存在,它将不会自熄。
设置在层8上的层9由纯锡或锡合金制成,且具有大约2微米到大约10微米的厚度。该层用来增加UBM结构的可浸润性和可接合性,并防止层8的污染。该锡层还有利于后面的制造工序。
该UBM结构的每个层可以利用常规的制造技术形成,例如,溅射、蒸发和镀覆工艺。
通过利用丝网印刷技术或焊料球滴(solder sphere drop)技术将焊料凸块10设置在层9上方。
如图2所示,可以通过重新分布层11使该UBM结构与芯片接合垫3偏离。重新分布层11覆盖接合垫3,并包括至少一个电连接到接合垫3的金属层。例如,该重新分布层可以包括钛层和铜层,其中钛层覆盖在接合垫3上,并且铜层沉积在钛层上方。该重新分布层通常被一个或更多个钝化层覆盖。钝化层形成有用来暴露部分重新分布层11的孔。如第一实施例中公开的UBM结构以完全覆盖暴露的接合垫3的方式形成在接合垫3上方。

Claims (19)

1.一种凸块下金属化UBM结构,包括:
设置在半导体基板的接合垫上方的第一金属或金属合金层;
设置在所述第一层上方的第二金属或金属合金层;
设置在所述第二层上方的第三金属或金属合金层;
设置在所述第三层上方的第四金属或金属合金层,所述第四层包括纯锡或锡合金并且与焊料凸块接触;
其中没有两个相邻层由相同的金属或金属合金形成。
2.如权利要求1的UBM结构,其中所述第一层是基于钛的。
3.如权利要求2的UBM结构,其中所述第二层是基于铜的。
4.如权利要求3的UBM结构,其中所述第三层是基于镍的。
5.如权利要求4的UBM结构,其中所述第一层具有大约500-3000A的厚度;所述第二层具有大约0.3-10微米的厚度;所述第三层具有大约1.0-5.0微米的厚度;和所述第四层具有大约2.0-10.0微米的厚度。
6.如权利要求5的UBM结构,其中所述UBM经由重新分布层从所述接合垫偏移,所述重新分布层包括电连接到所述接合垫的至少一个金属层。
7.如权利要求1的UBM结构,其中所述第一层具有大约500-3000A的厚度。
8.如权利要求7的UBM结构,其中所述第二层具有大约0.3-10微米的厚度。
9.如权利要求8的UBM结构,其中所述第三层具有大约1.0-5.0微米的厚度。
10.如权利要求9的UBM结构,其中所述第四层具有大约2.0-10.0微米的厚度。
11.如权利要求10的UBM结构,其中所述第一层是基于钛的;所述第二层是基于铜的;和所述第三层是基于镍的。
12.如权利要求1的UBM结构,其中所述UBM经由重新分布层从所述接合垫偏移;所述重新分布层包括电连接到所述接合垫的至少一个金属层。
13.如权利要求12的UBM结构,其中所述重新分布层包括钛层和铜层,所述钛层覆盖在所述接合垫和至少一部分钝化层上,并且所述铜层沉积在所述钛层上方。
14.如权利要求13的UBM结构,其中所述第一层包括钛;所述第二层包括铜;并且所述第四层包括镍。
15.如权利要求14的UBM结构,其中所述第一层具有大约500-3000A的厚度;所述第二层具有大约0.3-10微米的厚度;所述第三层具有大约1.0-5.0微米的厚度;和所述第四层具有大约2.0-10.0微米的厚度。
16.一种在半导体结构上形成焊料连接的方法,包括:
提供基板,所述基板具有至少一个接合垫和在所述接合垫上形成的钝化层,其中所述钝化层包括暴露每个所述接合垫的至少一部分的孔;
在所述孔和部分所述钝化层上方形成凸块下金属化UBM结构,所述UBM结构包括:
设置在所述孔和部分所述钝化层上方的第一金属或金属合金层,
设置在所述第一层上方的第二金属或金属合金层,
设置在所述第二层上方的第三金属或金属合金层,
设置在所述第三层上方的第四金属或金属合金层,所述第四层包括纯
锡或锡合金,其中没有两个相邻层由相同的金属或金属合金形成;
在所述UBM结构上方形成焊料凸块。
17.一种在半导体结构上形成焊料连接的方法,包括:
提供基板,所述基板包括至少一个接合垫和形成在该接合垫上的第一钝化层,其中所述第一钝化层具有暴露每个所述接合垫的至少一部分的孔;
在所述基板上方沉积重新分布层,所述重新分布层电连接到每个所述接合垫;
在所述重新分布层上方形成第二钝化层;
移除部分所述第二钝化层以暴露至少一部分所述重新分布层;
在所述暴露的重新分布层和部分所述第二钝化层上方形成凸块下金属化UBM结构,所述UBM结构包括:
设置在所述暴露的重新分布层和部分所述第二钝化层上方的第一金
属或金属合金层,
设置在所述第一层上方的第二金属或金属合金层,
设置在所述第二层上方的第三金属或金属合金层,
设置在所述第三层上方的第四金属或金属合金层,所述第四层包括纯
锡或锡合金,其中没有两个相邻层由相同的金属或金属合金形成;
在所述UBM结构上方形成焊料凸块。
18.一种晶片结构,包括:
具有至少一个接合垫和钝化层的基板,所述钝化层包括暴露每个所述接合垫的至少一部分的孔;
形成在所述孔和部分所述钝化层上的UBM结构,其中所述UBM结构包括:
设置在所述孔和部分所述钝化层上方的第一金属或金属合金层,
设置在所述第一层上方的第二金属或金属合金层,
设置在所述第二层上方的第三金属或金属合金层,
设置在所述第三层上方的第四金属或金属合金层,所述第四层包括纯
锡或锡合金,其中没有两个相邻层由相同的金属或金属合金形成;
形成在所述UBM结构上的焊料凸块。
19.一种晶片结构,包括:
具有至少一个接合垫和第一钝化层的基板,其中所述第一钝化层具有暴露每个所述接合垫的至少一部分的第一组孔;
设置在所述基板上的重新分布结构,所述重新分布结构电连接到每个所述接合垫;
形成在所述重新分布结构上的第二钝化层,所述第二钝化层具有暴露至少一部分所述重新分布结构的第二组孔;
设置在所述第二组孔和部分所述第二钝化层上的UBM结构,其中所述UBM结构包括:
设置在通孔和部分第二钝化层上的第一金属或金属合金层,
设置在所述第一层上的第二金属或金属合金层,
设置在所述第二层上的第三金属或金属合金层,
设置在所述第三层上的第四金属或金属合金层,所述第四层包括纯锡
或锡合金,其中没有两个相邻层由相同的金属和金属合金形成;
形成在所述UBM结构上的焊料凸块。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990292A (zh) * 2015-03-17 2016-10-05 株式会社东芝 半导体装置及其制造方法
CN111508919A (zh) * 2019-01-31 2020-08-07 联华电子股份有限公司 半导体装置及半导体装置的制作方法
CN111508856A (zh) * 2014-10-13 2020-08-07 通用电气公司 具有引线接合件的功率覆层结构和制造其的方法
CN113611680A (zh) * 2021-09-28 2021-11-05 甬矽电子(宁波)股份有限公司 防脱凸块封装结构及其制备方法

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5234521B2 (ja) * 2009-08-21 2013-07-10 Tdk株式会社 電子部品及びその製造方法
US20110186989A1 (en) * 2010-02-04 2011-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Bump Formation Process
US20120325671A2 (en) * 2010-12-17 2012-12-27 Tel Nexx, Inc. Electroplated lead-free bump deposition
JP6046406B2 (ja) * 2011-07-26 2016-12-14 ローム アンド ハース エレクトロニック マテリアルズ エルエルシーRohm and Haas Electronic Materials LLC 高温耐性銀コート基体
US9054098B2 (en) * 2011-08-30 2015-06-09 Stats Chippac Ltd. Integrated circuit packaging system with redistribution layer and method of manufacture thereof
US8569886B2 (en) 2011-11-22 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of under bump metallization in packaging semiconductor devices
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8710656B2 (en) 2012-07-20 2014-04-29 International Business Machines Corporation Redistribution layer (RDL) with variable offset bumps
TWI490994B (zh) * 2012-09-03 2015-07-01 矽品精密工業股份有限公司 半導體封裝件中之連接結構
US9070644B2 (en) 2013-03-15 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging mechanisms for dies with different sizes of connectors
US9646894B2 (en) 2013-03-15 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging mechanisms for dies with different sizes of connectors
US9082649B2 (en) 2013-11-25 2015-07-14 Texas Instruments Incorporated Passivation process to prevent TiW corrosion
US9780052B2 (en) * 2015-09-14 2017-10-03 Micron Technology, Inc. Collars for under-bump metal structures and associated systems and methods
US20170365567A1 (en) * 2016-06-20 2017-12-21 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US10090271B1 (en) 2017-06-28 2018-10-02 International Business Machines Corporation Metal pad modification
US11289426B2 (en) * 2018-06-15 2022-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
WO2020136979A1 (ja) * 2018-12-28 2020-07-02 Jx金属株式会社 はんだ接合部
WO2023123328A1 (zh) * 2021-12-31 2023-07-06 京东方科技集团股份有限公司 线路板、功能背板及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184061B1 (en) * 1998-04-24 2001-02-06 Mitsubishi Denki Kabushiki Kaisha Electrode of semiconductor device, method of manufacturing thereof, and the semicondutor device
US20050012211A1 (en) * 2002-05-29 2005-01-20 Moriss Kung Under-bump metallugical structure
US20060128135A1 (en) * 2004-12-14 2006-06-15 Taiwan Manufacturing Company, Ltd. Solder bump composition for flip chip
CN1930672A (zh) * 2004-03-29 2007-03-14 英特尔公司 允许使用高含锡量焊块的凸块下金属化层
US20080122117A1 (en) * 2006-09-22 2008-05-29 Stats Chippac, Inc. Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps
JP2008172232A (ja) * 2007-01-12 2008-07-24 Silicon Storage Technology Inc パッケージのバンプ下冶金(ubm)構造及びそれを製造する方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6638847B1 (en) * 2000-04-19 2003-10-28 Advanced Interconnect Technology Ltd. Method of forming lead-free bump interconnections
US6413851B1 (en) * 2001-06-12 2002-07-02 Advanced Interconnect Technology, Ltd. Method of fabrication of barrier cap for under bump metal
US6774026B1 (en) * 2002-06-20 2004-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for low-stress concentration solder bumps
KR100476301B1 (ko) * 2002-07-27 2005-03-15 한국과학기술원 전기도금법에 의한 반도체 소자의 플립칩 접속용 ubm의형성방법
US6703069B1 (en) * 2002-09-30 2004-03-09 Intel Corporation Under bump metallurgy for lead-tin bump over copper pad

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184061B1 (en) * 1998-04-24 2001-02-06 Mitsubishi Denki Kabushiki Kaisha Electrode of semiconductor device, method of manufacturing thereof, and the semicondutor device
US20050012211A1 (en) * 2002-05-29 2005-01-20 Moriss Kung Under-bump metallugical structure
CN1930672A (zh) * 2004-03-29 2007-03-14 英特尔公司 允许使用高含锡量焊块的凸块下金属化层
US20060128135A1 (en) * 2004-12-14 2006-06-15 Taiwan Manufacturing Company, Ltd. Solder bump composition for flip chip
US20080122117A1 (en) * 2006-09-22 2008-05-29 Stats Chippac, Inc. Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps
JP2008172232A (ja) * 2007-01-12 2008-07-24 Silicon Storage Technology Inc パッケージのバンプ下冶金(ubm)構造及びそれを製造する方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
CHIH-TANG PENG等: "Experimental Characterization and Mechanical Behavior Analysis on Intermetallic Compounds of 96.5Sn-3.5Ag and 63Sn-37Pb Solder Bump with Ti-Cu-Ni UBM on Copper Chip", 《2004 ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE》 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111508856A (zh) * 2014-10-13 2020-08-07 通用电气公司 具有引线接合件的功率覆层结构和制造其的方法
CN111508856B (zh) * 2014-10-13 2023-03-21 通用电气公司 具有引线接合件的电气封装
CN105990292A (zh) * 2015-03-17 2016-10-05 株式会社东芝 半导体装置及其制造方法
CN105990292B (zh) * 2015-03-17 2019-11-01 东芝存储器株式会社 半导体装置及其制造方法
CN111508919A (zh) * 2019-01-31 2020-08-07 联华电子股份有限公司 半导体装置及半导体装置的制作方法
US11476212B2 (en) 2019-01-31 2022-10-18 United Microelectronics Corporation Semiconductor contact structure having stress buffer layer formed between under bump metal layer and copper pillar
CN113611680A (zh) * 2021-09-28 2021-11-05 甬矽电子(宁波)股份有限公司 防脱凸块封装结构及其制备方法

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