CN111508856B - 具有引线接合件的电气封装 - Google Patents

具有引线接合件的电气封装 Download PDF

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CN111508856B
CN111508856B CN202010112037.9A CN202010112037A CN111508856B CN 111508856 B CN111508856 B CN 111508856B CN 202010112037 A CN202010112037 A CN 202010112037A CN 111508856 B CN111508856 B CN 111508856B
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pol
layer
dielectric layer
metallization
semiconductor device
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CN111508856A (zh
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A.V.高达
P.A.麦康奈利
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General Electric Co
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General Electric Co
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Abstract

本发明涉及具有引线接合件的功率覆层结构和制造其的方法。具体而言，功率覆层(POL)结构包括：功率器件，其具有布置在功率器件的上表面上的至少一个上接触焊盘；和POL互连层，其具有联接至功率器件的上表面的电介质层、和金属化层，金属化层具有金属互连件，该金属互连件延伸穿过通孔并且电联接至功率器件的至少一个上接触焊盘，该通孔穿过电介质层而形成。POL结构还包括直接联接至金属化层的至少一个铜引线接合件。

Description

具有引线接合件的电气封装
本申请是于2015年10月13日提交（优先权日为2014年10月13日）的申请号为201510668963.3的中国发明专利申请(发明名称为“具有引线接合件的功率覆层结构和制造其的方法”)的分案申请。
技术领域
本发明的实施例大体涉及用于功率器件的引线接合的结构和方法，且更具体而言，涉及功率覆层(POL)结构，该功率覆层结构与功率器件的接触焊盘的材料类型无关地实现功率器件的铜引线接合。
背景技术
功率半导体器件是在功率电子电路中用作开关或整流器的半导体器件，例如，开关式功率供应。在使用中，功率半导体器件典型地借助于封装结构而安装至外部电路，其中封装结构提供对外部电路的电连接，并且还提供移除由器件生成的热且相对于外部环境保护器件的途经。功率半导体器件设有多个输入/输出(I/O)互连件来将器件电连接至外部电路。这些I/O连接件可以以焊球、电镀突块、或引线接合连接件的形式提供。在引线接合封装的情况下，引线接合件提供为，在可为电路板或引线框的下一个封装水平处将在功率半导体器件上提供的接合焊盘或接触焊盘连接至对应的焊盘或导电元件。大多数现有的功率器件封装结构使用引线接合件和衬底(例如，直接敷铜(DBC)衬底)的组合来提供对相应的半导体器件的两侧的I/O互连。封装结构可为有引线的(引线框等)或设有栓接的端子，以用于提供对封装结构的电连接性。引线接合件形成从封装结构的一个表面至封装引脚的电连接，该电引脚然后与外部电路对接，且DBC衬底将封装结构的其他表面电联接至外部电路。
图1绘出了根据已知的现有技术的引线接合的功率封装结构10，其具有半导体器件12，该半导体器件12具有联接至半导体器件12上表面18的门极接触焊盘14和发射极接触焊盘16。如所显示的，引线接合件20、22、24直接接合至半导体器件12的接触焊盘14、16。为了在引线接合件20、22、24与半导体器件12的上接触焊盘14、16之间形成可靠的连接，引线接合件20、22、24的材料典型地选择为匹配上接触焊盘14、16的金属化。
通常处于镍金金属化物或镍银金属化物的形式的集电极焊盘形成在半导体器件12的下表面28上。焊料30或烧结的银小片附接材料用于将半导体器件12联接至DBC或直接敷铝(DBA)衬底32。
因为功率器件典型地制造为带有铝接触焊盘，所以对应的引线接合件可能由铝或铝合金形成，以便形成对功率器件的可靠电连接。如今，在产业中存在朝向铜引线接合件的趋势，这提供更低的电阻，这导致更低的损耗和更高的效率。然而，铜引线接合件不形成对接触焊盘的铝金属化物的可靠电连接。
虽然铜接触焊盘可在制造时并入功率器件中，但是将铜并入功率器件制作工序中是非平凡的，且增加了显著的开发成本和时间。而且，制造商典型地在他们制造的所有功率器件上提供单个类型的金属化材料。如果功率模块可并入来自多个制造商的功率器件，那么在这些功率器件上形成可靠的引线接合件是困难的，因为在给出的模块内的各种功率器件可包括不相似的金属化材料。
甚至在功率器件设有铜金属化物的情况下，将铜引线接合件联接至铜金属化物也存在困难。例如，与较细尺度或铝引线接合件相比，将铜引线接合件，尤其是能够耐受高电流瞬变过程的粗尺度铜引线接合件附接至金属化物或接触焊盘将更大量的应力施加至功率器件。这是因为铜与铜的引线接合由于其与铝与铝的引线接合相比的材料特性，需要更高的能量以用于接合。由于这些更高的能量，故引线接合工序可损坏功率器件。
铜与铜的引线接合的另一问题为，电流在其从功率器件的接触焊盘向引线接合件流动时的集聚。在功率器件上的接触焊盘的金属化层是薄的(例如，数微米)，且电流必须行进穿过该薄的金属化物，直至其遇到引线接合件并然后流过其。引线接合件由于设备约束而仅可以以一定间隔放置，因而各功率器件将仅具有跨过接触焊盘分布的少量引线接合件。虽然为各接触焊盘提供多个引线接合件有助于分布电流流动，但互连结构中的电阻仍导致固有损耗。
虽然当前已进行尝试来缓解与铜与铜的引线接合相关的上述问题，例如通过优化接触焊盘的铜材料特性且调整硬焊盘的厚度，但在本领域中存在进一步改进的空间。
因而，将期望提供一种POL结构，其允许使用铜引线接合件而不将功率器件的接触焊盘的金属化物改变成铜。还将期望具有一种用于制作处于引线接合件的形式的I/O互连件的方法，该I/O互连件减少在引线接合工序期间由施加的应力引起的器件损坏，从而增加了加工生产量，且其提供从功率器件到引线接合件的有效电流分布。
发明内容
根据本发明的一个方面，功率覆层(POL)结构包括：功率器件，其具有布置在功率器件的上表面上的至少一个上接触焊盘；和POL互连层，其具有联接至功率器件的上表面的电介质层、和金属化层，金属化层具有金属互连件，该金属互连件延伸穿过通孔且电联接至功率器件的至少一个上接触焊盘，该通孔穿过电介质层而形成。POL结构还包括直接联接至金属化层的至少一个铜引线接合件。
根据本发明的另一方面，制造POL结构的方法包括：提供包括多个半导体器件的晶圆；将电介质层联接至多个半导体器件中的各个的上表面；穿过电介质层形成多个通孔，来暴露出多个半导体器件的至少一个接触焊盘；和在电介质层的上表面上形成金属化层，金属化层具有金属互连件，该金属互连件延伸穿过多个通孔且与多个半导体器件的至少一个接触焊盘电联接。该方法还包括将至少一个引线接合件联接至金属化层的顶部表面。
根据本发明的又一方面，POL组件包括第一半导体器件、第二半导体器件、和POL互连组件，该POL互连组件具有粘合地联接至第一和第二半导体器件的上接触焊盘的聚酰胺膜和形成在聚酰胺膜上的金属化路径，该金属化路径包括多个金属互连件，该金属互连件延伸穿过通孔且电联接至第一和第二半导体器件的上接触焊盘，该通孔穿过聚酰胺膜而形成。POL组件还包括多个铜引线接合件，该多个铜引线接合件直接联接至金属化路径，其中，多个铜引线接合件中的第一引线接合件电联接至第一半导体器件的上接触焊盘，且其中，多个铜引线接合件中的第二引线接合件电联接至第二半导体器件的上接触焊盘。
技术方案1：一种功率覆层(POL)结构，其包括：
功率器件，其具有布置在所述功率器件的上表面上的至少一个上接触焊盘；
POL互连层，其包括：
电介质层，其联接至所述功率器件的上表面；和
金属化层，其具有金属互连件，所述金属互连件延伸穿过通孔且电联接至所述功率器件的所述至少一个上接触焊盘，所述通孔穿过所述电介质层而形成；和
至少一个铜引线接合件，其直接联接至所述金属化层。
技术方案2：根据技术方案1所述的POL结构，其特征在于，所述至少一个上接触焊盘包括铝。
技术方案3：根据技术方案1所述的POL结构，其特征在于，还包括多层衬底，所述多层衬底利用焊料层热联接且电联接至所述功率器件的下接触焊盘，所述多层衬底包括直接敷铜(DBC)和直接敷铝(DBA)衬底中的一种。
技术方案4：根据技术方案1所述的POL结构，其特征在于，所述电介质层在所述至少一个铜引线接合件下方具有基本上均匀的厚度。
技术方案5：根据技术方案1所述的POL结构，其特性在于，所述电介质层经由粘合层而联接至所述功率器件的上表面。
技术方案6：根据技术方案1所述的POL结构，其特性在于，所述POL互连层的布置在所述引线接合件的接触表面与所述功率器件之间的一部分没有所述电介质层。
技术方案7：根据技术方案1所述的POL结构，其特征在于，还包括：
金属互连件，其具有定位于所述金属化层的顶部表面下方的上接触表面；和
铜引线接合件，其联接至所述金属互连件的上接触表面；
其中，上引线接合件的接触表面的表面区域小于所述金属互连件的上接触表面的表面区域。
技术方案8：根据技术方案1所述的POL结构，其特性在于，所述至少一个引线接合件的接触表面联接至所述POL互连层的具有金属化互连件的一部分。
技术方案9：一种制造功率覆层(POL)结构的方法，其包括：
提供包括多个半导体器件的晶圆；
将电介质层联接至所述多个半导体器件中的各个的上表面；
穿过所述电介质层形成多个通孔，来暴露出所述多个半导体器件的至少一个接触焊盘；
在所述电介质层的上表面上形成金属化层，所述金属化层具有金属互连件，所述金属互连件延伸穿过所述多个通孔且与所述多个半导体器件的所述至少一个接触焊盘电联接；和
将至少一个引线接合件联接至所述金属化层的顶部表面。
技术方案10：根据技术方案9所述的方法，其特征在于，将所述电介质层联接至所述多个半导体器件中的各个的上表面包括在它们之间布置粘合层。
技术方案11：根据技术方案9所述的方法，其特征在于，还包括使所述晶圆单一化成多个POL结构，所述多个POL结构中的各个包括至少一个半导体器件，所述至少一个半导体器件具有所述电介质层的一部分和形成于其上的所述金属化层的一部分。
技术方案12：根据技术方案9所述的方法，其特征在于，还包括：
形成通孔来暴露出比所述至少一个引线接合件的表面区域大的接触焊盘的表面区域；和
将所述至少一个引线接合件联接至在所述通孔内形成的金属互连件。
技术方案13：根据技术方案9所述的方法，其特征在于，还包括将所述至少一个引线接合件联接至所述金属化层的没有金属互连件的一部分。
技术方案14：根据技术方案9所述的方法，其特征在于，还包括在将所述电介质层联接至所述多个半导体器件的上表面之前，将可移除的支撑结构联接至所述多个半导体器件的下表面。
技术方案15：根据技术方案9所述的方法，其特征在于，还包括将所述电介质层联接至所述晶圆的第一半导体器件和第二半导体器件，所述第一半导体器件具有比所述第二半导体器件的厚度大的厚度。
技术方案16：根据技术方案15所述的方法，其特征在于，还包括将所述第一半导体器件定位为离所述第二半导体器件一定距离，使得在它们之间形成间隙。
技术方案17：根据技术方案15所述的方法，其特征在于，还包括将垫片配置在所述支撑结构与所述第二半导体器件的下表面之间，使得所述第一半导体器件的上表面与所述第二半导体器件的上表面基本上共面。
技术方案18：根据技术方案15所述的方法，其特征在于，还包括：
将所述电介质层的第一部分联接至所述第一半导体器件；和
将所述电介质层的第二部分联接至所述第二半导体器件，其中，所述电介质层的第二部分的厚度大于所述电介质层的第一部分的厚度。
技术方案19：一种功率覆层(POL)组件，其包括：
第一半导体器件和第二半导体器件；
POL互连组件，其包括：
聚酰亚胺膜，其粘合地联接至所述第一和第二半导体器件的上接触焊盘；和
金属化路径，其形成在所述聚酰亚胺膜上，所述金属化路径包括多个金属互连件，所述多个金属互连件延伸穿过通孔且电联接至所述第一和第二半导体器件的上接触焊盘，所述通孔穿过所述聚酰亚胺膜而形成；和
多个铜引线接合件，其直接联接至所述金属化路径；
其中，所述多个铜引线接合件中的第一引线接合件电联接至所述第一半导体器件的上接触焊盘；且
其中，所述多个铜引线接合件中的第二引线接合件电联接至所述第二半导体器件的上接触焊盘。
技术方案20：根据技术方案19所述的POL组件，其特性在于，所述第一POL结构的所述至少一个铜引线接合件电联接至所述第二POL结构的所述至少一个铜引线接合件。
技术方案21：根据技术方案19所述的POL组件，其特性在于，所述第一半导体器件的厚度不同于所述第二半导体器件的厚度；且
其中，所述POL组件包括具有可变厚度的聚酰亚胺膜和联接至所述第一和第二半导体器件中的一者的底部表面的垫片中的至少一者。
技术方案22：根据技术方案19所述的POL组件，其特性在于，所述第一引线接合件联接至所述POL互连组件的基本上没有所述聚酰亚胺膜的一部分。
技术方案23：根据技术方案19所述的POL组件，其特性在于，所述第一引线接合件联接至所述POL互连组件的一部分，在其中，所述聚酰亚胺膜具有基本上均匀的厚度。
根据结合附图提供的本发明的优选实施例的下列详细描述，这些和其他优点和特征将更加易于理解。
附图说明
附图示出了用于执行本发明的当前构思的实施例。
在附图中：
图1是根据已知的现有技术的引线接合的功率封装结构的示意截面侧视图。
图2-6是在根据本发明的实施例制造功率覆层(POL)结构的各种阶段期间的示意截面侧视图。
图7是根据本发明的另一实施例的并入引线接合件的图6的POL结构中的一个的示意截面侧视图。
图8和9是根据本发明的备选实施例的带有引线接合件的POL结构的示意俯视图和截面侧视图。
图10和11是根据本发明的又一实施例的带有引线接合件的POL结构的示意俯视图和截面侧视图。
图12是根据本发明的实施例的示出包括POL结构的重组晶圆的示意截面侧视图。
图13是根据本发明的另一实施例的显示了包括POL结构的重组晶圆的示意截面侧视图。
图14是根据本发明的实施例的POL组件的示意截面侧视图。
图15是根据本发明的另一实施例的POL组件的示意截面侧视图。
具体实施方式
本发明的实施例提供了一种包括POL互连层的功率覆层(POL)结构，以及形成此种POL结构的方法。如在本文中所使用的，用语“POL”描述了一种结构，该结构与功率器件的接触焊盘的材料类型无关地允许功率器件的铜引线接合。POL互连层与门和发射极焊盘的材料无关地允许铜引线接合件对POL结构的可靠连接。此外，POL互连层设计为作为应力缓冲器起作用，该应力缓冲器减少在将引线接合件附接至器件接触焊盘的工序期间对功率器件的损坏。通过为电流提供在其进入引线接合件之前流过功率器件的金属化物的平行路径，在本文中公开的POL结构与现有技术的引线接合的功率器件相比具有降低的互连电阻和损耗。
图2-6绘出了一种根据本发明的实施例的用于制造POL结构34的技术，其中图2-6中的各个例示出了装配工序期间的POL结构34的截面。首先参照图2，显示了晶圆36。根据一个实施例，晶圆36包括多个半导体小片或半导体器件38、40、42。作为非限制性实例，半导体器件38、40、42是例如以下的功率器件：绝缘门双极型晶体管(IGBT)、金属氧化物半导体场效应晶体管(MOSFET)、双极结型晶体管(BJT)、集成门换流晶闸管(IGCT)、门极关断晶闸管、可控硅整流器(SCR)、包括例如硅(Si)、碳化硅(SiC)、氮化镓(GaN)、砷化镓(GaAs)的二极管或其他器件或器件的组合。虽然图2显示了具有三个半导体器件38、40、42的晶圆36，但可构想，晶圆36可包括多于或少于三个的半导体器件。
各半导体器件38、40、42可包括布置在其相应的半导体器件38、40、42的上表面56、58、60上的一个或更多个上接触焊盘44、46、48、50、52、54。这些上接触焊盘44-54提供对各半导体器件38、40、42内的内部接触件的导电路线。在示出的实施例中，各半导体器件38、40、42包括一对上接触焊盘，其联接至半导体器件38、40、42的对应发射极和/或门极或阳极区。在一个实施例中，半导体器件38、40、42是具有接触焊盘44-54的IGBT，接触焊盘44-54联接至相应半导体器件38、40、42的相应发射极区和门极区。具体而言，半导体器件38包括门极焊盘44和发射极焊盘46，半导体器件40包括门极焊盘48和发射极焊盘50，且半导体器件42包括门极焊盘52和发射极焊盘54。构想半导体小片38、40、42可提供为具有不同数量的接触焊盘和/或与在上述的那些不同的接触焊盘的组合。作为一个非限制实例，半导体小片38可提供为具有一对发射极焊盘。在一个实施例中，接触焊盘44、46、48包括铝。但是，构想接触焊盘44、46、48可由其他类型的导电材料(例如，铜)形成。各半导体器件38、40、42还包括至少一个下接触焊盘或集电极焊盘62、64、66，其布置在其相应半导体器件38、40、42的下表面68、70、72上。
如在图3中所示，POL结构34的制作开始于使用粘合层76将电介质层74联接至半导体器件38、40、42的上表面56、58、60。根据各种实施例，电介质层74可处于稳定、非流动的叠片或膜的形式，且可由例如以下的多种电介质材料中的一种形成：Kapton®、Ultem®、聚四氟乙烯(PTFE)、Upilex®、聚砜材料(例如，Udel®、Radel®)，或另一聚合物膜，例如，液晶聚合物(LCP)或聚酰亚胺材料。在一个实施例中，电介质层74可在框架(未显示)上伸展以控制制作工序期间的扭曲。粘合层76可使用旋涂技术应用至电介质层74，在其后，使用常规的拾取和放置设备和方法将晶圆36放置入粘合层76中。
虽然图3绘出了POL结构34已具有分离的电介质和粘合层74、76，但构想在备选实施例中，层74、76可由具有粘合特性的单个电介质层替换。此种粘合电介质层的非限制性实例包括旋制电介质(spin-on dielectric)，例如，聚酰胺或聚苯丙恶唑(PBO)。
现在参照图4，穿过电介质层74和粘合层76形成多个通孔78来暴露各半导体器件38、40、42的接触焊盘44、46、48。通孔78可通过但不限于例如激光钻孔或干刻蚀而形成。如在图5中所示的，金属化路径或金属化层80在制作工序的下个步骤中形成在电介质层74的上表面82上。金属化层80包括：金属互连件84的第一部分，其延伸穿过通孔78且电联接至半导体器件38、40、42的接触焊盘44、48、52；和金属互连件86的第二部分，其延伸穿过通孔78且电联接至半导体器件38、40、42的接触焊盘46、50、54。在优选实施例中，金属化路径80包括铜层。但是，构想制造技术可延伸至使用用于金属化路径80的其他导电材料。在一个实施例中，金属化路径80可使用溅射和电镀技术，随后进行光刻工序而形成。金属化路径80、通孔78、电介质层74、和粘合层76一起形成POL互连层88。
现参照图6，POL结构34被锯成或单一化成独立的POL结构90、92、94。各POL结构90、92、94包括相应的半导体器件38、40、42，该相应的半导体器件38、40、42具有接合至其的POL互连层88的一部分。因为晶圆36可包括多于或少于三个的半导体器件38、40、42，因而还构想POL结构34可分离成多于或少于三个的POL结构90、92、94。
现参照图7，在POL结构34已锯成或单一化成独立的POL结构90、92、94之后，一个或更多个引线接合件在制造技术的下个步骤中联接至金属化路径80。在例示出的实施例中，通过引线接合工序，引线接合件96、98联接至金属化路径80的金属互连件86，且引线接合件100而接合至金属互连件84。但是，构想备选实施例可包括接合至金属互连件86的第二部分的多于或少于两个的引线接合件，和/或接合至金属互连件84的第一部分的多于一个的引线接合件100。根据本发明的示范性实施例，引线接合件96、98、100是铜。
在一个实施例中，引线接合件96、98提供为具有比引线接合件100更粗的尺度或更大的直径，因而允许引线接合件96、98以更低的电阻处理行进穿过接触焊盘46的更大量的电流。作为一个非限制性实例，引线接合件96、98可提供为“粗”的铜引线接合件，其具有大约10-20密耳的直径。同时，引线接合件100可提供为相对于引线接合件96、98的“细”的铜引线接合件，其具有范围为例如从大约3-10密耳的直径。在本发明的此种非限制性实施例中，在粗引线接合件96、98与金属化路径80之间的表面接触区域102可为大约50密耳至80密耳。另一方面，在细尺度引线接合件100与金属化路径80之间的表面接触区域104可处于例如大约10-15密耳接近20密耳的范围中。在本发明的示范实施例中，表面接触区域102、104的宽度为相应引线接合件96、98、100的直径的两到三倍，并且表面接触区域102、104的长度是相应引线接合件96、98、100的直径的四到五倍。但是，本领域技术人员将理解，本发明的实施例不限于用于引线接合件96、98、100的特定线尺度，且引线接合件96、98、100的直径或尺寸可为给出的应用而根据需要变化，且对应的表面接触区域将相应地改变。
多层衬底106经由焊料108热联接且电联接至半导体器件38的接触焊盘62。在一个实施例中，多层衬底106是预先制作的直接敷铜(DBC)构件，其包括无机陶瓷衬底110，例如，如氧化铝、氮化铝、氮化硅等，其中铜的上和下薄片112、114经由直接敷铜中间层或硬焊层结合至其两侧。在本发明的另一实施例中，构想多层衬底106可为直接敷铝(DBA)衬底，其具有上和下铝薄片112、114。
虽然图7和随后的图绘出了热联接且电联接至接触焊盘62的多层衬底106，但构想备选实施例可包括单层衬底，例如，如引线框，而非多层衬底106。
如在图7中所显示，半导体器件38提供为具有大约50-500微米的厚度116。此外，金属化路径80的厚度118可处于大约5-150微米的范围中，而电介质层74的厚度120可为大约0.5-2密耳。
在图7中示出的实施例中，各引线接合件96、98、100联接至包括至少一个金属互连件84、86或其一部分的POL互连层88的相应部分122、124、126。具体而言，POL互连层88的在引线接合件100的接触表面128下方的部分126包括一个金属互连件84，且POL互连层88的在引线接合件96、98的相应接触表面130、132下方的部分122、124各自包括至少两个金属互连件86的部分。金属互连件86因而形成用于电流从半导体器件38行进到引线接合件96、98中的多个平行路径。
图8和9例示出了根据本发明的另一实施例的引线接合件96的在POL结构134内的定位。对POL结构134和POL结构34而言共通的元件和构件在适当的时候在本文中用相似的部件标号引用。如所显示，引线接合件96定位在形成于电介质层74内的凹陷或阱136内。阱136是通过在粘合层76和电介质层74内形成大通孔138而形成的，该大通孔138暴露出接触焊盘46的一部分，该部分具有比引线接合件96的表面区域142大的表面区域140。当形成金属化路径80时，金属化路径80延伸到通孔138中且形成金属互连件144，该金属互连件144具有相对平坦的上接触表面146。上接触表面146的表面区域148大于引线接合件96的对应表面区域142。因而，引线接合件96的接触表面150定位在金属化路径80的顶部表面152下方。在该实施例中，如在图9中例示出的，金属化路径80与接触焊盘46直接接触，粘合层76或电介质层74的任何部分都不定位在其间。因而，POL结构134的在引线接合件96的接触表面150下方的部分154基本上没有电介质层74或粘合层76的任何部分。在该实施例中，金属化路径80和接触焊盘46的增大的表面区域减少在接触焊盘46与引线接合件96之间的电流路径中的电阻。
在另一实施例中，构想当通过延伸到通孔138中和形成金属互连件144来形成金属化路径80时，金属化路径80的平坦上接触表面146和表面152是共面的。因此，引线接合件96定位在与金属化路径80的顶部表面152相同的高度处。在该实施例中，POL结构134的在引线接合件96的接触表面150之下的部分154仍然基本上没有电介质层74或粘合层76的任何部分。
现参照图10和11，示出了根据本发明的备选实施例的POL结构156。而且，对POL结构156和POL结构34而言共通的元件用在适当的时候用相似的参考标号引用。如所显示，引线接合件96、100在POL结构156的没有通孔78的一部分处联接至金属化路径80。因而，在该实施例中，没有通孔78位于电介质层74的部分158、160内，部分158、160直接定位在引线接合件96、100的相应接触位置162、164下方。电介质层74的厚度120在POL结构156的在引线接合件96、100之下的部分中是基本上均匀的，且作为应力缓冲器作用，来减少在引线接合工序期间对半导体器件38的潜在损坏。
虽然引线接合件96、98、100和DBC衬底106在上面描述为联接至图7-11中的独立的半导体器件38，但构想DBC衬底106和/或引线接合件96、98、100可在晶圆水平处(即，在单一化之前)应用至相应的半导体器件38、40、42。
在备选实施例中，POL互连层166可同时形成在提供在封装或重组晶圆内的多个独立的半导体器件上。现参照图12，重组晶圆168显示为具有联接至可移除的支撑结构174的多个半导体器件170、172。本领域技术人员将认识到，在备选实施例中，重组晶圆168可包括多于两个的半导体器件170、172。与图2-6的半导体器件38、40、42相似，半导体器件170、172包括多个上接触焊盘176、178、180、182，和至少一个下接触焊盘或集电极焊盘184、186。上接触焊盘176-182可包括发射极和/或门极焊盘的各种组合。在优选实施例中，上接触焊盘176-182是铝或铜。但是，构想上接触焊盘176-182可包括备选的金属化材料。
如在图12中所显示，半导体器件170、172具有不同的厚度188、190，其中半导体器件170的厚度188大于半导体器件172的厚度190。为了解决该厚度的不一致，可将垫片192定位在更薄的半导体器件与可移除的支撑结构174之间，使得半导体器件170的接触焊盘176、178的上表面194与在晶圆168内的半导体器件172的接触焊盘180、182的上表面196基本上共面。
半导体器件170、172的一个上表面194-196定位为基本上共面，POL互连层166以与关于图3-5描述的相似的方式形成在半导体器件170、172的顶部。在将电介质层200应用至半导体器件170、172时，构想单个粘合层可以与关于电介质层74(图3)描述的相似的方式旋涂到电介质层200上，或者独立的粘合剂层202、204可形成在各半导体器件170、172的顶部，如在图11中显示的。在任一情况下，电介质层200定位为跨过相邻半导体器件170、172之间的间隙206。根据各种实施例，电介质层200可处于叠片或膜的形式，并且可由与电介质层74相似的多种电介质材料中的一种形成。
在本发明的备选实施例中，半导体器件170、172经由相应的粘合层202、204(或单个粘合层)联接至电介质层200。在此，与将电介质层200应用至半导体器件170、172相反，半导体器件170、172通过将它们放置在粘合层202、204上而联接至电介质层200。因此，可移除的支撑结构174可省略。
在图13中例示出的本发明的另一实施例中，POL互连层208可形成为具有电介质层210，电介质层210构造为补偿半导体器件170、172的不同的厚度188、190。如所显示，电介质层210的与半导体器件170对准的第一部分212具有第一厚度214，且电介质层210的与半导体器件172对准的第二部分216具有第二厚度218。阶梯220定位在第一部分212与第二部分216之间的过渡部分处。在本发明的又一实施例中，半导体器件170、172的不同高度可通过改变粘合层202、204的厚度来补偿。
一起参照图12和13，为了完成各POL互连层166，穿过电介质层200和粘合层202、204形成多个通孔222，来暴露接触焊盘176、178、180、182。接着，金属化路径224形成在电介质层200的上表面226上。金属化路径224包括：金属互连件228，其延伸穿过通孔222且与接触焊盘176、180电联接；和金属互连件230，其延伸穿过通孔222且与接触焊盘178、182、214电联接。金属化路径224可包括铜层，并且可使用溅射和电镀技术，随后进行光刻工序而形成。
在POL互连层166或POL互连层208的形成之后，可根据需要移除支撑结构174和任何垫片192。各所得的POL组件232、234可然后被锯成或单一化成具有一个或多个半导体器件的独立的POL结构。在所得的POL结构包括多个半导体小片的情况下，电介质层200、210的置于间隙206内的部分可例如通过激光烧蚀来移除，或保留以对POL结构提供额外的结构刚性。引线接合件可在单一化之前或之后以与关于图7-11中的任一个所描述的相似的方式联接至金属互连件228、230。
现参照图14，根据本发明的另一实施例，单一化的POL结构90示为与POL组件238内的另一POL结构236电联接。如所显示，各POL结构90、236包括相应的POL互连层88，相应的POL结构90、236的引线接合件96、100、240、242联接至该相应的POL互连层88。引线接合件96、240将半导体器件38的接触焊盘46与半导体器件246的接触焊盘244电联接。虽然图14将POL结构90、236显示为具有不同的高度，但构想POL结构90、236可具有相同的高度。
在一个实施例中，如在图14中所显示，POL结构90、236热联接至相同的多层衬底106。然而，本领域技术人员将认识到，POL结构90、236可热联接至不同的多层衬底106。此外，构想在备选实施例中，多层衬底106可为DBC衬底或DBA衬底。
接着，图15显示了POL组件238的备选实施例，其中，关于图14描述的单一化的POL结构90、236被具有至少两个半导体器件170、172的重组晶圆232替换。如所显示，POL互连层166跨过两个半导体器件170、172的面朝上表面而形成，且跨越半导体器件170、172之间的间隙。虽然图15将半导体器件170、172描绘为热联接至相同的多层衬底106，但构想各半导体器件170、172可联接至其自身的不同的多层衬底106。
引线接合件96、100、240、242联接至POL互连层166。在该实施例中，金属化路径224将电连接POL组件238的半导体器件170、172的接触焊盘176、178、180、182。作为结果，半导体器件170、172可电联接至彼此，而没有在引线接合件96、240之间的直接连接。引线接合件96、240可因而用于将POL组件238电联接至其他POL组件。
有利地，本发明的实施例提供了一种POL结构，其与半导体器件的接触焊盘的材料类型无关地允许铜引线接合。POL互连层提供了铜金属化路径，该铜金属化路径电连接至半导体器件的接触焊盘且形成接触表面，铜引线接合件可以可靠地附接至该接触表面。这允许在如下POL模块中使用铜引线接合件，该POL模块包括具有不同金属化层(例如，铜和铝接触焊盘)的不同类型的功率器件。
与现有技术结构相比，所得的POL结构还提供从半导体功率器件至引线接合件的更有效的电流分布。在POL互连层内提供的金属化互连结构为电流提供在进入引线接合件之前从功率器件的接触焊盘的薄金属化物行进的平行路径。
而且，POL互连层的厚度形成了在引线接合件与功率器件之间的保护缓冲层，其相对于与铜与铜的引线接合相关的与铝与铝的引线接合相比高的能量来保护功率器件。因为POL互连层在引线接合工序期间充当用于功率器件的应力缓冲器，故具有比用于传统的铜与铜的引线接合的那些更粗尺度的引线接合件可电联接至功率器件而没有损坏器件的危险。这些更粗尺度的引线接合件还降低了在功率器件与引线接合件之间的互连电阻，并因而降低了相关的损耗。
因而，根据本发明的一个实施例，功率覆层(POL)结构包括：功率器件，其具有布置在功率器件的上表面上的至少一个上接触焊盘；和POL互连层，其具有联接至功率器件的上表面的电介质层、和金属化层，涂金属层具有金属互连件，该金属互连件延伸穿过通孔且电联接至功率器件的至少一个上接触焊盘，该通孔穿过电介质层而形成。POL结构还包括直接联接至金属化层的至少一个铜引线接合件。
根据本发明的另一方面，制造POL结构的方法包括：提供包括多个半导体器件的晶圆；将电介质层联接至该多个半导体器件中的各个的上表面；穿过电介质层形成多个通孔，来暴露出该多个半导体器件的至少一个接触焊盘；和在电介质层的上表面上形成金属化层，该金属化层具有金属互连件，该金属互连件延伸穿过该多个通孔且与该多个半导体器件的至少一个接触焊盘电联接。该方法还包括将至少一个引线接合件联接至金属化层的顶部表面。
根据本发明的又一方面，POL组件包括第一半导体器件、第二半导体器件、和POL互连组件，该POL互连组件具有粘合地联接至第一和第二半导体器件的上接触焊盘的聚酰胺膜和形成在聚酰胺膜上的金属化路径，该金属化路径包括多个金属互连件，该金属互连件延伸穿过通孔且电联接至第一和第二半导体器件的上接触焊盘，该通孔穿过聚酰胺膜而形成。POL组件还包括多个铜引线接合件，铜引线接合件直接联接至金属化路径，其中，多个铜引线接合件中的第一引线接合件电联接至第一半导体器件的上接触焊盘，且其中，多个铜引线接合件中的第二引线接合件电联接至第二半导体器件的上接触焊盘。
虽然已结合仅有限数量的实施例详细地说明了本发明，但是应该容易理解，本发明不限于此种公开的实施例。相反，本发明可修改以并入至今未描述但与本发明的精神和范围相称的任何数量的变更、改造、置换或等同布置。此外，虽然已经说明了本发明的各种实施例，但应该理解，本发明的方面可包括描述的实施例中的仅一些。因此，本发明不应看作由前述说明限制，而是仅由所附权利要求的范围限制。

Claims (4)

1.一种电气封装，包括：半导体器件，其至少具有位于其有源表面上的第一接触焊盘；以及互连层，所述互连层包括：电介质层，具有联接到所述半导体器件的有源表面的底部表面；在所述电介质层的顶部表面顶部的金属化层；以及从所述金属化层延伸且延伸穿过所述电介质层以与所述第一接触焊盘接触的多个金属互连件，
其中，所述电气封装还包括在所述金属化层顶部的引线接合件，所述引线接合件通过所述多个金属互连件电联接至所述第一接触焊盘；并且所述引线接合件被定位为使得没有所述多个金属互连件中的金属互连件位于所述引线接合件的接触表面与所述第一接触焊盘之间限定的区域中，并且所述电介质层在所述引线接合件之下的部分在厚度上是均匀的并且作为应力缓冲器作用。
2.根据权利要求1所述的电气封装，其中，所述半导体器件的所述有源表面包括所述第一接触焊盘和第二接触焊盘；且其中，所述互连层还包括从所述金属化层延伸且延伸穿过所述电介质层以与所述第二接触焊盘接触的另一金属互连件。
3.根据权利要求2所述的电气封装，还包括：第一引线接合件，通过所述多个金属互连件电联接到所述第一接触焊盘；和第二引线接合件，通过从所述金属化层延伸的另一金属互连件电联接到所述第二接触焊盘；其中所述第二引线接合件包括与所述第一引线接合件相比更细尺度的线。
4.根据权利要求1所述的电气封装，其中，所述半导体器件和所述互连层的宽度基本相等。
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