TW201626468A - 具有焊線的功率覆蓋結構及其製造方法 - Google Patents

具有焊線的功率覆蓋結構及其製造方法 Download PDF

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TW201626468A
TW201626468A TW104133047A TW104133047A TW201626468A TW 201626468 A TW201626468 A TW 201626468A TW 104133047 A TW104133047 A TW 104133047A TW 104133047 A TW104133047 A TW 104133047A TW 201626468 A TW201626468 A TW 201626468A
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power
semiconductor device
dielectric layer
layer
coupled
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TW104133047A
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TWI713470B (zh
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艾倫 格達
保羅 麥克尼爾
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通用電機股份有限公司
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Abstract

功率覆蓋(POL)結構包含功率裝置，其具有設置在功率裝置的上表面上的至少一上接觸墊，以及功率覆蓋互連層，其具有耦接至功率裝置的上表面的介電層以及具有金屬互連的金屬化層，該金屬互連延伸通過通過介電層而形成的通孔並且電性耦接至功率裝置的至少一上接觸墊。功率覆蓋結構更包含至少一銅焊線，其直接耦接至金屬化層。

Description

具有焊線的功率覆蓋結構及其製造方法
本發明之實施例大致係關於用於功率裝置之打線接合的結構及方法，更具體而言，係用於功率覆蓋(power overlay；POL)結構，其使得不管功率裝置的接觸墊之材料類型為何，功率裝置皆能夠進行銅打線接合。
功率半導體裝置為用以做為功率電子電路中的開關或整流器的半導體裝置，舉例而言，例如開關模式電源。在使用時，功率半導體裝置通常藉由封裝結構的方式安裝至外部電路，透過封裝結構提供電性連接至該外部電路，並且亦提供消除由裝置產生的熱的方法，以及保護裝置不受外部環境影響。功率半導體裝置提供有數個輸入/輸出(I/O)互連，用以電性連接該裝置至外部電路。這些輸入/輸出連接可以焊球、電鍍凸塊或焊線連接的形式提供。以打線接合封裝為例，焊線係提供用以將提供在功率半導體裝置上的接合墊或接觸墊連接至在封裝的下一級 之相應的墊或導電元件，其可以是電路板或引線框。多數現有的功率裝置封裝結構使用焊線及基板之組合，例如，直接接合銅(direct bond copper；DBC)基板，以便提供輸入/輸出互連至個別半導體裝置的兩側。這些封裝結構可以是有引線的(例如，引線框等)或是提供有螺栓端，用以提供電性連接至封裝結構。焊線形成自封裝結構的一表面至封裝接腳的電性連接，封裝接腳接著接口至外部電路，並且，DBC基板電性耦接封裝結構的另一表面至外部電路。
圖1描述依據現有技術之打線接合的功率封裝結構10，具有半導體裝置12，帶有閘極的接觸墊14及射極(emitter)的接觸墊16耦接至半導體裝置12的上表面18。如所示，焊線20、22、24直接接合至半導體裝置12的接觸墊14、16。為了形成焊線20、22、24與半導體裝置12的上接觸墊14、16之間的可靠連接，焊線20、22、24通常選擇與上接觸墊14、16之金屬積覆匹配的材料。
集極墊26形成在半導體裝置12的下表面28上，集極墊26通常為鎳鍍金或鎳鍍銀的形式。焊料30或燒結銀晶粒附接材料用以耦接半導體裝置12至直接接合銅(DBC)或直接接合鋁(direct bond aluminum；DBA)基板32。
由於功率裝置通常以鋁接觸墊製造，相應的焊線因而同樣地以鋁或鋁合金形成，以便建立可靠的電性 連接至功率裝置。目前，業界的趨勢傾向銅焊線，銅焊線可提供較低電阻，因而導致較低的損耗及較高的效率。然而，銅焊線無法形成可靠的電性連接至接觸墊的鋁金屬積覆。
雖然銅接觸墊在製造時可結合至功率裝置內，結合銅到功率裝置內之製程是複雜的，且顯著地增加開發成本和時間。並且，製造商在其所製造的所有功率裝置上通常僅提供單一類型的金屬積覆材料。由於功率模組可能結合來自多個製造商的功率裝置，在這些功率裝置上形成可靠的打線接合很困難，因為所提供的模組內之多樣的功率裝置可能包含不同的金屬積覆材料。
即使功率裝置提供有銅金屬積覆，耦接銅焊線至銅金屬積覆仍是困難的。舉例而言，附接銅焊線(特別是能夠承受高電流瞬變的大尺寸的銅焊線)至金屬積覆或接觸墊，施加比起較細尺寸或鋁焊線還要大量的應力至功率裝置。這是因為，銅至銅的打線接合相較於鋁至鋁的打線接合需要較高的接合能量。由於上述較高的能量，打線接合製程可能損害功率裝置。
另一個銅至銅打線接合的問題為，自功率裝置的接觸墊流向焊線之電流所造成的電流集中。功率裝置上的接觸墊之金屬化層為薄的(例如，幾微米)，因此電流必須穿過該薄金屬積覆直到遇到焊線，接著流經焊線。由於設備的限制，焊線僅能夠以一定的間隔設置，因此，每個功率裝置僅具有一些焊線分部越過接觸墊。雖然提供 每個接觸墊多條焊線有助於分配電流，在互連結構中的電阻仍會造成無法避免的損失。
雖然目前已經嘗試解決上述與銅至銅打線接合有關的問題，例如，透過優化接觸墊的銅材料特性，以及調整銅墊的厚度，在此領域中，仍有進一步改善的空間。
因此，以下將敘述所提供的功率覆蓋結構，此功率覆蓋結構允許使用銅焊線而不需要將功率裝置的接觸墊的金屬積覆改變成銅。同時也可期望具有用於製造可減少由於在打線接合製程中所施加之應力而造成裝置損壞的打線接合形式的輸入/輸出互連，進而增加製程的產能，以及提供自功率裝置至焊線的有效電流分佈。
依據本發明之一方面，功率覆蓋結構包含功率裝置，具有設置在功率裝置的上表面上的至少一上接觸墊，以及功率覆蓋互連層，具有耦接至功率裝置的上表面的介電層，以及具有金屬互連的金屬化層，金屬互連延伸通過通過介電層而形成的通孔，以及電性耦接至功率裝置的至少一上接觸墊。功率覆蓋結構也包含直接耦接至金屬化層的至少一銅焊線。
依據本發明之另一方面，製造功率覆蓋結構的方法包含提供包括複數個半導體裝置的晶圓，耦接介電層至每個該等半導體裝置的上表面，形成複數個通過介電 層的通孔以便暴露半導體裝置的至少一接觸墊，以及形成金屬化層在介電層的上表面上，金屬化層具有延伸通過通孔且與半導體裝置的至少一接觸墊電性耦接的金屬互連。此方法更包含耦接至少一焊線至金屬化層的頂表面。
依據本發明之又一方面，功率覆蓋組合包含第一半導體裝置、第二半導體裝置以及功率覆蓋互連組合，功率覆蓋互連組合具有聚醯亞胺膜，黏著地耦接至第一半導體裝置及第二半導體裝置的上接觸墊，以及金屬化路徑，形成在聚醯亞胺膜上，金屬化路徑包括複數個金屬互連，金屬互連延伸通過通過聚醯亞胺膜而形成的通孔，且電性耦接至第一半導體裝置及第二半導體裝置的上接觸墊。功率覆蓋組合也包含複數個銅焊線，直接耦接至金屬化路徑，其中，複數個銅焊線的第一焊線電性耦接至第一半導體裝置的上接觸墊，以及其中，複數個銅焊線的第二焊線電性耦接至第二半導體裝置的上接觸墊。
藉由以下本發明較佳的實施例的詳細說明，結合附加的圖式，這些及其它優點和特徵將被更容易地理解。
10‧‧‧功率封裝結構
12‧‧‧半導體裝置
14‧‧‧接觸墊
16‧‧‧接觸墊
18‧‧‧上表面
20‧‧‧焊線
22‧‧‧焊線
24‧‧‧焊線
26‧‧‧集極墊
28‧‧‧下表面
30‧‧‧焊料
32‧‧‧基板
34‧‧‧功率覆蓋結構
36‧‧‧晶圓
38‧‧‧半導體裝置(半導體晶粒)
40‧‧‧半導體裝置(半導體晶粒)
42‧‧‧半導體裝置(半導體晶粒)
44‧‧‧上接觸墊(閘極墊)
46‧‧‧上接觸墊(射極墊)
48‧‧‧上接觸墊(閘極墊)
50‧‧‧上接觸墊(射極墊)
52‧‧‧上接觸墊(閘極墊)
54‧‧‧上接觸墊(射極墊)
56‧‧‧上表面
58‧‧‧上表面
60‧‧‧上表面
62‧‧‧下接觸墊(集極墊)
64‧‧‧下接觸墊(集極墊)
66‧‧‧下接觸墊(集極墊)
68‧‧‧下表面
70‧‧‧下表面
72‧‧‧下表面
74‧‧‧介電層
76‧‧‧黏著層
78‧‧‧通孔
80‧‧‧金屬化層(金屬化路徑)
82‧‧‧上表面
84‧‧‧金屬互連的第一部分
86‧‧‧金屬互連的第二部分
88‧‧‧功率覆蓋互連層
90‧‧‧功率覆蓋結構
92‧‧‧功率覆蓋結構
94‧‧‧功率覆蓋結構
96‧‧‧焊線
98‧‧‧焊線
100‧‧‧焊線
102‧‧‧表面接觸區域
104‧‧‧表面接觸區域
106‧‧‧多層基板
108‧‧‧焊料
110‧‧‧非有機陶瓷基板
112‧‧‧薄片
114‧‧‧薄片
116‧‧‧厚度
118‧‧‧厚度
120‧‧‧厚度
122‧‧‧部分
124‧‧‧部分
126‧‧‧部分
128‧‧‧接觸表面
130‧‧‧接觸表面
132‧‧‧接觸表面
134‧‧‧功率覆蓋結構
136‧‧‧井
138‧‧‧通孔
140‧‧‧表面區域
142‧‧‧表面區域
144‧‧‧金屬互連
146‧‧‧上接觸表面
148‧‧‧表面區域
150‧‧‧接觸表面
152‧‧‧上表面
154‧‧‧部分
156‧‧‧功率覆蓋結構
158‧‧‧部分
160‧‧‧部分
162‧‧‧接觸位置
164‧‧‧接觸位置
166‧‧‧功率覆蓋互連層
168‧‧‧晶圓
170‧‧‧半導體裝置
172‧‧‧半導體裝置
174‧‧‧可移除支撐結構
176‧‧‧上接觸墊
178‧‧‧上接觸墊
180‧‧‧上接觸墊
182‧‧‧上接觸墊
184‧‧‧下接觸墊(集極墊)
186‧‧‧下接觸墊(集極墊)
188‧‧‧厚度
190‧‧‧厚度
192‧‧‧填隙片
194‧‧‧上表面
196‧‧‧上表面
200‧‧‧介電層
202‧‧‧黏著劑
204‧‧‧黏著劑
206‧‧‧空隙
208‧‧‧功率覆蓋互連層
210‧‧‧介電層
212‧‧‧第一部分
214‧‧‧第一厚度
216‧‧‧第二部分
218‧‧‧第二厚度
220‧‧‧臺階
222‧‧‧通孔
224‧‧‧金屬化路徑
226‧‧‧上表面
228‧‧‧金屬互連
230‧‧‧金屬互連
232‧‧‧功率覆蓋組合(晶圓)
234‧‧‧功率覆蓋組合
236‧‧‧功率覆蓋結構
238‧‧‧功率覆蓋組合
240‧‧‧焊線
242‧‧‧焊線
244‧‧‧接觸墊
246‧‧‧半導體裝置
圖式說明目前預期用於實現本發明的實施例。
在圖式中：圖1為依據現有技術之打線接合的功率封裝 結構之示意性截面側視圖。
圖2至圖6為根據本發明之一實施例，在製造功率覆蓋(POL)結構之多個階段中的示意性截面側視圖。
圖7為依據本發明的另一實施例，圖6之一結合焊線的功率覆蓋結的示意性截面側視圖。
圖8及圖9為依據本發明的替代實施例，帶有焊線的功率覆蓋結構之示意性上視圖及截面側視圖。
圖10及圖11為依據本發明的又一實施例，帶有焊線的功率覆蓋結構之示意性上視圖及截面側視圖。
圖12為依據本發明之一實施例，顯示結合功率覆蓋結構而再組成的晶圓之示意性截面側視圖。
圖13為依據本發明之另一實施例，顯示結合功率覆蓋結構而再組成的晶圓之示意性截面側視圖。
圖14為依據本發明之一實施例，功率覆蓋組合之示意性截面側視圖。
圖15為依據本發明之另一實施例，功率覆蓋組合之示意性截面側視圖。
本發明之實施例提供包含功率覆蓋互連層的功率覆蓋(POL)結構，以及形成此功率覆蓋結構的方法。本文所使用的用詞「功率覆蓋」描述不管功率裝置的接觸墊之材料類型為何，皆能夠進行銅打線接合的結構。 功率覆蓋互連層允許銅焊線至功率覆蓋結構的可靠連接，不論閘極及射極墊的材料。除此之外，功率覆蓋互連層設計用以作為應力緩衝之功能，用以在附接焊線至裝置接觸墊的製程中，減少對功率裝置的損害。藉由提供平行路徑，使電流在進入焊線前流過功率裝置的金屬積覆，本文所揭露的功率覆蓋結構相較於現有技術的打線接合功率裝置，具有降低的互連電阻以及損耗。
圖2至圖6描述根據本發明之一實施例，用以製造功率覆蓋結構34之技術。圖2至圖6之每一者描繪在建立製程中的功率覆蓋結構34之截面圖。首先參照圖2，顯示晶圓36。依據一實施例，晶圓36包含複數個半導體晶粒或半導體裝置38、40、42。半導體裝置38、40、42為功率裝置，作為非限制性的例子，例如為絕緣閘雙極電晶體(insulated gate bipolar transistor；IGBT)、金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor；MOSFET)、雙極接面電晶體(bipolar junction transistor；BJT)、積體閘換向閘流體(integrated gate-commutated thyristor；IGCT)、閘門關斷(gate turn-off；GTO)閘流體、矽控整流器(Silicon Controlled Rectifier；SCR)、二極體或其他裝置、或包含例如為矽(Si)、碳化矽(SiC)、氮化鎵(GaN)、砷化鎵(GaAs)之材料的裝置組合。雖然圖2顯示晶圓36具有三個半導體裝置38、40、42，可以考慮到地，晶圓36可能包含多於三或少於三個的半導體 裝置。
每個半導體裝置38、40、42可包含一或更多上接觸墊44、46、48、50、52、54，設置在半導體裝置38、40、42之各自的上表面56、58、60上。這些上接觸墊44至54提供至每個半導體裝置38、40、42中的內部接點的導電路徑。在所述的實施例中，每個半導體裝置38、40、42包含一對上接觸墊，耦接至半導體裝置38、40、42之相應的射極及/或閘極或陽極區域。在一實施例中，半導體裝置38、40、42為IGBT，具有分別耦接至半導體裝置38、40、42之各自的射極區域及閘極區域的接觸墊44至54。特別地，半導體裝置38包含閘極墊44及射極墊46，半導體裝置40包含閘極墊48及射極墊50，以及半導體裝置42包含閘極墊52及射極墊54。可以考慮到地，半導體晶粒38、40、42可提供具有不同於上述數量的接觸墊及/或不同於上述的接觸墊組合。以非限制性的範例為例，半導體晶粒38可提供具有一對的射極墊。在一實施例中，接觸墊44、46、48包括鋁。然而，可以考慮到地，接觸墊44、46、48可由其他類型的導電材料形成，例如，舉例而言，銅。每個半導體裝置38、40、42還包含至少一設置在半導體裝置38、40、42各自的下表面68、70、72上的下接觸墊或集極墊62、64、66。
如圖3所示，功率覆蓋結構34之製造起始於使用黏著層76來耦接介電層74至半導體裝置38、40、 42的上表面56、58、60。依據多個實施例，介電層74可為穩定的、非流動層壓或薄膜之形式，並且可以複數個介電材料之一者來形成，複數個介電材料例如為Kapton®、Ultem®、聚四氟乙烯(PTFE)、Upilex®、聚碸材料(例如Udel®、Radel®)，或其他聚合物薄膜，例如液晶聚合物(LCP)或聚醯亞胺材料。在一實施例中，介電層74可在框架(圖未示)上進行拉伸，以控制在製造程序中的變形。在使用常用的拾起及放置裝置及方法將晶圓36放進黏著層76之後，可使用旋塗技術將黏著層76施加至介電層74。
雖然圖3描述功率覆蓋結構34具有分開的介電及黏著層74、76，可以考慮到地，在替代的實施例中，層74、76可以具有黏著特性的單一介電層來取代。上述黏著介電層之非限制性的例子包含旋塗式介電質，例如聚醯亞胺或聚苯並噁唑(PBO)。
現在參照圖4，複數個通孔78通過介電層74及黏著層76而形成，用以暴露每個半導體裝置38、40、42的接觸墊44、46、48。通孔78可藉由例如雷射鑽孔或乾蝕刻來形成，但不以此為限。如圖5所示，在製造程序的下一步驟中，金屬化路徑或金屬化層80形成在介電層74的上表面82上。金屬化層80包含金屬互連的第一部分84，其延伸通過通孔78且電性耦接至半導體裝置38、40、42的接觸墊44、48、52，以及金屬互連的第二部分86，其延伸通過通孔78且電性耦接至半導體裝置 38、40、42的接觸墊46、50、54。在一較佳的實施例中，金屬化路徑80包括一層銅。然而，可以考慮到地，製造技術可以延伸使用在金屬化路徑80的其他導電材料。在一實施例中，金屬化路徑80可使用濺鍍及電鍍技術，以及隨後的微影製程來形成。金屬化路徑80、通孔78、介電層74以及黏著層76一起形成功率覆蓋互連層88。
現在參照圖6，功率覆蓋結構34被鋸開或被切割分離而成為個別的功率覆蓋結構90、92、94。每個功率覆蓋結構90、92、94包含各自的具有部分功率覆蓋互連層88接合在其上的半導體裝置38、40、42。由於晶圓36可能包含多於三或少於三個的半導體裝置38、40、42，因此也可以考慮到地，功率覆蓋結構34可被分成多於三或少於三個的功率覆蓋結構90、92、94。
現在參照圖7，功率覆蓋結構34被鋸開或被切割分離成個別的功率覆蓋結構90、92、94之後，在製造技術的下一步驟中，一或更多的焊線耦接至金屬化路徑80。在所述的實施例中，藉由打線接合製程，焊線96、98耦接至金屬化路徑80的金屬互連86，且焊線100接合至金屬互連84。然而，可以考慮到地，替代實施例可將多於二或少於二個的焊線接合至金屬互連的第二部分86及/或將多於一個的焊線100接合至金屬互連的第一部分84。依據本發明之一示範性實施例，焊線96、98、100為銅。
在一實施例中，比起焊線100，焊線96、98具有較大尺寸或較大直徑，因此，允許焊線96、98以較低的電阻處理流經接觸墊46之較大量的電流。以非限制性的範例為例，焊線96、98可提供做為具有約10至20密耳(mils)之直徑的「粗的」銅焊線。同時，焊線100可提供做為相對於焊線96、98之「細的」銅焊線，具有例如約3至10密耳之範圍的直徑。在本發明之此非限制性的實施例中，粗的焊線96、98與金屬化路徑80之間的表面接觸區域102可約為50密耳乘以80密耳。另一方面，舉例而言，細尺寸的焊線100與金屬化路徑80之間的表面接觸區域104可在約10至15密耳乘以20密耳之範圍。在本發明一示範性實施例中，表面接觸區域102、104的寬度為個別的焊線96、98、100之直徑的兩至三倍，且表面接觸區域102、104的長度為個別的焊線96、98、100之直徑的四至五倍。然而，所屬技術領域中具有通常知識者將認可，本發明之實施例不限制焊線96、98、100為特定之線尺寸，且焊線96、98、100的尺寸或直徑可依給予之應用的需求而變化，而對應的表面接觸區域也會相應的改變。
多層基板106透過焊料108而熱及電性耦接至半導體裝置38的接觸墊62。在一實施例中，多層基板106為預先製造的直接接合銅(DBC)組件，其包含非有機陶瓷基板110，舉例而言，例如為礬土、氮化鋁、氮化矽等，帶有透過直接接合銅介面或銅焊層接合在兩側的上 及下銅的薄片112、114。在本發明之另一實施例中，可以考慮到地，多層基板106可以是直接接合鋁(DBA)基板，具有上及下鋁的薄片112、114。
雖然圖7及隨後的圖式描述多層基板106，其熱及電性耦接至接觸墊62，可以考慮到地，替代的實施例可包含單層基板，舉例而言，例如以引線框代替多層基板106。
如圖7所示，半導體裝置38具有大約50至500微米的厚度116。除此之外，金屬化路徑80的厚度118約在5至150微米範圍，而介電層74的厚度120可約為0.5至2密耳。
在圖7描述的實施例中，每條焊線96、98、100耦接至功率覆蓋互連層88之包含至少一金屬互連84、86或部分金屬互連84、86的個別部分122、124、126。特別地，功率覆蓋互連層88的部分126在焊線100的接觸表面128之下包含一個金屬互連84，並且，功率覆蓋互連層88的部分122、124在焊線96、98個別的接觸表面130、132之下各自包含至少兩個金屬互連86之部分。金屬互連86因此形成供電流自半導體裝置38流進焊線96、98的多平行路徑。
圖8及圖9描述依據本發明之另一實施例之功率覆蓋結構134中的焊線96的位置。在本文中，功率覆蓋結構134及功率覆蓋結構34之共同的元件及組件參照適當的相同的元件符號。如所示，焊線96位於形成在 介電層74的凹處或井136內。井136藉由在黏著層76內建立大的通孔138而形成，且介電層74暴露的接觸墊46的部分具有大於焊線96之表面區域142的表面區域140。當建立金屬化路徑80，金屬化路徑80延伸進入通孔138且形成具有相對平面的上接觸表面146的金屬互連144。上接觸表面146的表面區域148大於相應的焊線96的表面區域142。因此，焊線96的接觸表面150位於金屬化路徑80的上表面152的下方。在此實施例中，金屬化路徑80直接接觸接觸墊46而沒有任何黏著層76或介電層74之部分位於兩者之間，如圖9所示。因此，功率覆蓋結構134之在焊線96的接觸表面150之下的部分154實質上沒有任何介電層74或黏著層76之部分。在此實施例中，增加的金屬化路徑80及接觸墊46之表面區域減少在接觸墊46與焊線96之間的電流路徑中的電阻。
在另一實施例中，可以考慮到地，當金屬化路徑80藉由延伸進入通孔138而建立並形成金屬互連144時，平面的上接觸表面146及金屬化路徑80的上表面152為共平面。例如，焊線96設置為與金屬化路徑80的上表面152相同的高度。在此實施例中，功率覆蓋結構134在焊線96之接觸表面150之下的部分154仍然實質上沒有任何介電層74或黏著層76之部分。
現在參照圖10及圖11，依據本發明另一實施例描繪功率覆蓋結構156。再次說明，功率覆蓋結構156及功率覆蓋結構34之共同的元件參照適當的相同的元件 符號。如所示，焊線96、100耦接至在功率覆蓋結構156中沒有通孔78之部分的金屬化路徑80。因此，在此實施例中，沒有任何的通孔78位於直接設置於焊線96、100個別的接觸位置162、164下方的介電層74的部分158、160中。介電層74在功率覆蓋結構156於焊線96、100下方的部分的厚度120實質上一致，且用做為應力緩衝，以降低在打線接合程序中，可能對半導體裝置38造成的損害。
雖然以上在圖7至圖11中描述的焊線96、98、100以及DBC基板106為耦接至個別的半導體裝置38，可以考慮到地，DBC基板106及/或焊線96、98、100可施加至在晶圓級(也就是，分割前)的各個半導體裝置38、40、42。
在另一實施例中，功率覆蓋互連層166可同時地形成在提供在封裝或再組成的晶圓中的多個個別的半導體裝置上。現在參照圖12，所示的再組成的晶圓168具有複數個耦接至可移除支撐結構174的半導體裝置170、172。所屬技術領域中具有通常知識者將認可，在替代實施例中，再組成的晶圓168可包含多於兩個的半導體裝置170、172。相似於圖2至圖6的半導體裝置38、40、42，半導體裝置170、172包含複數個上接觸墊176、178、180、182以及至少一個下接觸墊或集極墊184、186。上接觸墊176至182可包括射極及/或閘極墊的多種組合。在一較佳的實施例中，上接觸墊176至182 為鋁或銅。然而，可以考慮到地，上接觸墊176至182可包括替代金屬積覆材料。
如圖12所示，半導體裝置170、172有不同的厚度188、190，半導體裝置170的厚度188大於半導體裝置172的厚度190。考量上述厚度的差異，填隙片192可設置在較薄的半導體裝置與可移除支撐結構174之間，使得晶圓168中半導體裝置170的接觸墊176、178的上表面194與半導體裝置172的接觸墊180、182的上表面196實質上共平面。
一旦半導體裝置170、172的上表面194至196設置為實質上共平面，功率覆蓋互連層166以如圖3至5所述相同的方式形成在半導體裝置170、172頂上。施加介電層200至半導體裝置170、172，可以考慮到地，單一黏著層可以如介電層74(圖3)所述的方式旋塗在介電層200上，或是黏著劑202、204之個別的層可形成在每個半導體裝置170、172頂上，如圖11所示。在任一情況下，介電層200設置用以跨越相鄰的半導體裝置170、172之間的空隙206。依據多個實施例，介電層200可以是層壓或薄膜之形式，且可以由複數個介電材料中的一種形成，相同於介電層74。
在本發明替代一實施例中，半導體裝置170、172透過各自的黏著層202、204(或單一黏著層)耦接至介電層200。相對於施加介電層200至半導體裝置170、172，在此，藉由放置半導體裝置170、172在黏著層 202、204上而使半導體裝置170、172耦接至介電層200。如此，可以省略可移除支撐結構174。
在本發明另一實施例中，描述於圖13中，功率覆蓋互連層208可形成為具有建構用以補償半導體裝置170、172之不同的厚度188、190的介電層210。如所示，與半導體裝置170對準的介電層210的第一部分212具有第一厚度214，以及與半導體裝置172對準的介電層210的第二部分216具有第二厚度218。臺階220設置在第一部分212與第二部分216之間的過渡部分。在本發明的又一實施例中，半導體裝置170、172之不同的高度可藉由黏著層202、204之不同的厚度來補償。
同時參照圖12及圖13，為了完成每個功率覆蓋互連層166，複數個通孔222通過介電層200及黏著層202、204而形成，用以暴露接觸墊176、178、180、182。接著，金屬化路徑224形成在介電層200的上表面226上。金屬化路徑224包含延伸通過通孔222且電性耦接接觸墊176、180的金屬互連228，以及延伸通過通孔222且電性耦接接觸墊178、182、214的金屬互連230。金屬化路徑224可包括一層銅，且可使用濺鍍及電鍍技術，以及隨後的微影製程來形成。
以下形成功率覆蓋互連層166或功率覆蓋互連層208，如果需要，支撐結構174及任何的填隙片192可以被移除。每個所得的功率覆蓋組合232、234可接著被鋸開或被切割分離而成為個別的具有一個或多個的半導 體裝置的功率覆蓋結構。其中，所得的功率覆蓋結構包含多個半導體晶粒，介電層200、210居於空隙206中之部分可被移除，例如藉由雷射燒蝕，或被保留以提供功率覆蓋結構額外的結構剛性。焊線可以相同於任何在圖7至圖11中所述的方式，在分割前或分割後耦接至金屬互連228、230。
現在參照圖14，根據本發明的另一實施例，在功率覆蓋組合238中，所示的已分割的功率覆蓋結構90電性耦接至另一個功率覆蓋結構236。如所示，每個功率覆蓋結構90、236包含各自的功率覆蓋互連層88，各自的功率覆蓋結構90、236的焊線96、100、240、242耦接至各自的功率覆蓋互連層88。焊線96、240電性耦接半導體裝置38的接觸墊46與半導體裝置246的接觸墊244。雖然圖14顯示功率覆蓋結構90、236為具有不同的高度，可以考慮到地，功率覆蓋結構90、236可具有相同的高度。
在一實施例中，功率覆蓋結構90、236為熱耦接至相同的多層基板106，如圖14所示。然而，所屬技術領域中具有通常知識者將認可，功率覆蓋結構90、236可熱耦接至分別的多層基板106。除此之外，可以考慮到地，在替代實施例中，多層基板106可以是DBC基板或DBA基板。
接著，圖15顯示功率覆蓋組合238的另一實施例，其中，相對於圖14所述的分割的功率覆蓋結構 90、236，替換為具有至少兩個半導體裝置170、172的再組成的晶圓232。如所示，功率覆蓋互連層166跨越半導體裝置170、172兩者的面向上的表面而形成，並且橫跨半導體裝置170、172之間的空隙。雖然圖15描述半導體裝置170、172為熱耦接至相同的多層基板106，可以考慮到地，每個半導體裝置170、172可耦接至其自身的分離的多層基板106。
焊線96、100、240、242耦接至功率覆蓋互連層166。在此實施例中，金屬化路徑224電性連接功率覆蓋組合238的半導體裝置170、172的接觸墊176、178、180、182。如此一來，半導體裝置170、172可電性耦接至彼此而不需焊線96、240之間的直接連接。焊線96、240因而可用於電性耦接功率覆蓋組合238至其他的功率覆蓋組合。
有益地，本發明的實施例提供功率覆蓋結構，其可以允許銅打線接合，不管半導體裝置的接觸墊的材料。功率覆蓋互連層提供銅金屬化路徑，也就是電性連接至半導體裝置的接觸墊，並且因此形成銅焊線可以可靠地接合至其的接觸表面。如此可允許在包含有不同類型的功率裝置(具有不同的金屬化層，舉例而言，例如銅及鋁接觸墊)的功率覆蓋模組中使用銅焊線。
所得的功率覆蓋結構也提供比現有技術之結構更有效率的自半導體功率裝置至焊線的電流分佈。金屬化互連結構提供在功率覆蓋互連層中，其提供平行路徑， 用以提供電流在進入焊線之前，流經薄的功率裝置的接觸墊的金屬積覆。
此外，功率覆蓋互連層的厚度形成在焊線與功率裝置之間的保護緩衝層，其保護功率裝置不受與銅至銅打線接合相關聯的相較於鋁至鋁打線接合更高的能量之傷害。由於功率覆蓋互連層作為用於在打線接合程序時，功率裝置的應力緩衝，焊線具有比習知所使用的銅至銅打線接合還大的尺寸，因此可電性耦接至功率裝置而沒有損害裝置的風險。這些較大尺寸的焊線更減少了功率裝置與焊線之間的互連電阻以及相關損失。
因此，依據本發明的一實施例，功率覆蓋(POL)結構包含功率裝置，具有設置在功率裝置的上表面上的至少一上接觸墊，以及功率覆蓋互連層，具有耦接至功率裝置的上表面的介電層以及具有金屬互連的金屬化層，金屬互連延伸通過通過介電層而形成的通孔並且電性耦接至功率裝置的至少一上接觸墊。功率覆蓋結構更包含至少一銅焊線，直接耦接至金屬化層。
依據本發明另一方面，製造功率覆蓋結構的方法包含提供包括複數個半導體裝置的晶圓，耦接介電層至複數個半導體裝置之各者的上表面，形成複數個通過介電層的通孔以便暴露複數個半導體裝置的至少一接觸墊，以及形成金屬化層在介電層的上表面上，金屬化層具有延伸通過複數個通孔且與複數個半導體裝置的至少一接觸墊電性耦接的金屬互連。此方法更包含耦接至少一焊線至金 屬化層的上表面。
依據本發明之又一方面，功率覆蓋組合包含第一半導體裝置、第二半導體裝置以及功率覆蓋互連組合，功率覆蓋互連組合具有聚醯亞胺膜，黏著地耦接至第一半導體裝置及第二半導體裝置的上接觸墊，以及金屬化路徑，形成在聚醯亞胺膜上，金屬化路徑包括複數個金屬互連，金屬互連延伸通過通過聚醯亞胺膜而形成的通孔，且電性耦接至第一半導體裝置及第二半導體裝置的上接觸墊。功率覆蓋組合也包含複數個銅焊線，直接耦接至金屬化路徑，其中，複數個銅焊線的第一焊線電性耦接至第一半導體裝置的上接觸墊，以及其中，複數個銅焊線的第二焊線電性耦接至第二半導體裝置的上接觸墊。
雖然本發明已經以有限的實施例而詳細的描述，應該容易理解的是，本發明並不限於這些揭示的實施例。相反地，本發明可以被修改以結合之前未描述但與本發明的精神和範圍相應的任何數量的變化、變更、替換或等同配置。除此之外，雖然本發明的各種實施例已被描述，但是應當理解，本發明的各方面可僅包括所述實施例的部分。因此，本發明不應被視為由前述描述來限制，而是僅由所附申請專利範圍的範圍來限制。
38‧‧‧半導體裝置(半導體晶粒)
44‧‧‧上接觸墊(閘極墊)
46‧‧‧上接觸墊(射極墊)
62‧‧‧下接觸墊(集極墊)
74‧‧‧介電層
76‧‧‧黏著層
80‧‧‧金屬化層(金屬化路徑)
84‧‧‧金屬互連的第一部分
86‧‧‧金屬互連的第二部分
88‧‧‧功率覆蓋互連層
90‧‧‧功率覆蓋結構
96‧‧‧焊線
98‧‧‧焊線
100‧‧‧焊線
102‧‧‧表面接觸區域
104‧‧‧表面接觸區域
106‧‧‧多層基板
108‧‧‧焊料
110‧‧‧非有機陶瓷基板
112‧‧‧薄片
114‧‧‧薄片
116‧‧‧厚度
118‧‧‧厚度
120‧‧‧厚度
122‧‧‧部分
124‧‧‧部分
126‧‧‧部分
128‧‧‧接觸表面
130‧‧‧接觸表面
132‧‧‧接觸表面

Claims (23)

  1. 一種功率覆蓋(POL)結構，包括：功率裝置，具有設置在該功率裝置的上表面上的至少一上接觸墊；功率覆蓋互連層，包括：介電層，耦接至該功率裝置的該上表面；以及金屬化層，具有金屬互連，該金屬互連延伸通過通過該介電層而形成的通孔並且電性耦接至該功率裝置的該至少一上接觸墊；以及至少一銅焊線，直接耦接至該金屬化層。
  2. 根據申請專利範圍第1項之功率覆蓋結構，其中，該至少一上接觸墊包括鋁。
  3. 根據申請專利範圍第1項之功率覆蓋結構，更包括多層基板，以焊料層而熱及電性耦接至該功率裝置的下接觸墊，該多層基板包括直接接合銅(DBC)基板和直接接合鋁(DBA)基板之一者。
  4. 根據申請專利範圍第1項之功率覆蓋結構，其中，該介電層在該至少一銅焊線的接觸位置之下具有實質上一致的厚度。
  5. 根據申請專利範圍第1項之功率覆蓋結構，其中，該介電層透過黏著層耦接至該功率裝置的該上表面。
  6. 根據申請專利範圍第1項之功率覆蓋結構，其中，設置在該焊線的接觸表面與該功率裝置之間的該功率覆蓋互連層之部分係缺少該介電層。
  7. 根據申請專利範圍第1項之功率覆蓋結構，更包括：金屬互連，具有位於該金屬化層的頂表面之下的上接觸表面；以及銅焊線，耦接至該金屬互連的該上接觸表面；其中，該銅焊線的接觸表面的表面區域小於該金屬互連的該上接觸表面的表面區域。
  8. 根據申請專利範圍第1項之功率覆蓋結構，其中，該至少一焊線的接觸表面耦接至該功率覆蓋互連層之具有金屬化互連之部分。
  9. 一種製造功率覆蓋(POL)結構的方法，包括：提供包括複數個半導體裝置的晶圓；耦接介電層至每個該等半導體裝置的上表面；形成複數個通過該介電層的通孔以便暴露該等半導體裝置的至少一接觸墊；形成金屬化層在該介電層的上表面上，該金屬化層具有延伸通過該等通孔且與該等半導體裝置的該至少一接觸墊電性耦接的金屬互連；以及耦接至少一焊線至該金屬化層的上表面。
  10. 根據申請專利範圍第9項之方法，其中，耦接該介電層至每個該等半導體裝置的該上表面包含設置黏著層在該介電層與該等半導體裝置的該上表面之間。
  11. 根據申請專利範圍第9項之方法，更包括分割該晶圓以成為複數個功率覆蓋結構，每個該等功率覆蓋結構 包括至少一具有部分該介電層及部分該金屬化層形成在上的半導體裝置。
  12. 根據申請專利範圍第9項之方法，更包括：形成通孔以便暴露大於該至少一焊線之表面區域的接觸墊之表面區域；以及耦接該至少一焊線至形成在該通孔內的金屬互連。
  13. 根據申請專利範圍第9項之方法，更包括耦接該至少一焊線至該金屬化層之沒有金屬互連的部分。
  14. 根據申請專利範圍第9項之方法，更包括，在耦接該介電層至該等半導體裝置的該上表面之前，耦接可移除的支撐結構至該等半導體裝置的下表面。
  15. 根據申請專利範圍第9項之方法，更包括耦接該介電層至該晶圓的第一半導體裝置及第二半導體裝置，該第一半導體裝置具有大於該第二半導體裝置之厚度的厚度。
  16. 根據申請專利範圍第15項之方法，更包括定位該第一半導體裝置與該第二半導體裝置有距離，使得該第一半導體裝置與該第二半導體裝置之間形成有空隙。
  17. 根據申請專利範圍第15項之方法，更包括設置填隙片在該支撐結構與該第二半導體裝置的該下表面之間，使得該第一半導體裝置的上表面實質上與該第二半導體裝置的上表面共平面。
  18. 根據申請專利範圍第15項之方法，更包括：耦接該介電層的第一部分至該第一半導體裝置；以及 耦接該介電層的第二部分至該第二半導體裝置，其中該介電層的該第二部分之厚度大於該介電層的該第一部分之厚度。
  19. 一種功率覆蓋(POL)組合，包括：第一半導體裝置及第二半導體裝置；功率覆蓋互連組合，包括：聚醯亞胺膜，黏著地耦接至該第一半導體裝置及該第二半導體裝置的上接觸墊；以及金屬化路徑，形成在該聚醯亞胺膜上，該金屬化路徑包括複數個金屬互連，該等金屬互連延伸通過通過該聚醯亞胺膜而形成的通孔，且電性耦接至該第一半導體裝置及該第二半導體裝置的該上接觸墊；以及複數個銅焊線，直接耦接至該金屬化路徑；其中，該等銅焊線的第一焊線電性耦接至該第一半導體裝置的上接觸墊；以及其中，該等銅焊線的第二焊線電性耦接至該第二半導體裝置的上接觸墊。
  20. 根據申請專利範圍第19項之功率覆蓋組合，其中，該第一功率覆蓋結構的該至少一銅焊線電性耦接至該第二功率覆蓋結構的該至少一銅焊線。
  21. 根據申請專利範圍第19項之功率覆蓋組合，其中，該第一半導體裝置之厚度不同於該第二半導體裝置之厚度；以及其中，該功率覆蓋組合包括至少一具有可變厚度的聚 醯亞胺膜，以及耦接至該第一半導體裝置及該第二半導體裝置之一者的底表面之填隙片。
  22. 根據申請專利範圍第19項之功率覆蓋組合，其中，該第一焊線耦接至該功率覆蓋互連組合實質上沒有該聚醯亞胺膜的部分。
  23. 根據申請專利範圍第19項之功率覆蓋組合，其中，該第一焊線耦接至該功率覆蓋互連組合之部分，其中該聚醯亞胺膜具有實質上一致的厚度。
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