CN108231728A - 半导体器件、电子组件及方法 - Google Patents
半导体器件、电子组件及方法 Download PDFInfo
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- CN108231728A CN108231728A CN201711318207.3A CN201711318207A CN108231728A CN 108231728 A CN108231728 A CN 108231728A CN 201711318207 A CN201711318207 A CN 201711318207A CN 108231728 A CN108231728 A CN 108231728A
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- layer
- metal
- semiconductor devices
- contact pad
- barrier coating
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000011469 building brick Substances 0.000 title claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 179
- 239000002184 metal Substances 0.000 claims abstract description 179
- 239000000758 substrate Substances 0.000 claims abstract description 80
- 238000000576 coating method Methods 0.000 claims abstract description 77
- 239000011248 coating agent Substances 0.000 claims abstract description 76
- 230000008054 signal transmission Effects 0.000 claims abstract description 28
- 238000000926 separation method Methods 0.000 claims description 85
- 238000002161 passivation Methods 0.000 claims description 65
- 230000001939 inductive effect Effects 0.000 claims description 58
- 238000004873 anchoring Methods 0.000 claims description 34
- 230000002093 peripheral effect Effects 0.000 claims description 23
- 239000010949 copper Substances 0.000 claims description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 18
- 229910052802 copper Inorganic materials 0.000 claims description 18
- 238000002955 isolation Methods 0.000 claims description 18
- 229910020776 SixNy Inorganic materials 0.000 claims description 12
- 230000005540 biological transmission Effects 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 230000008878 coupling Effects 0.000 claims description 10
- 238000010168 coupling process Methods 0.000 claims description 10
- 238000005859 coupling reaction Methods 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 10
- 230000011664 signaling Effects 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000002253 acid Substances 0.000 claims description 5
- 238000005984 hydrogenation reaction Methods 0.000 claims description 5
- 150000003949 imides Chemical class 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 239000005360 phosphosilicate glass Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- -1 Wherein Substances 0.000 claims 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 18
- 230000004888 barrier function Effects 0.000 description 17
- 238000010586 diagram Methods 0.000 description 17
- 238000009792 diffusion process Methods 0.000 description 14
- 238000001465 metallisation Methods 0.000 description 13
- 238000004804 winding Methods 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 230000002457 bidirectional effect Effects 0.000 description 9
- 238000000151 deposition Methods 0.000 description 9
- 230000005611 electricity Effects 0.000 description 9
- 238000004070 electrodeposition Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 230000008021 deposition Effects 0.000 description 8
- 229910052763 palladium Inorganic materials 0.000 description 8
- 230000002787 reinforcement Effects 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 4
- 230000001737 promoting effect Effects 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 238000009434 installation Methods 0.000 description 3
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000005728 strengthening Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004615 ingredient Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000008520 organization Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 208000025274 Lightning injury Diseases 0.000 description 1
- 229910001096 P alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000008521 reorganization Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
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- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/074—Stacked arrangements of non-apertured devices
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- H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
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Abstract
本发明公开了半导体器件、电子组件及方法。在一个实施例中,一种半导体器件包括包含接触衬垫的电流隔离信号传输耦合器。所述接触衬垫包括金属基底层,布置在金属基底层上的金属扩散屏障层,以及布置在金属扩散屏障层上的金属线可接合层。金属扩散屏障层包括第一部分和第二部分。第一部分具有第一表面以及与第一表面相对的第二表面。第一表面在外围处包括弯曲表面。第一部分在横向平面中延伸并且具有宽度。第二部分在第一部分的宽度的中间处从第二表面伸出。
Description
技术领域
本发明涉及半导体器件、电子组件及方法。
背景技术
在某些应用中,两个或更多电路例如通过双向信号交换进行通信。如果所述电路具有处于不同电位的接地,可以使用电流隔离(galvanic isolation)来防止所述电路之间的电流流动同时允许所述电路之间的通信。电流隔离例如可以基于光学、电容式或电感式通信。用于电感式电流隔离和信号交换的设备的一个示例是包括通过隔离层分开的初级绕组和次级绕组的空芯变换器,所述隔离层足够薄从而允许双向信号传输。
在其中从较高电压网络(诸如电网)向较低电压网络(诸如家庭供电网络)传输电力和信息的某些应用中,如果不是管理机构要求,针对高达10kV或更高的尖峰的加强电流隔离也是合期望的。
发明内容
在一个实施例中,一种半导体器件包括电流隔离信号传输耦合器,所述耦合器包括接触衬垫。所述接触衬垫包括金属基底层,布置在金属基底层上的金属扩散屏障层,以及布置在金属扩散屏障层上的金属线可接合层。金属扩散屏障层包括第一部分和第二部分。第一部分具有在外围处包括弯曲表面的第一表面以及与第一表面相对的第二表面。第一部分在横向平面中延伸并且具有宽度。第二部分在第一部分的宽度的中间处从第二表面伸出。
在某些实施例中,所述半导体器件还包括布置在金属基底层的外围区段上并且具有暴露金属基底层的一部分的第一开口的第一隔离层,其中金属扩散屏障层的第二部分布置在第一隔离层中的第一开口中并且金属扩散屏障层的第一部分延伸到第一隔离层的邻近第一开口的表面上。
在某些实施例中,所述半导体器件还包括金属线可接合层上的金属钝化层。
在某些实施例中,所述金属基底层包括铜,和/或金属扩散屏障层包括NiP,和/或金属线可接合层包括Pd和/或金属钝化层包括Au。
在某些实施例中,所述半导体器件还包括布置在金属线可接合层的外围区段上并且包括暴露金属线可接合层的一部分的第二开口的第二隔离层。金属钝化层可以布置在第二开口中并且由第二开口定界。
在某些实施例中,所述半导体器件还包括第三隔离层和第四隔离层,所述第三隔离层包括布置在第一隔离层上的环,所述第四隔离层布置在第三隔离层的外部面上。
在某些实施例中,第一隔离层包括氢化SixNy,并且第二隔离层包括酰亚胺。
在某些实施例中,第三隔离层包括SiOx或者磷硅酸玻璃,并且第四隔离层包括氢化SixNy。
在某些实施例中,电流隔离信号传输耦合器包括电感式耦合器,其包括耦合到接触衬垫的平面线圈。
在某些实施例中,电感式耦合器包括与第一平面线圈一起布置在堆叠中并且通过包括SiOx的隔离层与第一平面线圈电流隔离的第二平面线圈,并且被配置成提供针对至少10kVPEAK的浪涌脉冲隔离电压VIOSM的加强电流隔离。
在某些实施例中,所述半导体器件还包括第三平面线圈,其被布置成与第一平面线圈基本上共面并且耦合到接触衬垫。
在某些实施例中,平面线圈和金属基底层集成在半导体管芯中。
在某些实施例中,电流隔离信号传输耦合器包括电容式耦合器,并且接触衬垫提供所述电容式耦合器的板。
在一个实施例中,一种电子组件包括根据先前描述的实施例中的任何一个的半导体器件以及耦合到所述半导体器件的双向信号传输路径。电流隔离信号传输耦合器被耦合在所述双向信号传输路径中,并且通过接合线耦合到所述半导体器件。所述电流隔离信号传输耦合器提供针对至少10kVpeak的浪涌脉冲隔离电压VIOSM的加强电流隔离。
在某些实施例中,所述电子组件还包括通过双向信号传输路径耦合到所述半导体器件的另一个半导体器件。
在一个实施例中,一种用于形成接触衬垫的方法包括:将金属扩散屏障层沉积到在第一隔离层的第一开口中被暴露的金属基底层的表面上,所述第一隔离层覆盖金属基底层的外围区段,使得金属扩散屏障层延伸到第一隔离层的外表面上。金属扩散屏障层被退火,并且将金属线可接合层沉积到经过退火的金属扩散屏障层上。
在某些实施例中,使用电化学沉积或电流沉积来沉积所述金属扩散屏障层。
在某些实施例中,该方法还包括将第二隔离层沉积到金属线可接合层的外围区段上从而限定暴露线可接合层的一部分的第二开口。
在某些实施例中,该方法还包括将金属钝化层沉积到金属线可接合层上使得第二隔离层对金属钝化层进行定界。
在一个实施例中,一种半导体器件被提供,其包括包含接触衬垫的电流隔离信号传输耦合器。所述接触衬垫包括金属基底层和布置在金属基底层上的金属锚定层。金属锚定层包括第一部分和第二部分。第一部分具有第一表面和与第一表面相对的第二表面。第一部分的第一表面在外围处包括弯曲表面。第一部分在横向平面中延伸并且具有宽度。第二部分在第一部分的宽度的中间处从第二表面伸出。
在某些实施例中,金属锚定层和/或金属基底层包括铜。
在某些实施例中,所述半导体器件还包括布置在金属基底层的外围区段上并且具有暴露金属基底层的一部分的第一开口的第一隔离层,其中金属锚定层的第二部分被布置在第一隔离层中的第一开口中,并且金属锚定层的第一部分延伸到第一隔离层的邻近第一开口的表面上。
在某些实施例中,第一隔离层包括SiOx。
在某些实施例中,所述半导体器件还包括镶衬第一开口的金属粘附促进层。在某些实施例中,所述半导体器件还包括布置在金属锚定层的第一表面上的绝缘钝化层。
在某些实施例中,绝缘钝化层包括Al2O3或SixNy。在某些实施例中,第一隔离层包括SixNy。
在某些实施例中,金属锚定层与金属基底层,第一开口的侧壁和绝缘层的邻近第一开口的表面直接接触。
在某些实施例中,所述半导体器件还包括布置在金属锚定层上的一个或多个金属层。
在某些实施例中,一个或多个另外的金属层包括布置在锚定层的外表面上的NiP层、布置在NiP层上的Pd层以及布置在NiP层上的Au层。
在阅读下面的详细描述时并且在查看附图时,本领域技术人员将认识到另外的特征和优点。
附图说明
附图的元件不一定相对于彼此按比例。相似的参考数字指定相应的类似部件。除非其彼此排斥,否则各种图示的实施例的特征可以被组合。在附图中描绘出示例性实施例并且在后面的描述中对其进行详细描述。
图1a图示根据一个实施例的包括电流隔离信号传输耦合器的半导体器件,所述电流隔离信号传输耦合器包括接触衬垫。
图1b图示根据一个实施例的包括电流隔离信号传输耦合器的半导体器件,所述电流隔离信号传输耦合器包括电感式耦合器,所述电感式耦合器包括平面线圈和接触衬垫。
图1c图示根据一个实施例的包括电流隔离信号传输耦合器的半导体器件,所述电流隔离信号传输耦合器包括电容式耦合器,所述电容式耦合器包括接触衬垫。
图2图示根据一个实施例的包括电感式耦合器的半导体器件,所述电感式耦合器包括平面线圈和接触衬垫。
图3a图示用于电感式或电容式耦合器的接触衬垫。
图3b图示图3a的接触衬垫的放大视图。
图4图示根据一个实施例的用于电感式或电容式耦合器的连接结构。
图5图示根据一个实施例的用于电感式或电容式耦合器的连接结构。
图6a图示根据另一个实施例的用于电感式或电容式耦合器的接触衬垫。
图6b图示根据另一个实施例的用于电感式或电容式耦合器的接触衬垫。
图7是用于制作用于电感式或电容式耦合器的接触衬垫的方法的流程图。
图8a图示根据一个实施例的电感式耦合器的透视图。
图8b图示用于电感式耦合器的平面螺旋线圈的平面视图。
图8c图示用于电感式耦合器的平面螺旋线圈的平面视图。
图9a图示包括提供电流隔离和信号传输的电感式耦合器的系统的示意性电路图。
图9b图示包括提供电流隔离和信号传输的电容式耦合器的系统的示意性电路图。
图10图示包括提供电流隔离和信号传输的电感式耦合器的功率转换设备的示意图。
图11图示包括至少两个半导体器件的电子组件,所述半导体器件具有包括电感式耦合器的双向数据交换路径。
图12图示到图11的电感式耦合器的接触衬垫的连接结构的详细视图。
具体实施方式
在下面的详细描述中参考附图,所述附图形成本文的一部分,并且在其中通过图示的方式示出在其中可以实践本发明的具体实施例。在这方面,参考所描述的(一个或多个)附图的取向使用诸如“顶部”、“底部”、“正面”、“背面”、“在前”、“在后”等等的方向术语。因为实施例的组件可以被定位在若干不同的取向中,所以所述方向术语被用于说明的目的而绝不是进行限制。应当理解的是,在不脱离本发明的范围的情况下,可以利用其他实施例并且可以做出结构或逻辑上的改变。由此,下面的详细描述不应当以限制性含义来理解,并且本发明的范围由所附权利要求限定。
以下将解释若干示例性实施例。在这种情况下,完全相同的结构特征在附图中由完全相同或类似的参考符号标识。在本描述的上下文中,“横向”或“横向方向”以及“侧向”或“侧向方向”应当被理解成意味着总体上平行于半导体材料或半导体载体的侧向范围延伸的方向或范围。因此,侧向方向总体上平行于这些表面或侧面延伸。相比之下,术语“垂直”或“垂直方向”被理解成意味着总体上垂直于这些表面或侧面并且因此垂直于侧向方向延伸的方向。因此,垂直方向在半导体材料或半导体载体的厚度方向上延伸。
如在本说明书中所采用的那样,当诸如层、区段或基板之类的元件被称为“处于另一个元件上”或者“延伸到另一个元件上”时,该元件可以直接处于另一个元件上或者直接延伸到另一个元件上,或者还可以存在中间的元件。相比之下,当元件被称为“直接处于另一个元件上”或者“直接延伸到另一个元件上”时,则没有中间的元件存在。
如在本说明书中所采用的那样,当元件被称为“连接”或“耦合”到另一个元件时,该元件可以直接连接或耦合到另一个元件,或者可以存在中间的元件。相比之下,当元件被称为“直接连接”或“直接耦合”到另一个元件时,则没有中间的元件存在。
电力装备中的电流隔离指的是这样的布置,其中输出功率电路与输入功率电路通过电气和物理方式隔离,以便防止电流流动。仍然可以通过其他手段诸如电容、电感或电磁波,或者通过光学、声学或机械手段在所述电路之间交换能量或信息。例如在两个或更多电路将进行通信但是其接地处于不同的电位的场合,可以使用电流隔离。提供电流隔离的常见原因包括工业级产品和应用中的故障状况下的安全性,在所述工业级产品和应用中需要设备之间的通信但是每一个设备调节其自身的电力。
在某些电子系统中,控制功能由与高电力电路电流隔离的较低电压电路提供。较低电压电路与较高电压电路之间的双向信号路径例如可以被用来从系统控制器向供电装置传送控制数据,并且从供电装置接收监测数据。当高电力电路定义供电装置时,通常的工业实践或管理机构对于供电系统可能要求与大地或接地的高电压电气隔离。对于加强电流隔离,在这样的实践和规章中可以提到的工业标准的示例包括ICE-60747-5-5或VDE0884-11。对于基本电流隔离,可以提到的工业标准的一个示例是IEC 60664-1和VDE0884-11。
提供双向信号路径的一种方式是在其中感应地传送信号的变换器或电感式耦合器,其中所述双向信号路径在较高电压电路与较低电压电路之间提供电流隔离。
本文中所描述的实施例可以被用来提供用于使用在电感式耦合器以及包括电感式耦合器的至少一个线圈的设备中的连接结构,并且所述电感式耦合器具有接触衬垫,其在故障状况下更加稳健并且其在被使用时可以增加所述电感式耦合器或设备的操作寿命。电感式耦合器也可以被称作变换器。在某些实施例中,所述变换器是包括初级线圈和次级线圈的空芯变换器,所述初级线圈和次级线圈被定位成足够靠近在一起以便于可靠的数据交换,并且彼此足够隔离以提供电流隔离。所述初级线圈和次级线圈可以是被集成到可以包括另外的电路的半导体管芯中的平面线圈。
提供双向信号路径的另一种方式是在其中通过电容方式传送信号的电容式耦合器,其中所述双向信号路径在较高电压电路与较低电压电路之间提供电流隔离。
本文中所描述的实施例可以被用来提供用于使用在电容式耦合器中的连接结构。电容式耦合器可以包括通过电介质分开的两个导电板。电容式耦合器的两个导电板可以被集成到可以包括另外的电路的半导体管芯中。
图1a图示根据一个实施例的包括电流隔离信号传输耦合器21的半导体器件20,所述电流隔离信号传输耦合器21包括接触衬垫22。电流隔离信号传输耦合器21可以实现双向信号交换,并且可以包括如在图1b的实施例中图示的电感式耦合器23或者如在图1c的实施例中图示的电容式耦合器24。
接触衬垫22包括金属基底层25,布置在金属基底层25上的金属扩散屏障层26,以及布置在金属扩散屏障26上的金属线可接合层27。金属扩散屏障层26包括第一部分28,所述第一部分28具有在外围31处包括弯曲表面30的第一外表面29以及与第一表面相对的第二表面32。第一部分28在横向平面中延伸并且具有宽度。金属扩散屏障层26还包括第二部分33,所述第二部分33在第一部分28的宽度的中间处从第二表面32伸出。第一部分28的宽度指的是第一部分28在横向平面中的宽度x。
由于第二部分33在第一部分28的宽度的中间处从第二表面32伸出,因此第二表面32在第一部分28与第二部分29之间的接合部处在所有侧面围绕第二部分33,或者换句话说,第一部分28在所有侧面从第二部分33延伸。第一部分28的侧向面积大于第二部分33的侧向面积。金属扩散屏障层26的形状可以被描述成具有头部的蘑菇型形状,所述头部的侧向面积大于从头部的下表面伸出的柱销(pin)的侧向面积。
接触衬垫22,特别是第一部分28或头部包括具有弯曲外表面的外围,所述弯曲外表面朝向金属扩散屏障层26的第二表面32和第二部分33或柱销延伸。所述外围的弯曲表面避免在金属扩散屏障层28的最外表面处存在尖锐的边缘,这可以帮助增加电流隔离信号传输耦合器21对于例如瞬时电压尖峰之类的故障状况的稳健性,并且可以帮助增加电流隔离信号传输耦合器21和半导体器件20的操作寿命。
第一表面29的中心区段可以是基本上平面的以用于接受接合线连接的头部,所述接合线连接用于把电流隔离信号传输耦合器21耦合到用于信号传输或交换的电路。第一部分28的第一表面29的外围31可以具有曲率半径r,其处于第一部分28的最大高度的0.5到2倍范围内。金属线可接合层27可以共形地覆盖第一部分28的第一表面29,并且还可以具有基本上平面的中心部分以及外围处的弯曲表面。
图1b图示半导体器件20’,其包括形式为电感式耦合器23的电流隔离信号传输耦合器21,所述电感式耦合器23包括耦合到接触衬垫22的平面线圈34。
电感式耦合器23也可以被称作变换器,并且可以是空芯变换器。电感式耦合器23可以被用于在具有加强电流隔离的设备中提供电感式双向数据交换。
平面线圈34可以包括由接触衬垫22形成的外端。接触衬垫22的金属基底层25可以与电感式耦合器21的平面线圈34的绕组基本上共面。在某些实施例中,平面线圈34是螺旋平面线圈,所述螺旋平面线圈在其外端处包括接触衬垫22并且在其位于螺旋中心处的内端处包括第二接触衬垫。
图1c图示半导体器件20’’,其包括形式为电容式耦合器的电流隔离信号传输耦合器21,所述电容式耦合器包括接触衬垫22。接触衬垫22形成提供电容器的一对板35、36中的第一板35。板35、36通过电介质37彼此间隔开。
在某些实施例中,接触衬垫22的金属扩散屏障26的第一部分28具有基本上垂直于第一部分28的横向平面延伸的纵轴,并且第二部分33具有与第一部分28的纵轴对准的纵轴。在这些实施例中,第二部分33可以与第一部分28是同心的,使得第一部分从第二部分33的侧面向外侧向延伸基本上相同的距离。接触衬垫22在平面视图中可以是基本上圆形的。
金属扩散屏障层26可以提供抵抗线可接合层27的材料与金属基底层25的材料之间的扩散的屏障,以及提供用于在电压尖峰的情况下减小接触衬垫22的边缘处的电场的尺寸和形状。
在某些实施例中,金属基底层25可以包括铜,例如高纯度铜。在这些实施例中,金属扩散屏障层26可以包括镍磷,并且金属线可接合层27可以包括钯。钯适合于形成到例如包括金或铝的线接合的可靠低欧姆连接。
在包括电感式耦合器23的实施例中,接触衬垫22的平面线圈34和金属基底层25可以包括铜,特别是高纯度铜。
在某些实施例中,在金属线可接合层27上布置另一个金属钝化层。所述金属钝化层可以被提供来例如在把接合线应用到接触衬垫22之前的储存期间防止金属线可接合层27的腐蚀或氧化。在包括钯的线可接合层的情况下,所述金属钝化层例如可以包括金。
在某些实施例中,线可接合层可以被省略,并且金属扩散屏障26的外表面可以提供可以将接合线可靠地附着到其上的表面。
在某些实施例中,金属扩散屏障层25可以包括Ni、CoW或NiMoP。
在某些实施例中,所述接触衬垫包括Cu锚定层,其尺寸和形状对应于金属扩散屏障层26的实施例中的一个。在铜金属基底层25和铜锚定层的情况下,不需要铜锚定层具有金属扩散屏障功能并且因此更好的是被称作锚定层,因为所述接触衬垫的蘑菇型形式可以被用来提供接触衬垫与周围的钝化和绝缘层的机械锚定。
接触衬垫22,并且特别是金属扩散屏障层26的形状可以通过钝化和/或隔离层的适当选择和结构化以及用于沉积接触衬垫22的沉积技术而形成,如参考图2所描述的那样。
图2图示包括电感式耦合器41的半导体器件40的示意性横截面视图,所述电感式耦合器41包括耦合到接触衬垫43的平面线圈42。接触衬垫43包括与平面线圈42基本上共面的金属基底层44,布置在金属基底层44上的金属扩散屏障层45,以及布置在金属扩散屏障45上的金属线可接合层46。
电感式耦合器41被集成到布置在半导体管芯49的上表面48上的多层金属化结构47中。半导体管芯49可以包括硅(例如单晶硅),并且可以包括集成在半导体管芯49中的一个或多个低电压半导体器件(其未在图2的视图中图示)。
借助于覆盖平面线圈42和金属基底层44的外围区段的、布置在金属化结构47的最外表面51上的绝缘钝化层50,可以改进故障状况下从电感式耦合器41到另一个设备或电路的导电连接的可靠性。钝化层50包括接触衬垫43的金属基底层44上方的开口52。金属扩散屏障层45被布置在开口52中,使得开口52限定金属扩散屏障层45的下方部分54的尺寸和形状。金属扩散屏障层45的上方部分55在邻近开口52的钝化层50之上延伸,并且包括大于下方部分54的侧向面积的侧向面积。电气耦合到接触衬垫43的平面线圈42可以被集成在布置于半导体管芯49的上表面48上的金属化结构47内。
可以使用电流沉积(galvanic deposition)或电化学沉积来制作金属扩散屏障层45,使得下方部分54在金属基底层44的被暴露的表面上向上生长,并且在填充钝化层54中的开口52之后继续向上以及向外生长,使得上方部分55的外围区段56位于钝化层50上,并且使得外表面57在外围区段58中具有弯曲表面。
金属扩散屏障层45的上方部分55提供在横向平面中延伸并且具有宽度w的第一部分,所述第一部分具有第一表面57以及与第一表面57相对的第二表面。第一表面57在外围区段58中的外围处包括弯曲表面。金属扩散屏障层45的下方部分54提供从第一部分的第二表面伸出的第二部分。所述第二部分在第一部分的宽度w的中间的位置处从第二表面伸出。
诸如接触衬垫43的外围区段58之类的弯曲外表面例如在高电压设备中是有用的。在某些实施例中,金属基底层44的侧面66也可以具有弯曲形式。此外,至少平面线圈42和平面线圈60的最外侧绕组的外表面67也可以具有弯曲形式。
包括NiP的金属扩散屏障层可以使用电化学沉积来制作,例如,CoW通过也被称作无电沉积(electroless deposition)的电化学沉积,NiMoP通过电流和电化学沉积,Ni通过电流沉积。
金属扩散屏障45可以填充钝化层50中的开口54,并且在钝化层50的上表面处覆盖开口54的边缘。在制作钝化层50中的开口54期间,在下面的金属基底层44的材料可能被沉积在钝化层50中的开口54的侧壁上。这样的材料可能具有带有边缘的伸长或尖峰形式,其如果没有用另外的导电材料充分地覆盖,则可能提供失效的场所,所述失效归因于在诸如瞬时电压尖峰之类的故障状况下的局部增大的电场的形成。填充钝化层50的开口54以及上表面的相邻区段的金属扩散屏障45的形状覆盖这样的材料,并且可以被用来避免存在这样的场所。
所述钝化层可以包括SixNy,特别是氢化SixNy。钝化层50的厚度可以处于0.5μm到5μm的范围内,并且开口54的尺寸可以处于50μm到120μm的范围内。
如图2中图示的,在某些实施例中,电感式耦合器41还可以包括第二平面线圈60,其被布置在平面线圈42的下面并且通过一个或多个电介质或隔离层61与平面线圈42间隔开。某些实施例,电介质层61可以包括氧化硅。平面线圈42、60二者都可以被集成到半导体管芯49上的金属化结构47中。
在某些实施例中,平面线圈42、60和金属基底层44可以通过大马士革技术来制作。金属化结构47可以包括氮化硅层62和氧化硅层63,使得金属平面线圈60位于氮化硅层62上并且被嵌入在氧化物层63内。氧化硅层61被布置在下方平面线圈60上,氮化硅层64被布置在氧化硅层61上,并且另一个氧化硅层65被布置在氮化硅层64上。平面线圈41和金属基底层44被布置在氮化硅层64上并且被嵌入在氧化硅层65内。平面线圈42、60之间的间距与电介质层61的材料可以被选择成使得电感式耦合器41提供分别满足VDE 0884-11、IEC60664-1或IEC 62368的要求的基本或加强电流隔离。
图3a图示根据一个实施例的蘑菇形接触衬垫70的一部分的横截面视图,所述蘑菇形接触衬垫70可以被用作根据本文中所描述的实施例中的任一个的电感式耦合器的接触衬垫。图3a图示可以被调节从而提供针对高电压应用的加强电流隔离的尺寸。图3b图示接触衬垫70的边缘区段的放大视图。
接触衬垫70包括被布置在平面金属基底层72上的蘑菇形金属扩散屏障层71。金属基底层72可以是布置在半导体管芯76的上表面75上的金属化结构74的一部分。金属基底层72可以具有宽度wb。接触衬垫70在平面视图中可以是基本上圆形的,使得金属基底层72和金属扩散屏障层71也是基本上圆形的平面视图。在这些实施例中,金属基底层72的宽度wb可以对应于基本上圆形的金属基底层72的直径。
电气绝缘钝化层73被布置在金属化结构74的上表面77上并且在金属基底层72的外围78上。在某些实施例中,金属基底层72的外围78的距离l1被钝化层73覆盖。钝化层73限定开口79,所述开口79暴露金属基底层72的上表面80的中心部分,金属扩散屏障层71被布置在所述开口79中。金属扩散屏障71的基底具有宽度w2,该宽度w2对应于钝化层73中的开口79的宽度。钝化层73可以具有厚度t,该厚度t限定金属扩散屏障层71的第二部分81的高度。金属扩散屏障层71可以具有总体高度h。金属扩散屏障层71的第一部分82可以具有宽度w1,该宽度w1大于位于钝化层73中的开口79内的第二部分81的宽度w2。因此,第一部分82从开口79在钝化层73的最外表面83之上延伸达距离l2。金属扩散屏障的第一部分82的宽度w1大于第二部分81的宽度w2,并且小于金属基底层的宽度wb。在基本上圆形的接触衬垫70的情况下,距离l2对应于第一部分82的宽度与第二部分81的宽度中的差的一半,即l2=(w1-w2)/2。
为了实现基本和/或加强电流隔离,可以适当地选择钝化层73的厚度t与被钝化层73覆盖的金属基底层72的外围78的长度l1之间的关系。在某些实施例中,t与l1的比值处于0.5到1的范围内,即0.5≤t/l1≤1。
此外,金属扩散屏障层71的总体高度h与延伸l2的比值可以被选择成使得它处于1.5到2.5的范围内,即1.5≤h/l2≤2.5。接触衬垫70的第一部分82的外围包括曲率半径r。曲率半径r与金属扩散屏障层71的高度h的比值可以处于0.5≤r/h≤2的范围内。曲率半径r可以至少是钝化层73的厚度t的两倍,使得r>t/2。金属扩散屏障层71的高度h、第一部分82的外围的曲率半径r以及钝化层73的厚度t可以被选择成使得h≈t+r。
金属基底层72具有厚度tb。曲率半径r可以大于金属基底层72的厚度tb的三分之一,使得r≥tb/3。被钝化层73覆盖的金属基底层72的外围78的长度l1、第一部分82的外围的曲率半径r以及金属基底层的厚度tb可以被选择成使得r/3<l1<6tb。
作为一个示例,所述曲率半径可以处于3μm到5μm的范围内,宽度wb可以是大约100μm,宽度w2可以大于20μm,典型地80μm到90μm,并且宽度w1大于w2并且小于wb,并且可以是大约85μm到98μm。在某些实施例中,w1=w2+2r。长度l1可以是大约10μm。长度l2可以是大约3μm。高度h可以是大约5μm。金属基底层可以具有大约3μm的厚度。
某些实施例提供包括具有蘑菇型形状的接触衬垫和接合线的连接结构。所述连接结构可以被用来把电感式耦合器或电容式耦合器耦合到电路或电路的半导体器件,以提供电流隔离和信号传输。
如通过图3b的放大视图中的点线84示意性地指示的那样,接触衬垫70的尺寸和尺寸之间的关系可以被调节,从而在接触衬垫70和附着到接触衬垫70的接合线83的表面处或附近获得电压值,其更加均匀并且具有更加平滑的形式以便提供针对高电压应用的加强电流隔离。所述尺寸和尺寸之间的关系可以被调节,使得接触衬垫70和接合线83的表面处或附近的电压值尽可能地恒定。
图4图示连接结构90,所述连接结构90包括接触衬垫91以及被布置在接触衬垫91上并且与之电气耦合的接合线92。连接结构90可以被用于具有加强电流隔离的设备中的电感式双向数据交换。例如,连接结构90可以被使用在电感式耦合器中,包括根据本文中所描述的实施例中的一个的电感式耦合器,或者可以被使用在电容式耦合器中,包括根据本文中所描述的实施例中的一个的电容式耦合器。
接触衬垫91包括金属基底层93,布置在金属基底层93的上表面98上的金属扩散屏障层97,布置在金属扩散屏障层97上的线可接合层99,以及布置在金属线可接合层99上的金属钝化层100。具体来说,在线接合之后,金属钝化层100被布置在接合线92的头部101与金属线可接合层99之间的接触区域之外的区段中的线可接合层99上。
金属基底层93可以位于金属化结构94的绝缘层中,所述金属化结构94位于在图4的视图中不能看到的半导体管芯的表面上。具体来说,金属基底层93的下表面95和侧面96可以被嵌入在金属化结构94的电介质层或钝化层中。在某些实施例中,金属基底层93的侧面96可以具有圆形形式。
连接结构90还可以包括被布置在金属化结构94的上表面103以及金属基底层93的上表面98的外围区段上的第一钝化层102。钝化层102包括位于金属基底层93的上表面98的中心区段上方的开口104。金属扩散屏障层97的下方部分被布置在该开口104中,并且在钝化层102的上表面105之上延伸,使得金属扩散屏障层97的外表面106在外围107处具有弯曲形式并且在开口104上方的区段中是基本上平面的。中心基本上平面的区段108适合于在接合线92的头部101与接触衬垫91之间产生良好的机械和电气连接。
金属扩散屏障层97包括蘑菇型形状,使得上方部分具有比下方部分更大的面积。接触衬垫91在平面视图中可以是基本上圆形的。线可接合层99被布置在金属扩散屏障层97的上表面上并且适合外围107的弯曲表面,使得线可接合层99的外表面也具有弯曲形式,并且在其外围区段中在金属基底层93的方向上弯曲。线可接合层99可以与侧向邻近开口104的钝化层102的上表面105接触。
连接结构90包括第二隔离层109,其被布置在钝化层102的上表面105上并且具有如下侧向范围:使得其在金属扩散屏障层97的外围区段107之上延伸并且特别延伸到线可接合层99的外围区段上。第二隔离层109限定暴露线可接合层99的中心部分的开口110。金属钝化层100被布置在该开口110中,并且因此具有小于金属线可接合层99的侧向范围的侧向范围。
连接结构90的各个元件的材料可以被选择成提供特定的性质。在一个实施例中,金属基底层93包括铜,特别是高纯度铜。线可接合层99包括钯。为了防止线可接合层99的钯99与金属基底层93的铜之间的扩散,金属扩散屏障层97可以包括镍磷,即镍磷合金。金属钝化层100例如可以包括金。接合线92可以包括金或铝或Cu,或者能够与钯99形成低欧姆接触的另一金属或合金。接合线92的头部101与线可接合层99之间的界面区段可以没有金属钝化层100。
第一钝化层102可以包括氢化氮化硅,从而促进钝化层中的电荷捕获,并且第二隔离层109可以包括酰亚胺,例如聚酰亚胺。酰亚胺是有用的,因为其与粘附到铜或镍磷(并且因此,粘附到金属扩散屏障层97和金属基底层93)相比更好地粘附到线可接合层99的钯。
钝化层102和第二隔离层109的厚度和材料可以被选择成提供接合线92与半导体管芯内的另外的器件之间的适当的隔离水平。
在形成接合线连接之后,接触衬垫91和接合线92可以被封装在模制化合物中。覆盖钝化层102与金属扩散屏障层97之间的界面的第二隔离层109的布置以及第二隔离层109与金属线可接合层99之间的更好的粘附可以被用来阻碍或防止水分从上覆的模制化合物渗透到该界面中,并且降低在由于该界面处所累积的水分的蒸发而导致的故障期间失效的可能性。
图5图示连接结构120,其可以被用于具有加强电流隔离、并且特别是针对例如可能由雷击或其他故障电路导致的零星的瞬时过电压和/或其他干扰电压的加强电流隔离的设备中的电感式或电容式双向数据交换。所述连接结构可以被使用在具有额定用于3kV或10kV脉冲的电流隔离的设备中。
互连结构120与图4中图示的互连结构90的不同之处在于增大邻近接触衬垫91和接合线92的区段中的隔离层的总厚度的附加隔离层121、122的布置。
连接结构120包括接触衬垫91和接合线92,其具有与图4中图示的结构类似的结构。接触衬垫91包括金属基底层93、金属扩散屏障层97、金属线可接合层99以及金属钝化层100。所述连接结构还包括被布置在金属化结构94的上表面103上以及金属基底层93的上表面98的外围区段中的钝化层102,以及第二隔离层109。
连接结构120还包括被布置在邻近开口104的钝化层102上并且在第二隔离层109下方的第三隔离层121。第三隔离层121可以具有与开口104并且与接触衬垫91基本上同心的环的形式。第三隔离层121被布置在离金属基底层93的侧面96某一距离处。第四隔离层122被布置在第三隔离层121的上表面123和侧面124上,并且在钝化层102的上表面105之上延伸到钝化层102中的开口104。
第四隔离层122还限定可以具有与开口104基本上相同的侧向面积的开口126。金属扩散屏障层97的上方部分位于紧邻开口126的区段中的另一个隔离层122上。线可接合层99也在金属扩散屏障层97的上方部分的弯曲侧面之上延伸,并且与第四隔离层122接触。如在图4中图示的连接结构90中那样,第二隔离层109被布置在第四隔离层122和线可接合层99的外围区段上。在形成接合线连接之后,金属钝化层100、接合线92和第二隔离层109可以被封装在模制化合物中。
钝化层102可以包括氢化SixNy并且具有2μm的厚度,并且第二隔离层酰亚胺并且具有3μm到12μm的厚度。第三隔离层121可以包括磷硅酸玻璃(PSG)或SiOx,并且可以具有3μm到12μm的厚度,典型地7μm。第四隔离层122可以包括氢化SixNy并且可以具有300nm的厚度。第二隔离层109中的开口110可以具有处于50μm到120μm的范围内的直径。
作为一个示例,对于钉头接合连接,接合线92可以具有25μm到30μm的直径,并且接合线92的头部101大约60μm的直径和大约30μm的高度。
图6a和6b图示根据替换实施例的接触衬垫130。接触衬垫130包括被布置在金属基底层132上的金属锚定层131。金属基底层132和锚定层131可以包括Cu。锚定层131具有对应于金属扩散屏障层的实施例中的一个的尺寸和形状并且具有蘑菇型形式,其上方部分带有大于下方部分的侧向面积。所述上方部分具有带有在下方部分的方向上弯曲的弯曲形式的外围。下方部分的位置和体积由覆盖金属基底层132的外围区段的绝缘层134中的开口限定。
在铜金属基底层132和铜锚定层131的情况下,不要求锚定层131具有金属扩散屏障功能并且因此更好的是被称作锚定层,因为接触衬垫130的蘑菇型形式可以被用来提供接触衬垫130与周围的钝化和/或绝缘层134的机械锚定。接触衬垫130可以被使用在形式为电感式耦合器或电容式耦合器的电流隔离信号传输耦合器135中。
在沉积之后可以通过湿法蚀刻对锚定层131进行处理,以例如在上方部分的外围处产生弯曲形式。
在图6a中图示的实施例中,绝缘层134包括SiOx并且接触衬垫130可以包括粘附促进层136,所述粘附促进层136被布置在金属基底层132的上表面137的被暴露的部分上,绝缘层134中的开口138的侧壁上,以及邻近开口138的绝缘层134的上表面139的区段上。锚定层131的上方部分140被布置在粘附促进层136上并且从粘附促进层136向外延伸。锚定层131的下方部分141填充开口138。绝缘钝化层142,例如具有不多于几个原子(atom)的厚度的Al2O3或SixNy层,可以被布置在接触衬垫130的最外表面上。绝缘钝化层142可以覆盖绝缘层134的上表面139、粘附促进层136的侧面以及锚定层131的自由伸展的外表面143。
在图6b中图示的实施例中,绝缘层134包括SixNy,并且锚定层131与金属基底层132的上表面137、开口138的侧壁和绝缘层134的上表面139直接接触。接触衬垫130还包括布置在锚定层的外表面上的一层或多层。在某些实施例中,NiP层143被布置在锚定层131的外表面146上,Pd层144被布置在NiP层143上,并且Au层145被布置在NiP层144上。
锚定层131的上方部分140提供具有外表面146或第一表面以及与第一表面相对的第二表面的第一部分。该第一部分的第一表面在外围处具有弯曲表面。第一部分在横向平面中延伸并且具有宽度。锚定层131的下方部分141提供在第一部分的宽度的中间处从第一部分的第二表面伸出的第二部分。
图7图示用于制作接触衬垫的方法的流程图150,所述接触衬垫可以被用于提供双向信号交换以及基本和/或加强电流隔离的电感式耦合器。
在框151中,将金属扩散屏障层沉积到在第一隔离层的开口中被暴露的金属基底层的表面上,所述第一隔离层覆盖金属基底层的外围区段,使得金属扩散屏障层延伸到第一隔离层的外表面上。在框152中,对金属扩散屏障层进行退火。在框153中,将金属线可接合层沉积到经过退火的金属扩散屏障层上。
在沉积后续的一个或多个金属层之前对金属扩散屏障层进行退火。这种方法可以被使用,使得后续沉积的层可以为可能在金属扩散屏障与第一隔离层中的开口之间形成的任何间隙提供密封,其中所述间隙可能由于金属扩散屏障层在退火期间的松弛和收缩而产生。
金属扩散屏障的外表面可以在其外围处具有弯曲形式,并且朝向第一隔离层延伸。由外围定界的金属扩散屏障层的中心位置可以是基本上平面的。
取决于成分,可以使用电化学沉积或电流沉积来沉积金属扩散屏障层。可以使用电化学沉积来沉积NiP金属扩散屏障层。在电流沉积中使用外部电源,而在电化学沉积中不使用外部电源。电化学沉积也被称作无电沉积。由于金属扩散屏障在邻近开口的区段中的第一隔离层上的生长机制,这些方法可以被用来产生在外围处具有弯曲形式的外表面。
取决于成分,可以电流地或者通过无电沉积来沉积金属线可接合层。例如,可以通过无电沉积来沉积Pd,并且通过电流沉积来沉积Ni。线可接合层可以适合在下面的金属扩散屏障层的形状,并且在其外围处也具有弯曲形式。
在某些实施例中,将第二隔离层沉积到金属线可接合层的外围区段上。第二隔离层可以包括材料,其对于线可接合层具有良好的粘附性质,和/或与金属扩散屏障层相比对于线可接合层具有更好的粘附性质。这种布置可以被用来防止第二隔离层从导电接触衬垫分层。
在某些实施例中,将金属钝化层沉积到金属线可接合层上,使得第二隔离层限定金属钝化层的侧向范围。金属钝化层的侧向范围小于在下面的金属线可接合层和金属扩散屏障层的头部的侧向范围,因为第二隔离层被布置在线可接合层的外围区段上。金属钝化层可以被用来阻碍线可接合层在生产和储存期间,特别是在线接合被附着到接触衬垫之前的生产和储存期间氧化或污染。金属钝化可以不形成线接合与接触衬垫之间的接合的一部分。
可以通过例如使用钉头线接合技术把接合线施加到接触衬垫的基本上平面的中心部分来形成连接结构。
图8a图示电感式耦合器160的一个示例的透视图,所述电感式耦合器160可以通过根据本文中所描述的实施例中的一个的连接结构而耦合到电路以提供电流隔离。电感式耦合器160也可以被使用在根据本文中所描述的实施例中的一个的设备中。
电感式耦合器160包括初级侧161和次级侧162,据此初级侧141和次级侧162中的每一个包括至少一个平面线圈。在图8a中图示的实施例中,初级侧161和次级侧162中的每一个包括两个基本上共面的螺旋平面线圈163、164;168、169。次级侧161包括布置在螺旋平面线圈163的中心的接触衬垫165,布置在两个螺旋平面线圈163和164的外端之间并且耦合到所述外端的接触衬垫166,以及布置在螺旋平面芯164的中心的接触衬垫167。
根据本文中所描述的实施例中的任一个之一的接触衬垫的形状和结构可以用于中心衬垫166,据此金属基底层与平面线圈163、164共面并且耦合到平面线圈163、164。在某些实施例中,接触衬垫165、167中的一个或二者也包括根据本文中所描述的实施例中的任一个的结构。接触衬垫165、167的形状、尺寸和结构可以与接触衬垫166的那个相同或不同。
初级侧164还包括两个共面螺旋平面线圈168、169,其位于次级侧162的相应螺旋平面线圈163、164下方并且通过电介质层170与之间隔开。平面线圈168、169、163、164是导电的并且可以被集成在硅芯片上,并且特别地被集成在多层金属化结构的不同层中。螺旋平面线圈163、164、168、169可以包括高纯度铜并且可以例如使用大马士革技术来制作。
但是在其他实施例中,所述电感式耦合器可以包括初级侧161中的单一线圈和次级侧162中的单一线圈。一个或多个平面线圈不需要是螺旋的并且不需要是基本上圆形的。
图8b和8c图示可以被用于电感式耦合器的初级或次级侧的平面螺旋线圈的另外的实施例。
图8b图示电感式耦合器160’的一个实施例,其包括两个平面螺旋线圈171、172,据此接触衬垫173、174被布置在两个平面螺旋线圈171、172中的每一个的中心处,并且所述两个平面螺旋线圈171、172通过基本上S形的连接耦合。所述两个平面螺旋线圈171、172可以被连续导电隔离线圈175围绕。
图8c图示电感式耦合器160’’的一个实施例,其包括单一平面螺旋线圈176,据此第一接触衬垫177被布置在平面螺旋线圈176的中心处,并且第二接触衬垫178被布置在平面螺旋线圈177的外端处。平面螺旋线圈176和接触衬垫177、178可以被连续导电隔离线圈179围绕。
包括根据本文中所描述的实施例中的任一个的连接结构和电感式耦合器或电容式耦合器的设备可以被用来提供电流隔离,诸如各种应用和电路中的基本电流隔离或加强电流隔离。
图9a图示包括第一电路181、第二电路182以及由电感式耦合器183提供的电流隔离的系统180的示意性视图。电感式耦合器183包括电气耦合到第一电路181的第一线圈184和电气耦合到第二电路182的第二线圈165,以及布置在第一线圈184与第二线圈185之间的电流隔离186。
系统180的第一电路181和第二电路182可以包括单一设备或者形成电路的两个或更多设备。电感式耦合器183可以包括初级侧和次级侧的一个或两个线圈。系统180可以被用于功率转换,使得电路181、182例如可以包括功率转换系统和驱动器电路。
图9b图示包括第一电路191、第二电路192以及由两个电容式耦合器193、194提供的电流隔离的系统190的示意性视图。第一电路191可以是高电压电路,并且第二电路192可以是低电压电路。替选地,第一电路191和第二电路192二者可以都是高电压电路,或者第一电路191可以是低电压电路并且第二电路192可以是高电压电路。
每一个电容式耦合器193、194包括通过电介质材料197;197’彼此电流分离的两个导电板195、196;195’、196’。电介质材料197;197’的介电强度足够高,使得提供要求的电流隔离的水平,例如基本还是加强的。例如,电介质层197可以经受5kVRMS的板到板电压差而不遭受电介质击穿。
电容式耦合器利用电容中的改变来传送信号。在操作中,通过对数据进行编码然后把已编码数据信号以脉冲、RF波形或短时脉冲(glitch)的形式放置到板195上,第一电路191来向第二电路192传送数据。所述信号被电容耦合到低电压板196,并且随后由第二电路192检测到和解码。
在图9a和9b的系统中,初级和次级侧彼此电流隔离,并且仅通过电感式或电容式耦合器连接。所述系统可以具有在初级侧与次级侧之间提供双向数据的能力。此外,可以从初级侧向次级侧提供功率。初级侧可以通过一个或多个驱动器(未图示)来驱动次级侧,并且次级侧可以向初级侧提供用于感测的数据。
图10图示功率半导体模块200的示例的示意图,其可以包括根据本文中所描述的实施例中的一个或多个的电感式耦合器和/或连接结构。功率半导体模块200可以包括替代电感式耦合器的电容式耦合器。模块200具有三个块201、202、203。块201包括可以被集成到半导体驱动器组件204中的一个或多个驱动器电路。块202包括一个电源部分,所述电源部分可以包括两个或更多半导体开关205、206(诸如功率晶体管),其例如可以被耦合来提供半桥电路。
块203确保驱动器电路201与电源部分202之间的电流隔离。电流隔离可以被集成在驱动器组件204中或者由单独的组件形成。电流隔离可以由具有根据本文中所描述的实施例中的一个的接触衬垫的电感式耦合器207提供。所述电感式耦合器可以通过根据本文中所描述的实施例中的一个的连接结构耦合到驱动器组件204。驱动电路201可以耦合到处于模块200外部的另一个控制元件208。
图11图示电子组件210的一个示例,所述电子组件210包括第一半导体管芯211、第二半导体管芯212以及提供加强电流隔离的根据本文中所描述的实施例中的一个的至少一个电感式耦合器213。图12图示图11的电感式耦合器213的一部分,并且特别地是到接触衬垫215、216的接合线连接214的更加详细的视图。
电感式耦合器213耦合在第一半导体管芯211与第二半导体管芯212之间的双向信号交换路径中。在图11图示的实施例中,电感式耦合器213具有图8a中图示的结构。
第一半导体管芯211被布置在第一管芯衬垫217上,并且第二半导体管芯212被布置在第二管芯衬垫218上。第二管芯衬垫218与第一管芯衬垫217间隔开,并且通过提供半导体组件210的外壳220的模制化合物219与之隔离。
电感式耦合器213被集成到金属化结构221中,所述金属化结构221被布置在第二半导体管芯212的上表面上。电感式耦合器213被电气耦合以便通过接合线214提供第一半导体管芯211与第二半导体管芯212之间的信号路径。
耦合到电感式耦合器213的两个螺旋平面线圈223、224的外端的接触衬垫215可以具有根据本文中所描述的实施例中的一个的结构,并且特别可以具有圆形或弯曲的外围。
第一半导体管芯211可以包括逻辑、运算放大器或Schmitt触发器电路,并且第二半导体管芯212可以包括门驱动器或者ADC(模拟数字转换器)电路与Schmitt触发器。
为了易于描述以便解释一个元件相对于第二元件的定位,使用了诸如“在…下方”、“在…之下”、“下方”、“在…之上”、“上方”等空间相对术语。除了不同于附图中所描绘的取向之外,这些术语意图涵盖设备的不同取向。此外,诸如“第一”、“第二”等术语也被用来描述各个元件、区段、部分等等并且也不意图是限制性的。贯穿本描述,相同的术语指代相同的元件。
如本文中所使用的,术语“具有”、“含有”、“包含”、“包括”等等是开放性术语,其指示所陈述的元件或特征的存在,而不排除附加的元件或特征。除非上下文清楚地另外指示,否则冠词“一”、“一个”和“该”意图包括复数以及单数。应当理解的是,除非明确地另行声明,否则本文中所描述的各个实施例的特征可以与彼此组合。
虽然在本文中说明并描述了具体实施例,但是本领域普通技术人员中的那些将领会到,在不脱离本发明的范围的情况下,各种替换的和/或等同的实现方式可以替代所示出和描述的具体实施例。本申请意图覆盖本文中所讨论的具体实施例的任何改编或变型。因此,意图是本发明仅由权利要求及其等同物限制。
Claims (20)
1.一种半导体器件,包括:
包括接触衬垫的电流隔离信号传输耦合器,
其中所述接触衬垫包括:
金属基底层;
布置在金属基底层上的金属扩散屏障层;以及
布置在金属扩散屏障层上的金属线可接合层,
其中,金属扩散屏障层包括第一部分、第二部分,所述第一部分具有第一表面以及与第一表面相对的第二表面,第一部分的第一表面在外围处包括弯曲表面,第一部分在横向平面中延伸并且具有宽度,所述第二部分在第一部分的宽度的中间处从第二表面伸出。
2.根据权利要求1所述的半导体器件,还包括被布置在金属基底层的外围区段上并且具有暴露金属基底层的一部分的第一开口的第一隔离层,其中金属扩散屏障层的第二部分被布置在第一隔离层中的第一开口中,并且金属扩散屏障层的第一部分延伸到第一隔离层的邻近第一开口的表面上。
3.根据权利要求1所述的半导体器件,还包括金属线可接合层上的金属钝化层。
4.根据权利要求3所述的半导体器件,其中,金属基底层包括铜,和/或金属扩散屏障层包括NiP,和/或金属线可接合层包括Pd和/或金属钝化层包括Au。
5.根据权利要求3所述的半导体器件,还包括第二隔离层,所述第二隔离层被布置在金属线可接合层的外围区段上并且包括暴露金属线可接合层的一部分的第二开口。
6.根据权利要求5所述的半导体器件,其中,金属钝化层被布置在第二开口中并且由第二开口定界。
7.根据权利要求5所述的半导体器件,还包括第三隔离层和第四隔离层,所述第三隔离层包括被布置在第一隔离层上的环,所述第四隔离层被布置在第三隔离层的外部面上。
8.根据权利要求7所述的半导体器件,其中,第一隔离层包括氢化SixNy,第二隔离层包括酰亚胺,第三隔离层包括SiOx或磷硅酸玻璃并且第四隔离层包括氢化SixNy。
9.根据权利要求1所述的半导体器件,其中,所述电流隔离信号传输耦合器包括电感式耦合器,所述电感式耦合器包括耦合到接触衬垫的平面线圈。
10.根据权利要求9所述的半导体器件,其中,所述电感式耦合器包括与第一平面线圈一起布置在堆叠中并且通过包括SiOx的隔离层与第一平面线圈电流隔离的第二平面线圈,并且被配置成提供针对至少10kVpeak的浪涌脉冲隔离电压VIOSM的加强电流隔离。
11.根据权利要求10所述的半导体器件,还包括被布置成与第一平面线圈基本上共面并且耦合到接触衬垫的第三平面线圈。
12.根据权利要求9所述的半导体器件,其中,所述平面线圈和金属基底层被集成在半导体管芯中。
13.根据权利要求1所述的半导体器件,其中,所述电流隔离信号传输耦合器包括电容式耦合器,并且所述接触衬垫提供所述电容式耦合器的板。
14.一种电子组件,包括:
半导体器件,其包括
包括接触衬垫的电流隔离信号传输耦合器,
其中接触衬垫包括:
金属基底层;
布置在金属基底层上的金属扩散屏障层,以及
布置在金属扩散屏障层上的金属线可接合层,
其中金属扩散屏障层包括第一部分、第二部分,所述第一部分具有第一表面和与第一表面相对的第二表面,第一部分的第一表面在外围处包括弯曲表面,第一部分在横向平面中延伸并且具有宽度,所述第二部分在第一部分的宽度的中间处从第二表面伸出;以及
耦合到所述半导体器件的双向信号传输路径;
其中,电流隔离信号传输耦合器被耦合在所述双向信号传输路径中并且通过接合线耦合到所述半导体器件,并且提供针对至少10kVpeak的浪涌脉冲隔离电压VIOSM的加强电流隔离。
15.根据权利要求14所述的电子组件,还包括通过所述双向信号传输路径耦合到所述半导体器件的另一个半导体器件。
16.一种用于形成接触衬垫的方法,所述方法包括:
将金属扩散屏障层沉积到在第一隔离层的第一开口中被暴露的金属基底层的表面上,所述第一隔离层覆盖金属基底层的外围区段,使得金属扩散屏障层延伸到第一隔离层的外表面上;
对金属扩散屏障层进行退火;
将金属线可接合层沉积到经过退火的金属扩散屏障层上。
17.根据权利要求16所述的方法,还包括把第二隔离层沉积到金属线可接合层的外围区段上,从而限定暴露线可接合层的一部分的第二开口并且,可选地,还包括把金属钝化层沉积到金属线可接合层上使得第二隔离层对金属钝化层进行定界。
18.一种半导体器件,包括:
包括接触衬垫的电流隔离信号传输耦合器,其中所述接触衬垫包括:
金属基底层;
布置在金属基底层上的金属锚定层,并且
其中,金属锚定层包括第一部分、第二部分,所述第一部分具有第一表面以及与第一表面相对的第二表面,第一部分的第一表面在外围处包括弯曲表面,第一部分在横向平面中延伸并且具有宽度,所述第二部分在第一部分的宽度的中间处从第二表面伸出,其中金属锚定层和/或金属基底层包括铜。
19.根据权利要求18所述的半导体器件,还包括被布置在金属基底层的外围区段上并且具有暴露金属基底层的一部分的第一开口的第一隔离层,其中金属锚定层的第二部分被布置在第一隔离层中的第一开口中,并且金属锚定层的第一部分延伸到第一隔离层的邻近第一开口的表面上,以及被布置在金属锚定层的第一表面上的绝缘钝化层。
20.根据权利要求18所述的半导体器件,其中,金属锚定层与金属基底层、第一开口的侧壁以及绝缘层的邻近第一开口的表面直接接触。
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Also Published As
Publication number | Publication date |
---|---|
CN114464592A (zh) | 2022-05-10 |
GB2557614A (en) | 2018-06-27 |
US11380612B2 (en) | 2022-07-05 |
KR20180067449A (ko) | 2018-06-20 |
KR102120820B1 (ko) | 2020-06-10 |
GB201621079D0 (en) | 2017-01-25 |
EP3336889B1 (en) | 2022-09-28 |
US20180166375A1 (en) | 2018-06-14 |
EP3336889A1 (en) | 2018-06-20 |
CN108231728B (zh) | 2022-03-04 |
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