CN106057775A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN106057775A
CN106057775A CN201610216608.7A CN201610216608A CN106057775A CN 106057775 A CN106057775 A CN 106057775A CN 201610216608 A CN201610216608 A CN 201610216608A CN 106057775 A CN106057775 A CN 106057775A
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film
metal
semiconductor device
distribution
barrier
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CN106057775B (zh
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大森和幸
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

一种半导体器件及其制造方法，所述半导体器件可以防止再配线之间的电短路。在铜再配线的各个侧表面上形成阻挡膜。阻挡膜包括例如锰氧化物膜。所述阻挡膜也与阻挡金属膜的各个端表面接触，所述阻挡金属膜的各个端表面位于从铜再配线的侧表面向内后退的位置。通过铜再配线、阻挡膜和阻挡金属膜形成再配线部。

Description

半导体器件及其制造方法
相关申请的交叉引用
在此通过引用将于2015年4月10提交的日本专利申请No.2015-080779的公开内容，包括说明书、附图和摘要以整体的方式并入本文中。
技术领域
本发明涉及半导体器件及其制造方法，更具体地涉及适合用于包括铜再配线的半导体器件的技术。
背景技术
为了实现电子装置的小型化等，在半导体器件领域一直在不断开发晶圆级芯片规模封装技术。晶圆级芯片规模封装是涉及如下的技术：为了在半导体衬底(晶圆)上形成元件、布线(wiring)等进行一系列的处理，随后形成钝化膜，然后在钝化膜上形成更多的布线、电极(焊盘)等。
在钝化膜上形成的布线被称为再配线。再配线的大小近似比在钝化膜下形成的正常的布线的大小大一个数量级。适合用于再配线的材料为铜，其具有相对低的电阻(比电阻)和高的热导率。
用于键合铜线的键合焊盘在再配线的表面处形成。作为键合焊盘，形成金(Au)膜等。具有在再配线中包括金膜的键合焊盘的这种结构被称为“具有金焊盘(RAP)结构的再配线层”。
在形成键合焊盘之后，形成覆盖再配线、键合焊盘等的聚酰亚胺膜。聚酰亚胺膜设置有用于暴露各个键合焊盘的开口。之后，将晶圆切成芯片。将铜线键合至芯片的半导体器件的键合焊盘，然后将半导体器件(芯片)密封(封装)。应注意，专利文献1为公开一般的铜布线的文献的示例。
现有技术文献
专利文献
专利文献1：日本未审专利申请公开No.2012-204495
发明内容
对半导体器件进行作为可靠性评估中的一项的被称为“高加速的温度和湿度应力试验(HAST)”的环境试验。在环境试验中，在将半导体器件暴露于高温和高湿度下的环境的同时，向由铜制成的再配线施加相对高的电压例如约几十V至约100V。发明人已经确认，此时，铜在再配线之间沉淀，导致它们之间的电短路现象。
由本说明书的说明和附图将会清楚本发明的其它问题和新颖特征。
根据一个实施方式的半导体器件包括半导体衬底、多层布线、钝化膜、再配线部(redistribution portion)、焊盘部和树脂膜。形成覆盖设置在多层布线中的最高位置的最上层布线且具有与最上层布线连通的开口的钝化膜。再配线部包括再配线，所述再配线形成为与位于开口中的最上层布线的部分接触且具有侧表面和上表面。形成与再配线的上表面接触的焊盘部。再配线部包括阻挡膜，所述阻挡膜形成为与再配线的侧表面接触且包含金属氧化物膜。焊盘部包括由与用于阻挡膜的材料不同的材料制成的焊盘金属膜。
根据另一个实施方式的半导体器件的制造方法包括以下步骤：形成多层布线；形成钝化膜；形成再配线部；以及形成焊盘部。在形成再配线部的步骤中，形成与从开口暴露的最上层布线接触的再配线部，所述再配线部包括具有侧表面和上表面的再配线。包含至少第一金属的金属膜在除钝化膜的表面和再配线的上表面之外的再配线的侧表面处形成。形成包含第一金属氧化物膜的阻挡膜，所述第一金属氧化物膜通过经由对金属膜施加热处理而导致的第一金属的氧化而形成。在形成焊盘膜时，由与用于阻挡膜的材料不同的材料形成焊盘金属膜。
因此，在所述一个实施方式中的半导体器件通过所述阻挡膜可以防止再配线之间的电短路。
此外，在另一个实施方式中的半导体器件的制造方法在再配线的侧表面处形成阻挡膜，从而产生可以防止再配线之间的电短路的半导体器件。
附图说明
图1为根据第一实施方式的半导体器件的横截面图。
图2为显示第一实施方式中的图1中所示的半导体器件的制造方法中的一个步骤的局部横截面图。
图3为显示在第一实施方式中的图2中所示的步骤之后进行的另一个步骤的局部横截面图。
图4为显示在第一实施方式中的图3中所示的步骤之后进行的另一个步骤的局部横截面图。
图5为显示在第一实施方式中的图4中所示的步骤之后进行的另一个步骤的局部横截面图。
图6为显示在第一实施方式中的图5中所示的步骤之后进行的另一个步骤的局部横截面图。
图7为显示在第一实施方式中的图6中所示的步骤之后进行的另一个步骤的局部横截面图。
图8为显示在第一实施方式中的图7中所示的步骤之后进行的另一个步骤的局部横截面图。
图9为显示在第一实施方式中的图8中所示的步骤之后进行的另一个步骤的局部横截面图。
图10为显示在第一实施方式中的图9中所示的步骤之后进行的另一个步骤的局部横截面图。
图11为显示在第一实施方式中的图10中所示的步骤之后进行的另一个步骤的局部横截面图。
图12为显示在第一实施方式中的图11中所示的步骤之后进行的另一个步骤的局部横截面图。
图13为显示在第一实施方式中的图12中所示的步骤之后进行的另一个步骤的局部横截面图。
图14为显示在第一实施方式中的图13中所示的步骤之后进行的另一个步骤的局部横截面图。
图15为显示在第一实施方式中的图14中所示的步骤之后进行的另一个步骤的局部横截面图。
图16为显示比较例中的半导体器件的制造方法中的一个步骤的局部横截面图。
图17为显示在图16中所示的步骤之后进行的另一个步骤的局部横截面图。
图18为用于说明比较例中的半导体器件的缺点的局部横截面图。
图19为用于说明第一实施方式中的半导体器件的功能效果的局部横截面图。
图20为用于说明第一实施方式中的半导体器件的其它功能效果的局部横截面图。
图21为用于说明第一实施方式中的半导体器件的其它功能效果的第一局部放大的横截面图。
图22为用于说明第一实施方式中的半导体器件的其它功能效果的第二局部放大的横截面图。
图23为用于说明第一实施方式的修改例中的半导体器件的制造方法的图。
图24为显示第一实施方式的修改例中的半导体器件的制造方法中的一个步骤的局部横截面图。
图25为显示在第一实施方式中的图24中所示的步骤之后进行的另一个步骤的局部横截面图。
图26为显示在第一实施方式中的图25中所示的步骤之后进行的另一个步骤的局部横截面图。
图27为用于说明第一实施方式的修改例中的半导体器件的功能效果的局部横截面图。
图28为根据第二实施方式的半导体器件的横截面图。
图29为显示第二实施方式中的图28中所示的半导体器件的制造方法中的一个步骤的局部横截面图。
图30为显示在第二实施方式中的图29中所示的步骤之后进行的另一个步骤的局部横截面图。
图31为显示在第二实施方式中的图30中所示的步骤之后进行的另一个步骤的局部横截面图。
图32为显示在第二实施方式中的图31中所示的步骤之后进行的另一个步骤的局部横截面图。
图33为显示在第二实施方式中的图32中所示的步骤之后进行的另一个步骤的局部横截面图。
图34为显示在第二实施方式中的图33中所示的步骤之后进行的另一个步骤的局部横截面图。
图35为显示在第二实施方式中的图34中所示的步骤之后进行的另一个步骤的局部横截面图。
图36为显示在第二实施方式中的图35中所示的步骤之后进行的另一个步骤的局部横截面图。
具体实施方式
第一实施方式
下文中，将对包括分别通过电镀法形成的铜再配线和键合焊盘的半导体器件的示例进行说明。
如图1中所示，通过在半导体衬底SUB的主表面处的预定区域中形成的元件隔离绝缘膜SI限定元件形成区域EFR。在元件形成区域EFR中形成作为一种半导体元件的晶体管TR。形成覆盖晶体管TR的层间绝缘膜IL1。形成穿过层间绝缘膜IL1的接触插塞CPG。
在层间绝缘膜IL1的表面上由例如铝膜形成第一布线ML1。经由相应的接触插塞CPG将第一布线ML1电连接到晶体管TR。形成覆盖第一布线ML1的层间绝缘膜IL2。形成穿过层间绝缘膜IL2的通孔(vias)VA1。在层间绝缘膜IL2的表面上由例如铝膜形成第二布线ML2。通过所述通孔VA1将各个第二布线ML2电连接至相应的第一布线ML1。
形成覆盖第二布线ML2的层间绝缘膜IL3。形成穿过层间绝缘膜IL3的通孔VA2。在层间绝缘膜IL3的表面上由例如铝膜形成第三布线ML3。第三布线ML3作为焊盘且通过通孔VA2电连接至第二布线ML2。在半导体器件中，第三布线ML3位于多层布线的最上层。
由氮化硅膜形成覆盖第三布线ML3的钝化膜PVF。钝化膜PVF设置有与第三布线ML3连通的开口PVH。形成与钝化膜PVF和位于开口PVH的底部的第三布线ML3的部分接触的阻挡金属膜MBR。
形成与阻挡金属膜MBR接触的铜再配线CPH。再配线CPH的大小近似比在钝化膜PVF下形成的各个正常的第一至第三布线ML1至ML3的大小大一个数量级。例如，再配线CPH具有近似若干μm的厚度和近似10μm的宽度。
通过稍后将会说明的电镀法形成铜再配线CPH。由例如铬(Cr)膜、钛(Ti)膜等形成阻挡金属膜MBR。阻挡金属膜MBR的各个端表面位于通过侧蚀刻从铜再配线CPH的侧表面向内(朝向开口PVH)后退的位置。
在铜再配线CPH的各个侧表面上形成阻挡膜BRF。阻挡膜BRF包含例如锰氧化物膜BMO。阻挡膜BRF也与阻挡金属膜MBR的端表面接触，所述阻挡金属膜MBR的端表面位于从铜再配线CPH的侧表面向内后退的位置。由铜再配线CPH、阻挡膜BRF和阻挡金属膜MBR形成再配线部CRL。
形成与铜再配线CPH的上表面接触的焊盘部MPD。由镍膜MNI和金膜MAU形成焊盘部MPD。在镍膜MNI上形成金膜MAU(焊盘金属膜)。形成覆盖再配线部CRL的聚酰亚胺膜PID。在聚酰亚胺膜PID中形成用于暴露焊盘部MPD的开口PHP。将铜线CPW键合至位于开口PHP的底部处的焊盘部MPD(金膜MAU)。本实施方式中的半导体器件的主要部分被如上所述的构成。
接下来，将通过示例的方式说明用于制造上述半导体器件的方法。首先，通过普通制造方法在半导体衬底SUB的区域中形成元件隔离绝缘膜SI，从而形成元件形成区域，然后在元件形成区域中形成晶体管TR(见图1)。形成覆盖晶体管TR等的包括第一至第三布线ML1至ML3的多层布线结构(见图1)。
然后，如图2中所示，例如通过化学气相沉积(CVD)法由氮化硅膜形成覆盖位于最上层的第三布线ML3的钝化膜PVF。随后，如在图3中所示，通过光刻蚀处理和蚀刻处理形成暴露第三布线ML3的开口PVH。然后，如图4中所示，通过溅射等形成与钝化膜PVF和位于开口PVH的底部的第三布线ML3的部分接触的诸如铬(Cr)膜或钛(Ti)膜的阻挡金属膜MBR。
之后，如图5中所示，通过溅射等形成与阻挡金属膜MBR接触的铜籽晶膜(copper seed film)CPS。然后，如图6中所示，形成暴露其中要通过光刻蚀处理形成再配线的区域且覆盖剩下的其它区域的光刻胶图案PR1。随后，如在图7中所示，通过使用铜籽晶膜CPS作为电极的电镀方法在暴露的铜籽晶膜CPS的表面上形成铜镀膜CF。铜镀膜CF变成铜再配线CPH。之后，将光刻胶图案PR1去除。
然后，如图8中所示，形成暴露其中要通过光刻蚀处理形成焊盘部的铜再配线CPH的一部分且覆盖剩下的其它区域的光刻胶图案PR2。然后，如图9中所示，通过电镀方法在铜再配线CPH暴露的表面(上表面)上形成镍镀膜NF。此外，通过电镀方法在镍镀膜NF的表面上形成金镀膜AF。在此，镍镀膜NF变成焊盘部的镍(Ni)膜MNI，且金镀膜AF变成焊盘部的金(Au)膜MAU。之后，如图10中所示，通过去除光刻胶图案PR2使在铜籽晶膜CPS的表面上形成的铜再配线CPH等暴露。
然后，通过利用化学品的湿法蚀刻将铜籽晶膜CPS暴露的部分去除从而暴露阻挡金属膜MBR。随后，如在图11中所示，通过利用化学品的湿法蚀刻将阻挡金属膜MBR暴露的部分去除从而暴露钝化膜PVF的表面。此时，在某些情况下，在阻挡金属膜MBR中，位于铜再配线CPH的正下方的阻挡金属膜MBR的部分被蚀刻(侧蚀刻)从而导致阻挡金属膜MBR的端表面从再配线CPH的各个侧表面向内(朝向开口PVH)后退。
然后，在铜再配线CPH的各个侧表面处形成阻挡膜。在此，在锰(Mn)和铜(Cu)粒子正在通过溅射在钝化膜PVF上沉积的同时，沉积的锰和铜粒子被朝向半导体衬底SUB飞来的锰和铜粒子蚀刻(再溅射掉或溅射)。
首先，将预定的偏压施加至半导体衬底SUB。如图12中所示，使通过溅射法从目标材料溅射的铜和锰粒子(见参考符号CM)朝向施加有偏压的半导体衬底SUB(钝化膜PVF)飞来。飞来的铜和锰粒子主要沉积在钝化膜PVF的表面处和铜再配线CPH的上表面处。
简而言之，沉积在钝化膜PVF等的表面上的铜和锰粒子被朝向半导体衬底SUB飞来的其它铜和锰粒子再溅射和蚀刻。被再溅射的铜和锰粒子飞向侧表面而被沉积在再配线CPH的侧表面上。
此时，调节施加至半导体衬底SUB的偏压使得沉积在钝化膜PVF上的铜和锰粒子的量基本上与通过再溅射所蚀刻的沉积的铜和锰粒子的量相同。以这种方式，如图13中所示，将铜和锰粒子沉积在铜再配线CPH的侧表面上而不沉积在钝化膜PVF的表面上和铜再配线CPH的上表面上，从而形成包括铜和锰的合金膜CMF。
然后，形成覆盖铜再配线CPH等的聚酰亚胺膜PID(见图14)。随后，实施热处理以烧掉聚酰亚胺膜。例如在近似300℃的温度下进行热处理。此时，在与聚酰亚胺膜PID接触的合金膜CMF中，如图14中所示，包含在合金膜CMF中的锰(Mn)被聚酰亚胺膜中的水分(H2O)氧化，使得自身形成作为阻挡膜BRF的锰(Mn)氧化物膜BMO。形成与阻挡金属膜MBR的端表面接触的阻挡膜BRF，所述阻挡金属膜MBR的端表面位于从铜再配线CPH的各个侧表面后退的位置。
然后，如图15中所示，通过光刻蚀处理和蚀刻处理在聚酰亚胺膜PID中形成暴露焊盘部MPD(金膜MAU)的开口PHP。然后，在对半导体衬底(晶圆)的背面进行研磨等之后，对晶圆进行切割。在切成芯片的半导体器件中，将铜线CPW(见图1)键合至焊盘部MPD，然后将半导体器件(芯片)密封(封装)。以这种方式，如图1中所示，完成半导体器件的主要部分的制造。
在第一实施方式中的半导体器件的铜再配线部CRL中，在再配线CPH的各个侧表面处形成包含锰氧化物膜BMO的阻挡膜BRF。因此，可以防止再配线之间的电短路。下面将通过与比较例中的半导体器件的比较对此进行详细说明。
关于比较例中的半导体器件，为了简化说明，通过相同的参考数字表示与第一实施方式中的半导体器件的构件相同的构件，且除非有需要，将不再重复其说明。
通过与如图2至10中所示的步骤相同的步骤，如图16中所示，在再配线CPH的上表面处形成焊盘部MPD。接下来，如在图17中所示，形成覆盖再配线CPH和焊盘部MPD的聚酰亚胺膜PID。然后，例如在近似300℃的温度下进行热处理以烧掉聚酰亚胺膜。之后，通过与如图15等中所示的步骤相同的步骤完成比较例中的半导体器件的主要部分的制造。
在比较例的半导体器件中，聚酰亚胺膜PID与包括再配线CPH的侧表面的铜再配线CPH的表面接触。聚酰亚胺膜PID包含水分。因此，与聚酰亚胺膜PID接触的再配线CPH倾向于促进铜的离子化。
在对这种半导体器件进行作为对于可靠性的加速应力试验的环境试验(高加速应力试验：HAST)时，在使半导体器件暴露于高温和高湿度下的环境的同时，向铜再配线CPH施加相对高的电压例如约几十V至约100V。此时，如在图18中所示，例如当将高电压施加至相邻的再配线CPH1和CPH2中的一个再配线CPH1，且使另一个再配线CPH2接地时，离子化的铜(铜离子)倾向于容易从一个再配线CPH1向另一个再配线CPH2移动(如左侧的箭头所示)。
发明人进行的评估已经显示，在这种情况下，特别地，铜离子倾向于沿钝化膜PVF与聚酰亚胺膜PID之间的界面从一个再配线CPH1的侧表面移动，所述再配线CPH1的侧表面位于距另一个再配线CPH2相对短的距离处且与另一个再配线CPH2相反。发明人已经进一步确认了由于移动的铜离子导致的在一个再配线CPH1与另一个再配线CPH2之间的铜沉淀导致再配线CPH1和CPH2之间的电短路。
与比较例相比，在根据所述实施方式的半导体器件中，在形成聚酰亚胺膜PID之前，形成覆盖再配线CPH的侧表面的包括锰(Mn)和铜(Cu)的合金膜CMF(见图13)。然后，在形成聚酰亚胺膜PID之后，对聚酰亚胺膜PID实施热处理，从而包含在合金膜CMF中的锰(Mn)与水分(氧)反应而形成锰氧化物膜BMO。在再配线CPH的侧表面处形成包含锰氧化物膜BMO的阻挡膜BRF(见图14)。阻挡膜BRF的形成抑制由于在再配线CPH的侧表面处的聚酰亚胺膜PID中包含的水分的存在而导致的铜的离子化。
发明人已经发现，如图19中所示，即使对半导体器件进行环境试验，这种布置也可以抑制铜离子沿钝化膜PVF与聚酰亚胺膜PID之间的界面从一个再配线CPH1的侧表面向另一个再配线CPH2移动。结果，可以防止在一个再配线CPH1与另一个再配线CPH2之间的电短路。
在一个实施方式的半导体器件中，由镍膜MNI和金膜MAU形成焊盘部MPD，且金膜MAU经由镍膜MNI堆叠在再配线CPH的上表面上。这种结构可以吸收在键合铜线时生成的冲击。此外，在键合铜线时可以形成由铜线和金膜MAU的材料制成的合金。结果，可以确保将铜线键合至焊盘部MPD(金膜MAU)。应注意，镍膜MNI防止金膜MAU的金扩散到铜再配线CPH中。
当对一个实施方式的半导体器件施加环境试验、热等时，如图20中所示，阻挡膜BRF应该会破裂(见由虚线所包围的部分)。在这种情况下，再配线CPH的铜可能会暴露于包含水分的聚酰亚胺膜PID。此时，残留在阻挡膜BRF中的锰(Mn)与水分反应从而自身形成锰氧化物(氧化物膜)，如图21中所示。以这种方式，作为允许锰氧化物逐渐自身形成的结果，如图22中所示，阻挡膜BRF可以自身修复。
修改例
在上述制造方法中，当形成锰和铜的合金膜时，对施加至半导体衬底SUB的偏压进行调节使得沉积在钝化膜PVF上的铜和锰粒子的量(沉积量)基本上与通过再溅射所蚀刻的沉积的铜和锰粒子的量(蚀刻量)相同。在此，将对通过经由偏压的调节改变沉积量以及蚀刻量来形成合金膜的情况进行说明。
首先，下面将对发明人已经获得的关于偏压与合金膜的形成的发现进行说明。如图23中所示，首先，对于入射到半导体衬底上的铜离子的能量，当施加至半导体衬底SUB的偏压相对高时(在高偏压条件下)，铜离子的能量变高，而当偏压相对低时(在低偏压条件下)，铜离子的能量变低。
对于沉积在半导体衬底上的合金的再溅射量，在高偏压条件下，再溅射量大，而在低偏压条件下，再溅射量小。此外，对于再溅射的合金的粒子的角度(由钝化膜的表面相对于合金粒子飞行的方向形成的角度)，在高偏压条件下，粒子的角度从低角度至高角度分布，而在低偏压条件下，粒子的角度主要在低角度处分布。
因此，当在高偏压条件下形成合金膜时，合金粒子从各个再配线CPH的侧表面的上端到下端均匀地沉积，从而在再配线CPH的各个侧表面处形成具有基本均匀的厚度的合金膜CMF。在钝化膜PVF的上表面和再配线CPH的上表面上的合金粒子被再溅射，从而几乎不在其上沉积合金膜(见图23中关于高偏压条件的图)。
相反，当在低偏压条件下形成合金膜时，合金粒子集中沉积在再配线CPH的各个侧表面的下端侧而不是其上端侧上，从而按照从侧表面的上端侧到下端侧逐渐增加合金膜CMF的厚度的方式在再配线CPH的侧表面处形成合金膜CMF。在钝化膜PVF的上表面和再配线CPH的上表面处，没有被再溅射的合金粒子沉积为合金膜CMF(见图23中关于低偏压条件的图)。
基于所述发现，在修改例的半导体器件中，在两个步骤中形成铜和锰的合金膜。首先，在与图2至11中所示的处理相同的处理之后，在第一步骤中，在低偏压条件下形成合金膜。如图24中所示，在再配线CPH的各侧形成合金膜CMF，以使其厚度从侧表面的上端侧到下端侧逐渐增加。合金膜CMF还沉积在钝化膜PVF的上表面和再配线CPH的上表面上。
然后，在接下来的步骤中，在高偏压条件下形成合金膜。如图25中所示，沉积在钝化膜PVF的上表面和再配线CPH的上表面上的合金膜CMF被再溅射至消失。铜和锰的合金的粒子在再配线CPH的侧表面处从各个侧表面的上端到下端沉积。
通过这两个步骤，在再配线CPH的侧表面处形成合金膜CMF，以使其厚度从侧表面的上端侧到下端侧逐渐增加，同时将沉积在钝化膜PVF的上表面和再配线CPH的上表面上的合金膜CMF去除。然后，以与图14中所示的步骤相同的步骤，通过热处理将合金膜CMF氧化从而形成锰氧化物膜BMO(见图26)。以这种方式，形成阻挡膜BRF，以使其厚度从再配线CPH的侧表面的上端侧到下端侧逐渐增加(见图26)。然后，在与图15至17等中所示的步骤相同的步骤之后，如图26中所示，完成半导体器件的主要部分的制造。
如上所述，在比较例的半导体器件中，铜离子倾向于沿钝化膜PVF与聚酰亚胺膜PID之间的界面从一个再配线CPH1的侧表面向另一个再配线移动(见图18)。
在修改例中的半导体器件的再配线部CRL中，形成阻挡膜BRF，以使其厚度从再配线CPH的各侧表面的上端侧到下端侧逐渐增加。结果，在钝化膜PVF与聚酰亚胺膜PID之间的界面所处于的侧上的阻挡膜BRF的部分形成得更厚。因此，如图27中所示(由虚线箭头表示)，可以确保中断倾向于沿钝化膜PVF与聚酰亚胺膜PID之间的界面移动的铜离子的移动，使得再配线之间的铜沉淀由此确保能够防止再配线之间的电短路。
应注意，在上述半导体器件(包括修改例)中，应用锰(Mn)和铜(Cu)以自身形成如上所述的阻挡膜BRF。另外，可以应用钛(Ti)和铜(Cu)的组合物，或铝(Al)和铜(Cu)的组合物。用于阻挡膜的材料不限于这些金属，且可以使用任何金属，只要其在铜再配线的表面处形成并且使得其氧化物(氧化物膜)能够自身形成即可。在使用钛时，形成钛(Ti)氧化物膜。在使用铝时，形成铝(Al)氧化物膜。尽管将上述金属中的任一种用作用于自身形成阻挡膜BRF的金属，但由与阻挡膜中所用的金属不同的金属形成焊盘部MPD的焊盘金属膜。
第二实施方式
下文中，将对半导体器件的示例进行说明，所述半导体器件包括通过电镀方法形成的铜再配线和通过溅射方法形成的键合焊盘。
如图28中所示，在铜再配线CPH的各个侧表面上形成阻挡膜BRF。阻挡膜BRF包含例如锰氧化物膜和锰膜MF。由铜再配线CPH、阻挡膜BRF和阻挡金属膜MBR形成再配线部CRL。形成覆盖再配线部CRL的聚酰亚胺膜PID。在聚酰亚胺膜PID中形成开口PHP，从而与再配线CPH的上表面连通。
形成与位于开口PHP的底部处的再配线CPH的上表面和聚酰亚胺膜PID接触的焊盘部MPD。由钛膜MTIL和钯膜MPA形成焊盘部MPD。在钛膜MTIL上形成钯膜MPA(焊盘金属膜)。除上述之外的其它部件的结构基本上与图1中所示的半导体器件的结构相同。由相同的参考符号表示相同的构件，因此除非有必要，否则将省略并不再重复对它们的说明。
接下来，将通过示例的方式对本实施方式中的半导体器件的制造方法进行说明。在通过图2至7中所示的步骤去除光刻胶图案PR1之后，与图11中所示的步骤相同，利用化学品对铜籽晶膜和阻挡金属膜各自进行湿法蚀刻处理。因此，将铜籽晶膜和阻挡金属膜的暴露的部分去除以暴露钝化膜PVF的表面，如图29中所示。
然后，如图30中所示，通过溅射形成覆盖铜再配线CPH的锰膜MF。此时，形成与阻挡金属膜MBR的端表面接触的锰膜MF，所述阻挡金属膜MBR的端表面位于从铜再配线CPH的侧表面后退的位置。接下来，对锰膜MF的整个表面进行各向异性蚀刻，由此如图31中所示，留下位于再配线CPH的侧表面处的锰膜MF的部分，且将分别位于钝化膜PVF的上表面和铜再配线CPH的上表面上的锰膜MF的部分去除。
然后，如图32中所示，形成覆盖铜再配线CPH等的聚酰亚胺膜PID。随后，例如在近似200℃的温度下进行热处理以烧掉聚酰亚胺膜PID。在热处理中，包含在与聚酰亚胺膜PID接触的锰膜MF中的锰(Mn)被聚酰亚胺膜的水分(H2O)氧化从而形成锰氧化物膜BMO。
此时,从与聚酰亚胺膜PID接触的锰膜MF表面直至近似2nm至5nm深度位置的锰膜MF的部分被氧化，且位于比上述部分更深的位置的锰膜MF的其它部分没有被氧化而仍作为锰膜存在。以这种方式，形成包括锰氧化物膜BMO和锰膜MF的阻挡膜BRF。
然后，如图33中所示，通过光刻蚀处理和蚀刻处理在聚酰亚胺膜PID中形成暴露再配线CPH的上表面的开口PHP。之后，如图34中所示，通过溅射形成与暴露的再配线CPH的上表面和聚酰亚胺膜PID的表面接触的钛膜MTIL。随后，通过溅射形成与钛膜MTIL接触的钯膜MPA。此外，通过溅射形成与钯膜MPA接触的钛膜MTIU。
之后，如图35中所示，通过光刻蚀处理形成用于使焊盘部图案化的光刻胶图案PR3。然后，使用光刻胶图案PR3作为蚀刻掩膜对钛膜MTIU的暴露部分进行蚀刻，由此将钛膜MTIU的部分去除以暴露钯膜MPA。
然后，在去除光刻胶图案PR3之后，利用化学品对衬底进行湿法蚀刻，从而去除钯膜MPA的暴露部分，使钛膜MTIL的一部分暴露。此外，利用化学品的湿法蚀刻去除钛膜MTIU的暴露部分和钛膜MTIL的暴露部分。以这种方式，如图36中所示，形成焊盘部MPD。之后，将铜线键合至焊盘部MPD，且因此如图28中所示，完成半导体器件的主要部分的制造。
在上述半导体器件的再配线部CRL中，在再配线CPH的各个侧表面处形成包括锰氧化物膜BMO和锰膜MF的阻挡膜BRF。因此，与关于第一实施方式的说明相同，抑制由于包含在聚酰亚胺膜PID中的水分而导致的在再配线CPH的侧表面处的铜的离子化。由于抑制铜的离子化，所以防止铜在彼此相邻的一个再配线与另一个再配线之间沉淀，从而能够防止在再配线之间的电短路。
在此，在上述半导体器件中，通过溅射形成为覆盖再配线CPH的锰膜被氧化从而形成锰氧化物膜。此时，从锰膜MF的表面到预定深度位置的锰膜MF的部分被氧化，而位于比上述部分更深的位置的其它部分未被氧化仍作为锰膜存在。
因此，与通过氧化经再溅射而沉积在再配线CPH的侧表面处的合金膜CMF产生的阻挡膜BRF相比，可以将包括锰氧化物膜BMO和锰膜MF的阻挡膜BRF制作得较厚作为阻挡膜BRF。即使阻挡膜BRF破损，剩下的锰膜也能被氧化从而确保锰氧化物(膜)能够自身形成，从而提高自身修复阻挡膜BRF的功能。
在根据一个实施方式的半导体器件中，由钛膜MTIL和钯膜MPA形成焊盘部MPD。经钛膜MTIL将钯膜MPA层叠在再配线CPH的上表面上。因此，可以吸收在键合铜线时生成的冲击，且当键合铜线时可以由铜线和钯膜MPA形成合金。结果，可以确保将铜线键合至焊盘部MPD(钯膜MPA)。应注意，钛膜MTIL抑制包括在钯膜MPA中的钯扩散到铜再配线CPH中。
应注意，在上述半导体器件中，应用锰(Mn)膜以自身形成如上所述的阻挡膜BRF。另外，可以应用钛(Ti)膜、铝(Al)膜等。用于阻挡膜BRF的材料不限于这些金属，可以使用任何金属，只要其在铜再配线的表面处形成且可以自身形成氧化物(氧化物膜)即可。在使用钛膜时，形成钛(Ti)氧化物膜。在使用铝膜时，形成铝(Al)氧化物膜。尽管将上述金属中的任一种用作自身形成阻挡膜BRF的金属，但由与在阻挡膜中所用的金属不同的金属形成焊盘部MPD的焊盘金属膜。尽管在以上说明中将聚酰亚胺膜PID用作树脂膜，但树脂膜不限于此。
应注意，根据需要可以将各个实施方式(包括修改例)中所述的各种半导体器件进行组合。
已经基于实施方式对发明人所完成的本发明进行了具体说明。很明显，本发明不限于上述实施方式，且在不背离本发明的主旨和范围的情况下可以完成各种修改和改变。

Claims (17)

1.一种半导体器件，包括：
半导体衬底，所述半导体衬底具有主表面；
多层布线，所述多层布线包括分别形成在所述半导体衬底的所述主表面上方并且具有与所述主表面不同的高度的布线；
钝化膜，所述钝化膜形成为覆盖所述多层布线中的设置在从所述主表面起最高位置的最上层布线，所述钝化膜具有与所述最上层布线连通的开口；
再配线部，所述再配线部包括形成为与所述最上层布线的位于所述开口中的部分接触的再配线，所述再配线具有侧表面和上表面；
焊盘部，所述焊盘部形成为与所述再配线的所述上表面接触；以及
树脂膜，所述树脂膜形成为覆盖所述再配线部，
其中，所述再配线部包括形成为与所述再配线的所述侧表面接触的阻挡膜，所述阻挡膜包含金属氧化物膜，并且
其中，所述焊盘部包括由与用于所述阻挡膜的材料不同的材料制成的焊盘金属膜。
2.根据权利要求1所述的半导体器件，
其中，所述阻挡膜的所述金属氧化物膜包含从由锰(Mn)氧化物膜、钛(Ti)氧化物膜和铝(Al)氧化物膜组成的组中选择的任一个。
3.根据权利要求1所述的半导体器件，
其中，在所述再配线部中，所述阻挡膜的在所述再配线的所述侧表面的下端侧形成的部分的厚度大于所述阻挡膜的在所述侧表面的上端侧形成的部分的厚度。
4.根据权利要求1所述的半导体器件，
其中，所述阻挡膜包括从由锰(Mn)膜和作为所述金属氧化物膜的锰(Mn)氧化物膜的层叠膜、钛(Ti)膜和作为所述金属氧化物膜的钛(Ti)氧化物膜的层叠膜、以及铝(Al)膜和作为所述金属氧化物膜的铝(Al)氧化物膜的层叠膜组成的组中选择的任一个层叠膜。
5.根据权利要求1所述的半导体器件，
其中，所述再配线部包括形成为与所述最上层布线的位于所述开口中的部分接触的第一阻挡金属膜，
其中，所述再配线形成为在所述第一阻挡金属膜介于所述最上层布线与所述再配线之间的情况下与所述第一阻挡金属膜接触，并且
其中，所述阻挡膜形成为与所述第一阻挡金属膜的端表面接触。
6.根据权利要求5所述的半导体器件，
其中，所述第一阻挡金属膜包括铬(Cr)膜和第一钛(Ti)膜中的至少一个。
7.根据权利要求1所述的半导体器件，
其中，所述焊盘部包括形成为与所述再配线的所述上表面接触的第二阻挡金属膜，并且
其中，所述焊盘金属膜形成为在所述第二阻挡金属膜介于所述再配线与所述焊盘金属膜之间的情况下与所述第二阻挡金属膜接触。
8.根据权利要求7所述的半导体器件，
其中，所述第二阻挡金属膜为镍(Ni)膜，并且
其中，所述焊盘金属膜为金(Au)膜。
9.根据权利要求7所述的半导体器件，
其中，所述第二阻挡金属膜为第二钛(Ti)膜，并且
其中，所述焊盘金属膜为钯(Pd)膜。
10.根据权利要求1所述的半导体器件，
其中，所述再配线由铜膜形成，
其中，所述最上层布线由铝膜形成，并且
其中，所述再配线的厚度大于所述最上层布线的厚度。
11.一种制造半导体器件的方法，包括以下步骤：
在具有主表面的半导体衬底的所述主表面上方形成多层布线，所述多层布线包括具有与所述主表面不同的高度的布线；
形成覆盖所述多层布线中的设置在从所述主表面起最高位置的最上层布线的钝化膜；
在所述钝化膜中，形成用于暴露所述最上层布线的开口；
形成与从所述开口暴露的所述最上层布线接触的再配线部，所述再配线部包括具有侧表面和上表面的再配线；以及
形成与所述再配线的所述上表面接触的焊盘部，
其中，形成所述再配线部的步骤包括以下步骤：
除所述钝化膜的表面和所述再配线的所述上表面之外，在所述再配线的所述侧表面处形成包含至少第一金属的金属膜；以及
形成包含第一金属氧化物膜的阻挡膜，所述第一金属氧化物膜通过对所述金属膜施加热处理而导致的所述第一金属的氧化来形成，并且
其中，形成所述焊盘部的步骤包括以下步骤：
由与用于所述阻挡膜的材料不同的材料形成焊盘金属膜。
12.根据权利要求11所述的半导体器件的制造方法，
其中，形成所述金属膜的步骤包括以下步骤：
通过在所述钝化膜的所述表面处蚀刻同时沉积所述第一金属和与所述第一金属不同的第二金属，来在所述再配线的所述侧表面上方沉积所述第一金属和所述第二金属作为所述金属膜，并且
其中，在以下条件下沉积所述金属膜：在所述钝化膜的所述表面处的所述第一金属和所述第二金属的沉积量与沉积的所述第一金属和所述第二金属的蚀刻量基本上相同。
13.根据权利要求11所述的半导体器件的制造方法，
其中，形成所述金属膜的步骤包括以下步骤：
通过在所述钝化膜的所述表面处蚀刻同时沉积所述第一金属和与所述第一金属不同的第二金属，来在所述再配线的所述侧表面上方沉积所述第一金属和所述第二金属作为所述金属膜，并且
其中，在以下条件下沉积所述金属膜：在所述钝化膜的所述表面处的所述第一金属和所述第二金属的沉积量与沉积的所述第一金属和所述第二金属的蚀刻量不同。
14.根据权利要求12所述的半导体器件的制造方法，
其中，在形成所述金属膜的步骤中，将从由锰(Mn)、钛(Ti)和铝(Al)组成的组中选择的任一个金属用作所述第一金属，并且
其中，将铜(Cu)用作所述第二金属。
15.根据权利要求11所述的半导体器件的制造方法，
其中，形成所述金属膜的步骤包括以下步骤：
由所述第一金属形成第一金属膜以覆盖所述钝化膜和所述再配线；以及
通过蚀刻所述第一金属膜将所述第一金属膜的分别位于所述再配线的所述上表面和所述钝化膜的所述表面上方的部分去除，同时留下所述第一金属膜的位于所述再配线的所述侧表面处的部分。
16.根据权利要求15所述的半导体器件的制造方法，
其中，在形成所述金属膜的步骤中，将从由锰(Mn)膜、钛(Ti)膜和铝(Al)膜组成的组中选择的任一个用作所述第一金属膜。
17.根据权利要求11所述的半导体器件的制造方法，还包括以下步骤：
形成覆盖所述再配线部和所述钝化膜的树脂膜；以及
对所述树脂膜施加热处理，
其中，对所述树脂膜施加热处理的步骤包括对所述金属膜施加热处理的步骤。
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