TWI483314B - 通過裝設附加保護層以在運送期間保護半導體裝置的反應性金屬表面的技術 - Google Patents
通過裝設附加保護層以在運送期間保護半導體裝置的反應性金屬表面的技術 Download PDFInfo
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- TWI483314B TWI483314B TW101108409A TW101108409A TWI483314B TW I483314 B TWI483314 B TW I483314B TW 101108409 A TW101108409 A TW 101108409A TW 101108409 A TW101108409 A TW 101108409A TW I483314 B TWI483314 B TW I483314B
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- Prior art keywords
- layer
- copper
- contact surface
- protective layer
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims description 82
- 229910052751 metal Inorganic materials 0.000 title claims description 29
- 239000002184 metal Substances 0.000 title claims description 29
- 239000010410 layer Substances 0.000 claims description 146
- 238000000034 method Methods 0.000 claims description 103
- 238000004519 manufacturing process Methods 0.000 claims description 79
- 238000001465 metallisation Methods 0.000 claims description 78
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 69
- 229910052802 copper Inorganic materials 0.000 claims description 69
- 239000010949 copper Substances 0.000 claims description 69
- 230000008569 process Effects 0.000 claims description 65
- 239000000463 material Substances 0.000 claims description 57
- 239000011241 protective layer Substances 0.000 claims description 53
- 238000002161 passivation Methods 0.000 claims description 45
- 239000003989 dielectric material Substances 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 17
- 238000003631 wet chemical etching Methods 0.000 claims description 16
- 238000000059 patterning Methods 0.000 claims description 13
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 12
- 239000012876 carrier material Substances 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052684 Cerium Inorganic materials 0.000 claims description 3
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 claims description 3
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 2
- 239000005751 Copper oxide Substances 0.000 claims description 2
- 229910000431 copper oxide Inorganic materials 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims 2
- 229910052788 barium Inorganic materials 0.000 claims 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 17
- 229910000679 solder Inorganic materials 0.000 description 13
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 238000005260 corrosion Methods 0.000 description 6
- 230000007797 corrosion Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 238000004377 microelectronic Methods 0.000 description 6
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000005219 brazing Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910000420 cerium oxide Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920000768 polyamine Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 229910001362 Ta alloys Inorganic materials 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- -1 hafnium oxynitride Chemical compound 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000009972 noncorrosive effect Effects 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
- 229910002058 ternary alloy Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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Description
本揭示內容大體有關於積體電路的領域,且更特別的是,有關於用以裝設基於銅及其類似者之高度導電接觸墊於精密金屬化結構中的後端製程。
積體電路的製造涉及許多複雜的製程步驟以在適當半導體材料中及上方形成電路元件,例如電晶體、電容器、電阻器、及其類似者。近年來,在積體電路的整合密度及整體機能上已有重大的進步。這些進步的達成是通過把個別電路元件縮放到在深次微米範圍內的尺寸,目前所用的關鍵尺寸,例如場效應電晶體的柵極長度,為30納米(nm)以下。因此,在晶粒區中可裝設數百萬個電路元件,其中也必須設計複雜的互連結構,通常每個電路元件可能電氣連接至一或更多其他電路元件。這些互連結構通常建立於包含一或更多接線層級(wiring level)的金屬化系統,其中根據考量下的電路組構用與多層印刷電路板類似的方式來形成適當的金屬特徵,其中,不過,金屬特徵的尺寸必須適於半導體電路元件(例如電晶體及其類似者)的尺寸。
數十年來,由於有中高的導熱及導電係數、自我限制產生鈍化性氧化物層以及相容於用來製造整合裝置的其他材料及製程技術,而選擇鋁作為在半導體裝置之金屬化層中形成金屬特徵的金屬。隨著電路尺寸持續地減小,也造成金屬特徵尺寸有以下情況:裝置的整體訊號延遲不再受
限於個別半導體電路元件的效能,例如電晶體的切換速度,而實質取決於金屬化系統的寄生時間常數,這是由鋁的受限導電係數與相鄰金屬區域之間的寄生電容造成。因此,在現代積體電路中,高度導電金屬(例如,銅及其合金)用來適應在裝置操作期間所遭遇的高電流密度,同時利用低k值介電材料可減少寄生電容,應瞭解它是電介質常數在3.0以下的電介質。
在製造積體電路的前面階段,常需要封裝晶片以及提供用於連接晶片電路及周邊的引線及端子。在有些封裝技術中,晶片、晶片封裝體或其他適當單元可用由所謂焊錫凸塊形成的焊球連接,焊球是形成於這些單元中之至少一個的對應層上,例如微電子晶片的介電鈍化層上。為了連接微電子晶片與對應載體,在兩個待連接個別單元(亦即,包含例如多個電路的微電子晶片與對應封裝體)的表面上已形成適當的墊片配置以在提供給這些單元中之至少一者(例如,微電子晶片)的焊錫凸塊回焊後使這兩個單元電氣連接。在其他的技術中,可能必須形成要連接至對應接線的焊錫凸塊,或可使焊錫凸塊與用作散熱器之另一基板的對應墊片區接觸。結果,有必要形成可能分佈於整個晶片區的大量焊錫凸塊,借此依照現代微電子晶片之高頻應用系統的要求來提供,例如,I/O(輸入/輸出)能力以及所欲低電容配置,其中現代微電子晶片常包含複雜的電路,例如微處理器、儲存電路及其類似者及/或包含形成完整複雜電路系統的多個積體電路。
用於連接晶片與封裝體的另一方法包括打線接合技術(wire bonding technique),數十年來其基於鋁成功地發展且仍被公認有效以及為用於使大量半導體晶片連接至載體基板的主導技術,其中常常提供鋁基焊墊,其與由鋁、銅、金及其類似者製成的適當接線接觸。在打線接合製程期間,則使焊線的末端與焊墊接觸。在施加壓力、升高溫度及超音波能量後,使接線(必要時,在其上形成小球)焊接至焊墊以便形成介金屬連接(intermetallic connection)。之後,焊線的另一端接合至封裝體的引腳(lead pin),其中在接合期間以機械方式固定該半導體晶片。
不過,在製造各種不同產品的設施中,許多先進半導體裝置鑒於裝置效能、整合密度及製程相容性(process compatibility)而可能有銅基金屬化結構,然而其中,至載體基板或封裝體的連接是要用打線接合建立,因為相比於例如CPU及其他高度複雜IC,對於I/O能力的要求較小,以及打線接合技術有高於基於複雜凸塊之技術的經濟優勢。例如,精密記憶裝置可能要求極複雜高效能的金屬化系統,然而基於打線接合容易實現I/O能力。不過,在生產環境中,銅焊墊的打線接合非常難以實現,因為銅表面會不均勻地自我氧化以及廣泛地腐蝕,這可能導致高度不可靠的焊接。亦即,焊墊和與其連接的焊線受苦於顯著的腐蝕,特別是暴露於精密環境條件時,這在正常操作下可能發生,特別是在以升高溫度進行測試的期間。
不過,在製造各種不同產品的半導體設施中,多種先
進半導體裝置鑒於裝置效能、整合密度及製程相容性而可能有銅基金屬化結構,然而其中至載體基板或封裝體是要用打線接合建立,因為相比於例如CPU及其他高度複雜積體電路,對於I/O能力的要求較小,以及打線接合技術有高於基於複雜凸塊之技術的經濟優勢。例如,精密記憶裝置可能要求極複雜高效能的金屬化系統,然而基於打線接合容易實現I/O能力。在生產環境中,銅焊墊的打線接合可能要求無腐蝕的表面區域以便讓焊線與含銅接觸面之間有可靠的介金屬連接(inter-metallic connection)。
不論是要用複雜凸塊結構還是打線接合技術來連接半導體晶片與適當載體材料或封裝體,通常不同的製造環境一方面涉及形成複雜金屬化系統,而另一方面涉及執行最終製造步驟,包括半導體晶片的切晶(dicing)及封裝。製程的對應分裂,這在當前半導體製造架構公認有效,可能涉及與複雜銅基金屬化系統有關的其他問題,這在說明第1a圖至第1d圖時會更詳細地描述。
第1a圖的橫截面圖示意圖示處於很前面製造階段的半導體裝置100。半導體裝置100包含有電路元件103形成於其中及上方的基板101,例如矽材料,或任何其他適當載體材料用於形成半導體層102於其上。例如,按照實作想要的電路功能的要求,電路元件103可包含電晶體、電容器、電阻器及其類似者。此外,金屬化系統150形成於電路元件103上方以及通常包含多個金屬化層151、…、154,它們每個至少包含對應金屬線路以便提供內層電氣連
接,同時也提供垂直接觸或通孔以便使一個金屬化層與相鄰金屬化層電氣連接。例如,金屬化層151包含適當介電材料151a,它可包含埋藏金屬線路或區域151b的精密低k值介電材料,如上述,它通常基於銅材料來形成。同樣,金屬化層152可包含介電材料152a以及金屬特徵152b,其中也可提供帽蓋層152c以便可靠地覆蓋金屬化層151的任何金屬特徵以及在圖案化介電材料152a時也用作蝕刻中止材料。例如,帽蓋層的典型材料為氮化矽,富含氮的碳化矽及其類似者。同樣,金屬化層153可包含介電材料153a與對應金屬特徵153b,接著是帽蓋層154c。金屬化層154為系統150的最終或最後金屬化層以及包含適當介電材料154a與金屬區域154b,金屬區域154b也可視為接觸區域以便在後面製造階段接受適當凸塊元件或接受焊線。如上述,金屬區域154b可包含銅材料從而有含銅表面154s,也可稱它為接觸面。此外,帽蓋層155c由金屬化層154形成以便適當局限金屬區域154b以及使得能夠對鈍化層堆疊160執行適當圖案化製程,鈍化層堆疊160可包含多個不同材料層,例如層161、162及其類似者。鈍化層堆疊160通常可包含諸如二氧化矽、氮氧化矽、氮化矽及之類的材料。
如第1a圖所示的半導體裝置100是基於任何適當製程策略來形成,其中基板101的加工是以晶片為基礎,亦即,在基板101中或上提供多個半導體晶粒區以便形成多個實質相同的半導體裝置。為此目的,半導體設施通常包
含多個製程模組,例如光刻模組、蝕刻模組、回火模組、植入模組及其類似者,其中基板101的加工是根據與半導體裝置100之要求一致的專屬製程處方。因此,在完成基於半導體的電路元件103後,利用精密製程技術來形成金屬化系統150,這通常可能包括沈積及圖案化適當的介電材料以便各自形成開口於其中,隨後會用銅基材料及適當阻障材料(未圖示)填滿這些開口,接著移除任何多餘材料。因此,通過應用基本上相同的製程策略,一層接一層地形成多個金屬化層151、…、154,然而其中,可能必須適應考量下的金屬化層的對應關鍵尺寸。最後,形成最終金屬化層154以便包含金屬區域154b而有與進一步加工一致的適當定位及適當橫向尺寸,亦即,形成焊錫凸塊或提供用於打線接合製程之接合區(bond area)者。在形成帽蓋層155c後,基於公認有效之製程技術來沈積層堆疊160,其中通常可應用基於光刻技術及基於電漿之蝕刻處方的另一圖案化製程。
第1b圖示意圖示處於更進一步製造階段的半導體裝置100。如圖示,開口160a形成於鈍化層堆疊160中以及也可延伸穿過帽蓋層155c從而暴露銅表面154s之一部份。為此目的,可應用任何適當基於電漿之蝕刻處方與光刻技術。如圖示,基於包含多個晶粒區110的基板101可執行到達此製造階段的加工。經常,在遠端製造設施中可繼續該進一步加工,其中實作專屬加工設備及製造策略以便完成半導體裝置100,這通常包括在把基板切成個別半
導體晶片後形成適當凸塊結構或執行打線接合製程。結果,如140所示,基板101可輸送至不同的製造環境,不過,這可能導致一定程度的表面污染,例如通過氧化及其類似者,通過形成高度不規則表面,在基於在輸送140期間被污染的銅表面154s來形成適當凸塊結構或執行打線接合製程時,這可能產生對應的良率損失。
結果,已有人建議,在實際圖案化鈍化層堆疊160(參考第1b圖)之前半導體裝置100,不過,這在遠端製造設施可能需要許多附加資源,因為必須執行光刻製程與基於電漿之蝕刻製程。在其他方法中,金屬區域154b可接受例如由鋁構成的最終金屬層(terminal metal layer,未圖示),鋁公認有效可用於形成凸塊結構於其上或執行打線接合製程的材料。不過,就此情形而言,在製造金屬化系統150的製造環境中必須提供許多附加資源。
第1d圖的橫截面圖示意圖示處於更進一步製造階段的半導體裝置100,其中可裝設另一鈍化層170,例如聚醯胺層,其中可形成數個焊錫凸塊結構171以便連接至接觸銅表面154s。為此目的,對於聚醯胺材料為公認有效的製程技術,可用來鋪設材料170以及隨後予以圖案化,接著是沈積導電材料,例如材料171b,以便提供與另一材料171a(例如,無鉛焊錫材料及其類似者)有關的適當介面特性。結果,如果在遠端製造場所完成用於形成聚醯胺材料170的半導體裝置100加工及焊錫凸塊結構171,則劣化銅表面154s(參考第1c圖)可能造成大量的良率損失,除非
做大量的再加工(reworking),不過,這可能需要通常在任何此類製造場所無法取得的額外加工工具資源。另一方面,在形成金屬化系統150的製造設施中提供專屬最終金屬層(例如,鋁)或形成焊錫凸塊結構171,可能需要經常與半導體製造設施之現有設備及組態不相容的附加資源。
鑒於上述情形,本揭示內容有關於數種製造策略及半導體裝置,其中可形成到達在遠端製造環境可完成之製造階段(亦即,聚醯胺加工及接觸加工)的複雜銅基金屬化系統,同時避免或至少減少上述問題中之一或更多的影響。
本揭示內容大體提供數種製造技術及半導體裝置,其中形成於最終或最後金屬化層上方的鈍化層可適當地予以圖案化以避免在進一步加工期間的基於電漿之精密蝕刻製程,同時可鈍化最終金屬化層之接觸區域的敏感含銅接觸面以便允許輸送及相當長的等候時間(queue time),而表面實質不會惡化。因此,可在遠端製造設施繼續該進一步加工而不需要與基於電漿之蝕刻製程有關的附加資源。為此目的,可加入適當保護層以便能可靠地鈍化敏感含銅接觸面,同時可實現該保護層的移除而不需要基於電漿之精密蝕刻策略。
揭示於本文的示範方法包括:在第一製造環境中,形成半導體裝置之金屬化系統的最終金屬化層。該金屬化系統形成於包含多個晶粒區之基板上方,其中該最終金屬化層包含有含銅接觸面的接觸區域。該方法更包括:形成鈍
化層堆疊於該最終金屬化層上方以及圖案化該鈍化層堆疊以便形成開口於該接觸區域中之每一者之該含銅接觸面的一部份上方。此外,該方法包括:於在遠離該第一製造環境的第二製造環境中加工該半導體裝置之前,形成保護層至少於每個接觸區域之該含銅接觸面的該部份上。
揭示於本文的另一示範方法包括:在一製造環境中,基於銅形成半導體裝置之金屬化系統,其中該金屬化系統包含含有多個金屬接觸區域的最終金屬化層。該方法更包括:形成保護層於該最終金屬化層上以及形成鈍化層堆疊於該保護層上方。另外,該方法包括:在該製造環境中執行蝕刻製程以便在不蝕刻穿過該保護層下,在該多個金屬接觸區域中之每一者上方形成開口於該鈍化層堆疊中。
揭示於本文的示範半導體裝置包括:形成於載體材料上的多個晶粒區,其中該晶粒區中之每一者包含金屬化系統,接著該金屬化系統包含具有含銅接觸面之銅基金屬區域的最終金屬化層。該半導體裝置更包含形成於該最終金屬化層上方的帽蓋層。此外,鈍化層堆疊形成於該帽蓋層上方以及包含位於該含銅接觸面之一部份上方及與該部份對齊的開口。另外,該半導體裝置包含形成於該含銅接觸面之該部份上的保護層。
儘管用如以下詳細說明及附圖所圖解說明的具體實施例來描述本揭示內容,然而應瞭解,以下詳細說明及附圖並非旨在限定本揭示內容為所揭示的特定示範具體實施
例,而是所描述的具體實施例只是用來舉例說明本揭示內容的各種方面,本發明的範疇系由隨附的權利要求定義。
本揭示內容提供數種製造技術及半導體裝置,其中一方面在形成複雜銅基金屬化系統及鈍化層堆疊以及另一方面在包括提供適當接觸方案的進一步加工(包括半導體基板的切晶及封裝)之後,基本上可實現想要的製造流程分離。為此目的,可在用來形成金屬化系統的製造環境內實現鈍化層堆疊的圖案化,其中,不過,為了提供有優異表面特性的含銅接觸面,可實作附加保護層,它可提供有充分完整性的敏感接觸面同時使得在遠端製造場所能夠有效快速地移除而不需要基於電漿之蝕刻策略。例如,在有些示範具體實施例中,在暴露接觸面上可形成適當保護材料,例如含矽及氧之介電材料,例如形式為氮氧化矽及其類似者,借此確保接觸面的完整性同時使得基於濕化學蝕刻化學法,例如使用氫氟酸(HF)及其類似者,可有效地移除。在任何適當製造階段可加入該保護層,例如在有些示範具體實施例中,在形成介電帽蓋層及沈積鈍化層堆疊之前,其中該保護層隨後在圖案化鈍化層堆疊及打開介電帽蓋層時可用作有效的蝕刻中止或蝕刻控制層。在其他示範具體實施例中,在圖案化該鈍化層堆疊以及該介電帽蓋層後在暴露敏感接觸面之一部份時可形成該保護層,借此可在任何暴露表面區上形成該保護層,因此使得在遠端製造場所基於濕化學蝕刻化學法能夠有效地移除而不會不當地影響底下的任何介電材料,例如鈍化層堆疊及其類似者的
材料。在其他示範具體實施例中,在圖案化鈍化層堆疊及介電帽蓋層後,可選擇性地形成該保護層於暴露接觸面上。為此目的,例如基於氧化製程可提供均勻氧化物層,例如氧化銅,其中,由於所得氧化物層有均勻的特性,因此在遠端製造場所可基於無掩膜濕化學蝕刻製程來實現有效及可靠的移除。
參考第2a圖至第2f圖,此時更詳細地描述其他的示範具體實施例,其中必要時也會參考第1a圖至第1d圖。
第2a圖的橫截面圖示意圖示處於進一步製造階段的半導體裝置200。半導體裝置200可包含任何適當載體材料201,例如半導體材料及其類似者,可提供適當半導體材料於其中及上方以便形成基於半導體的電路元件,也如在說明第1a圖之半導體裝置100時所解釋的。為了方便,第2a圖不圖示此類電路元件。此外,半導體裝置200可包含通常含有多個金屬化層的金屬化系統250,如圖示半導體裝置100之金屬化系統150的第1a圖所示。為了方便,第2a圖不圖示此類金屬化層。此外,金屬化系統250可包含最終金屬化層254,最終金屬化層254可包含經適當地定位及有適當橫向尺寸的適當接觸區域254b以便致能形成適當的接觸方案或執行適當的打線接合製程,也如以上所述。應瞭解,金屬化系統250的形成可基於銅,以及至少在一些金屬化層中基於低k值介電材料,也如以上所述。結果,金屬區域254b也可包含銅,有可能結合適當阻障材料,例如氮化鉭、鉭及其類似者,為了方便,這些未
圖示於第2a圖。因此,區域254b包含含銅接觸面254s,在後面製造階段它會有至少一部份暴露以便與仍待形成的所欲接觸方案一致。此外,在圖示具體實施例中,半導體裝置200可包含保護層220,它可形成於最終金屬化層254的介電材料254a上及每個區域254b的含銅接觸面254s上。在有些示範具體實施例中,保護層220可為含矽及氧之介電材料,例如氮氧化矽,或任何其他適當介電材料,基於濕化學蝕刻處方能可靠地移除它而不會造成其他介電材料的嚴重材料腐蝕,特別是,在接觸區域254b內者。例如,基於氫氟酸可有效地移除多種材料,這對基於氧化矽之材料可提供快速的移除速率同時不會不當地影響其他介電材料,例如氮化矽及其類似者,特別是濕化學蝕刻化學法不會不當地影響區域254b。可提供厚度約10至50納米的保護層220,借此在圖案化鈍化層堆疊時的進一步加工期間可提供足夠的蝕刻中止能力,然而應瞭解,可根據進一步加工來選擇任何其他厚度值。
如第2a圖所示的半導體裝置200可在特定製造環境290內形成以便形成基於半導體的電路元件與多個金屬化層,例如先前在說明半導體裝置100時提及的金屬化層。此外,在製程的最終階段,最終金屬化層254的形成可通過沈積及圖案化介電材料254a以便形成隨後可用阻障材料及銅材料填滿的適當開口,其中可用CMP(化學機械研磨法)及其類似者移除任何多餘材料。之後,例如用電漿增強CVD(化學氣相沈積法)及其類似者可沈積保護層220。應瞭
解,在製造環境290內的加工是以“晶片為基礎”進行,其中系同時加工多個晶粒區,也如以上在說明半導體裝置100之多個晶粒區110時所述。
第2b圖示意圖示在製造環境290內處於更進一步製造階段的半導體裝置200。如圖示,介電帽蓋層255c(例如氮化矽材料、富含氮的碳化矽材料及其類似者)可形成於有任何適當厚度的保護層220上方,或在有些示範具體實施例中於保護層220上以便符合整體裝置要求。此外,鈍化層堆疊260形成於帽蓋層255c上以及按需要可包含一或更多層,例如層261、262、263。例如,經常可提供氮化矽、二氧化矽、氮氧化矽。應瞭解,在有些示範具體實施例中,如果認為在進一步加工期間有不當對應材料腐蝕的話,至少最外層263可具有與保護層220不同的材料組合物。在其他情形下,可選定層堆疊260的厚度,使得可納入考慮在後面製造階段移除一部份保護層220時的特定材料腐蝕。層255c及堆疊260的形成可基於任何適當及公認有效的製程策略。
第2c圖示意圖示在製造環境290內處於更進一步製造階段的半導體裝置200。在此製造階段中,可應用基於適當蝕刻掩膜294(例如,光刻膠掩膜)的蝕刻製程295以便在鈍化層堆疊260及介電帽蓋層255c中形成開口260a。為此目的,可應用適當基於電漿之蝕刻處方以便蝕刻穿過堆疊260,有可能使用層255c作為蝕刻中止材料,其中隨後可應用另一蝕刻步驟以便蝕刻穿過層255c,同時
使用保護層220作為蝕刻中止材料或作為蝕刻控制材料。例如,多個公認有效之電漿輔助蝕刻處方可用來以對於基於氧化矽之材料(例如,二氧化矽、氮氧化矽及其類似者)有高度選擇性地蝕刻穿過層255c中以氮化矽為基礎的材料。以此方式,蝕刻製程295能可靠地中止於保護層220上或內而不會暴露含銅接觸面254s。因此,含銅接觸面254s之敏感表面積仍可靠地被保護層220覆蓋。結果,在蝕刻製程295及蝕刻掩膜294的移除之後,在通過形成接觸元件(例如,凸塊結構)繼續該加工,或製備用於打線接合製程策略之裝置及其類似者之前,半導體裝置200對於任何其他輸送活動及等待時間有適當的鈍化。結果,如240所示,在有些示範具體實施例中,半導體裝置200可輸送至遠端製造環境。
第2d圖示意圖示在製造環境280之中的半導體裝置200,可適當地裝備製造環境280以致能半導體裝置200的進一步加工。在有些示範具體實施例中,在環境280內可執行蝕刻製程281以便移除保護層220的任何暴露部份,借此重新暴露含銅接觸面254s或其至少一部份,如由鈍化層堆疊260定義者。為此目的,在有些示範具體實施例中,蝕刻製程281可以濕化學蝕刻製程完成而不需要任何電漿輔助製程環境。為此目的,可應用適當的濕化學蝕刻化學法,例如HF,以便移除保護層220的暴露部份而不會不當地影響區域254b。應瞭解,由於保護層220的厚度減少,一定程度的腐蝕(如260r所示)對於進一步加工及最
終所得裝置特性不會有負面影響,其中,如有必要,在選擇層堆疊260的初始厚度以及選擇初始厚度減少的開口260a時,可輕易地納入考慮任何此類材料腐蝕。結果,含銅接觸面254s之表面區域的暴露可基於無掩膜蝕刻製程,亦即不需要專屬的帶圖案光刻膠材料,其中中高蝕刻速率可造成有效率的整體加工流程。基於暴露含銅接觸面254s之表面區域,可繼續該進一步加工,例如通過形成適當凸塊結構,如在說明第1d圖之半導體裝置100時所解釋的。就此情形而言,可提供對應介電材料,例如形式為聚醯胺,以及可應用適當製程順序用來形成阻障材料及凸塊材料,隨後可基於任何公認有效之製程策略來圖案化該凸塊材料。在其他情形下,含銅接觸面254s之表面區域可為在後面製造階段用以執行打線接合製程的接合區。就此情形而言,可在實際打線接合製程之前的任何適當階段執行蝕刻製程281,借此可確保含銅接觸面254s的完整性從而致能與焊線直接連接。
第2e圖根據其他示範具體實施例示意圖示半導體裝置200。應瞭解,半導體裝置200可在製造環境290中加工,如第2a圖至第2c圖所示。如圖示,可圖案化鈍化層堆疊260及介電帽蓋層255c(此時其直接形成於介電材料254a及含銅接觸面254s上),以便形成開口260a而暴露部份含銅接觸面254s。在此製造階段中,可基於任何適當沈積技術例如共形沉積來沈積保護內襯,其中也可選定材料組合物以便允許基於濕化學蝕刻化學法來快速及有效地
移除保護層220,如上述。例如,可使用二氧化矽、氮氧化矽、非晶碳及其類似者,只要這些材料在任何延長等待時間及輸送活動期間可保證含銅接觸面254s的充分完整性。結果,在如第2e圖所示的狀態下,半導體裝置200可輸送至製造環境280(參考第2d圖)以及可應用對應蝕刻製程,從而有效地移除保護層220。就此情形而言,可避免不當地暴露鈍化層堆疊260及帽蓋層255c,因為這些元件可能只在最終階段(亦即在某一過度蝕刻時期)暴露於可能允許可靠地暴露含銅接觸面254s的反應性蝕刻環境。之後,可繼續該進一步加工,如上述。
第2f圖根據其他示範具體實施例示意圖示半導體裝置200。如圖示,在鈍化層堆疊260及帽蓋層255c中可裝設開口260a,借此初始暴露含銅接觸面254s之一部份。之後,可高度選擇性地形成保護層220,例如通過執行電化學沈積製程以便形成作為導電帽蓋材料的保護層220,它在專屬濕化學蝕刻化學法中有想要的高移除速率。例如,基於無電鍍覆技術,可有效地形成多種公認有效之導電阻障材料,例如鉭、鈦、包含鎢、鈷、磷及其類似者的二元或三元合金。基於適當蝕刻化學法,也可移除這些材料,這也可能導致移除形成於鈍化層堆疊260上的任何金屬殘留物。在其他情形下,基於氧化製程205,可實現保護層220的選擇性形成,其中銅材料的氧化可基於高度可控制的製程條件,借此在層厚度及材料組合物方面,可形成均勻及有可預測、可再制材料特性的保護層220。以此
方式,可用保護層220、其餘區域254b之介面來形成實際含銅接觸面254s。因而,保護層220可鈍化區域254b從而在輸送半導體裝置200至遠端製造環境時可提供有必要完整性的區域254b。之後,可應用適當濕化學蝕刻製程以便有效地移除高度均勻的保護層220以及可繼續進一步加工,如上述。
結果,本揭示內容可提供數種製造技術及半導體裝置,其中可圖案化鈍化層堆疊,然而不會危及含銅接觸面的完整性。為此目的,加入適當保護材料以便至少覆蓋該接觸面中在遠端製造場所之進一步加工期間不得不暴露的一部份,這可基於有效的濕化學蝕刻製程來實現而不需要電漿輔助蝕刻處方及任何光刻掩膜。
本領域技術人員基於本說明可明白本揭示內容的其他修改及變體。因此,本說明應被視為僅供圖解說明而且目的是用來教導本領域技術人員實施本文提供之教導的一般方式。應瞭解,應將圖示及描述於本文的形式應視為目前為較佳的具體實施例。
100、200‧‧‧半導體裝置
101‧‧‧基板
102‧‧‧半導體層
103‧‧‧電路元件
110‧‧‧晶粒區
140‧‧‧輸送
150、250‧‧‧金屬化系統
151、152、153、154‧‧‧金屬化層
151b、254b‧‧‧區域
151a、152a、153a、154a、254a‧‧‧介電材料
152b、153b‧‧‧金屬特徵
152c、154c、155c、255c‧‧‧帽蓋層
154b‧‧‧金屬區域
154s‧‧‧銅表面
160‧‧‧鈍化層堆疊
160a、260a‧‧‧開口
161、162、261、262、263‧‧‧層
170‧‧‧鈍化層
170、171a、171b‧‧‧材料
171‧‧‧焊錫凸塊結構
201‧‧‧載體材料
205‧‧‧氧化製程
220‧‧‧保護層
254‧‧‧最終金屬化層
254s‧‧‧含銅接觸面
260‧‧‧層堆疊
281、295‧‧‧蝕刻製程
290‧‧‧製造環境
294‧‧‧蝕刻掩膜
本揭示內容的其他具體實施例皆定義於隨附權利要求中,閱讀以下參考附圖的詳細說明可更加明白該等具體實施例。
第1a圖及第1b圖的橫截面圖示意圖示根據習知策略在形成複雜銅基金屬化系統之各種製造階段期間的半導體裝置,其中第1b圖也圖示在特定製造環境中加工包含多個
晶粒區之半導體基板的上視圖;第1c圖的橫截面圖根據習知製程策略示意圖示於輸送至遠端製造設施之後的半導體裝置;第1d圖示意圖示處於更進一步製造階段的半導體裝置;第2a圖至第2c圖的橫截面圖根據示範具體實施例示意圖示在形成金屬化系統之各種製造階段期間的半導體裝置,該金屬化系統包含有數個銅基接觸區域及一鈍化層堆疊的最終金屬化層,在用於形成該金屬化系統的製造環境中,可圖案化該鈍化層堆疊;第2d圖示意圖示處於更進一步製造階段的半導體裝置200,其中根據示範具體實施例,該裝置在遠端製造設施可基於含銅接觸面的優異表面條件來加工;以及第2e圖及第2f圖根據其他示範具體實施例示意圖示在圖案化鈍化層堆疊及實作附加保護層時的橫截面圖。
200‧‧‧半導體裝置
201‧‧‧載體材料
205‧‧‧氧化製程
220‧‧‧保護層
250‧‧‧金屬化系統
254‧‧‧最終金屬化層
254a‧‧‧介電材料
254b‧‧‧區域
254s‧‧‧含銅接觸面
255c‧‧‧帽蓋層
260‧‧‧層堆疊
260a‧‧‧開口
261、262、263‧‧‧層
Claims (20)
- 一種製造半導體裝置之方法,其包含下列步驟:在第一製造環境中,形成半導體裝置的金屬化系統的最終金屬化層,該金屬化系統形成於包含多個晶粒區的基板上方,該最終金屬化層包含有含銅接觸面的接觸區域;形成鈍化層堆疊於該最終金屬化層上方;圖案化該鈍化層堆疊以便形成開口於該接觸區域中的每一者的該含銅接觸面的一部份上方;以及於在遠離該第一製造環境的第二製造環境中加工該半導體裝置之前,執行共形沉積製程以形成保護層於該接觸區域中的每一者的該含銅接觸面的該部份上及圖案化該鈍化層堆疊之上表面。
- 如申請專利範圍第1項所述的方法,其中在形成該鈍化層堆疊之前形成該保護層。
- 如申請專利範圍第2項所述的方法,其中圖案化該鈍化層堆疊的步驟包括:在不暴露該含銅接觸面的該部份下,執行蝕刻製程以及終止該蝕刻製程。
- 如申請專利範圍第1項所述的方法,其中圖案化該鈍化層堆疊的步驟包括:暴露該含銅接觸面的該部份。
- 如申請專利範圍第4項所述的方法,其中該保護層形成於該鈍化層堆疊上以及於該含銅接觸面的該暴露部份上。
- 如申請專利範圍第4項所述的方法,其中該保護層選擇 性地形成於該含銅接觸面的該暴露部份上。
- 如申請專利範圍第6項所述的方法,其中形成該保護層成為氧化銅層。
- 如申請專利範圍第1項所述的方法,其中形成該保護層的步驟包括:形成含矽及氧的材料層。
- 如申請專利範圍第1項所述的方法,還包含下列步驟:在該第二製造環境中,通過執行濕化學蝕刻製程,至少由該含銅接觸面的該部份移除該保護層。
- 如申請專利範圍第9項所述的方法,其中該濕化學蝕刻製程是以無掩膜蝕刻製程執行。
- 如申請專利範圍第9項所述的方法,其中該濕化學蝕刻製程是基於氫氟酸(HF)來執行。
- 一種製造半導體裝置之方法,其包含下列步驟:在第一製造環境中,基於銅形成半導體裝置的金屬化系統,該金屬化系統包含含有多個金屬接觸區域的最終金屬化層;形成鈍化層堆疊於該最終金屬化層上方;圖案化該鈍化層堆疊以便形成開口於該接觸區域中的每一者的該含銅接觸面的一部份上方;以及於在遠離該第一製造環境的第二製造環境中加工該半導體裝置之前,執行共形沉積製程以形成保護層於該接觸區域中的每一者的該含銅接觸面的該部份上及圖案化該鈍化層堆疊之上表面。
- 如申請專利範圍第12項所述的方法,還包含下列步 驟:輸送該半導體裝置至第二製造環境,以及通過執行濕化學蝕刻製程來移除在該開口中的每一者內的該保護層。
- 如申請專利範圍第13項所述的方法,其中執行該濕化學蝕刻製程的步驟包括執行無掩膜蝕刻製程。
- 如申請專利範圍第13項所述的方法,其中該濕化學蝕刻製程是基於氫氟酸(HF)來執行。
- 如申請專利範圍第12項所述的方法,還包含下列步驟:在形成該鈍化層堆疊之前,形成帽蓋層於該保護層上方,其中執行該蝕刻製程的步驟包括:蝕刻穿過該帽蓋層以及使用該保護層作為蝕刻控制層。
- 如申請專利範圍第16項所述的方法,其中該保護層經形成為在該蝕刻製程中可用作蝕刻中止層。
- 如申請專利範圍第17項所述的方法,其中形成該介電材料為含矽及氧之材料。
- 一種半導體裝置,其包含:形成於載體材料上的多個晶粒區,該晶粒區中的每一者包含金屬化系統,該金屬化系統包含具有含銅接觸面的銅基金屬區域的最終金屬化層;形成於該最終金屬化層上方的帽蓋層;形成於該帽蓋層上方及包含開口的鈍化層堆疊,該開口定位於該含銅接觸面的一部份上方及與其對齊;以及形成於該含銅接觸面的該部份上及圖案化該鈍化 層堆疊之上表面的保護層。
- 如申請專利範圍第19項所述的半導體裝置,其中該保護層形成於該帽蓋層下方以及材料組合物與該帽蓋層不同。
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2011
- 2011-03-16 DE DE102011005642A patent/DE102011005642B4/de not_active Expired - Fee Related
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2012
- 2012-03-13 TW TW101108409A patent/TWI483314B/zh not_active IP Right Cessation
- 2012-03-14 KR KR1020120026291A patent/KR101345393B1/ko not_active IP Right Cessation
- 2012-03-15 US US13/421,154 patent/US8828888B2/en not_active Expired - Fee Related
- 2012-03-16 CN CN201210071418.2A patent/CN102915921B/zh not_active Expired - Fee Related
- 2012-03-16 SG SG2012019253A patent/SG184671A1/en unknown
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US6924228B2 (en) * | 2003-03-06 | 2005-08-02 | Samsung Electronics Co., Ltd. | Method of forming a via contact structure using a dual damascene technique |
US20080099913A1 (en) * | 2006-10-31 | 2008-05-01 | Matthias Lehr | Metallization layer stack without a terminal aluminum metal layer |
US20090166861A1 (en) * | 2007-12-31 | 2009-07-02 | Matthias Lehr | Wire bonding of aluminum-free metallization layers by surface conditioning |
Also Published As
Publication number | Publication date |
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DE102011005642A1 (de) | 2012-09-20 |
DE102011005642B4 (de) | 2012-09-27 |
US20120235285A1 (en) | 2012-09-20 |
TW201239987A (en) | 2012-10-01 |
CN102915921B (zh) | 2017-06-09 |
US8828888B2 (en) | 2014-09-09 |
SG184671A1 (en) | 2012-10-30 |
CN102915921A (zh) | 2013-02-06 |
KR20120106604A (ko) | 2012-09-26 |
KR101345393B1 (ko) | 2013-12-24 |
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