CN102915921B - 通过装设附加保护层以在运送期间保护半导体装置的反应性金属表面的技术 - Google Patents

通过装设附加保护层以在运送期间保护半导体装置的反应性金属表面的技术 Download PDF

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Publication number
CN102915921B
CN102915921B CN201210071418.2A CN201210071418A CN102915921B CN 102915921 B CN102915921 B CN 102915921B CN 201210071418 A CN201210071418 A CN 201210071418A CN 102915921 B CN102915921 B CN 102915921B
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layer
metal
dielectric cap
semiconductor device
contact
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CN102915921A (zh
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M·列
J·霍海格
A·奥特
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GlobalFoundries Dresden Module One LLC and Co KG
GlobalFoundries Inc
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GlobalFoundries Dresden Module One LLC and Co KG
GlobalFoundries Inc
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Abstract

一种通过装设附加保护层以在运送期间保护半导体装置的反应性金属表面的技术，在形成以铜为基础之复杂金属化系统时，最终金属化层可接受以铜为基础的接触区域，可基于专属保护层来钝化该接触区域的表面，从而允许在运送装置至远端制造场所之前图案化钝化层堆栈。因此，在远端制造场所，基于有效的无掩膜湿化学蚀刻制程，可有效地再暴露受保护的接触面。

Description

通过装设附加保护层以在运送期间保护半导体装置的反应性 金属表面的技术
技术领域
本揭示内容大体有关于集成电路的领域，且更特别的是，有关于用以装设基于铜及其类似者之高度导电接触垫于精密金属化结构中的后端制程。
背景技术
集成电路的制造涉及许多复杂的制程步骤以在适当半导体材料中及上方形成电路元件，例如晶体管、电容器、电阻器、及其类似者。近年来，在集成电路的整合密度及整体机能上已有重大的进步。这些进步的达成是通过把个别电路元件缩放到在深次微米范围内的尺寸，目前所用的关键尺寸，例如场效应晶体管的栅极长度，为30纳米(nm)以下。因此，在晶粒区中可装设数百万个电路元件，其中也必须设计复杂的互连结构，通常每个电路元件可能电气连接至一或更多其他电路元件。这些互连结构通常建立于包含一或更多接线层级(wiring level)的金属化系统，其中根据考量下的电路组构用与多层印刷电路板类似的方式来形成适当的金属特征，其中，不过，金属特征的尺寸必须适于半导体电路元件(例如晶体管及其类似者)的尺寸。
数十年来，由于有中高的导热及导电系数、自我限制产生钝化性氧化物层以及兼容于用来制造整合装置的其他材料及制程技术，而选择铝作为在半导体装置之金属化层中形成金属特征的金属。随着电路尺寸持续地减小，也造成金属特征尺寸有以下情况：装置的整体讯号延迟不再受限于个别半导体电路元件的效能，例如晶体管的切换速度，而实质取决于金属化系统的寄生时间常数，这是由铝的受限导电系数与相邻金属区域之间的寄生电容造成。因此，在现代集成电路中，高度导电金属(例如，铜及其合金)用来适应在装置操作期间所遭遇的高电流密度，同时利用低k值介电材料可减少寄生电容，应了解它是电介质常数在3.0以下的电介质。
在制造集成电路的前面阶段，常需要封装芯片以及提供用于连接芯片电路及周边的引线及端子。在有些封装技术中，芯片、芯片封装体或其他适当单元可用由所谓焊锡凸块形成的焊球连接，焊球是形成于这些单元中之至少一个的对应层上，例如微电子芯片的介电钝化层上。为了连接微电子芯片与对应载体，在两个待连接个别单元(亦即，包含例如多个电路的微电子芯片与对应封装体)的表面上已形成适当的垫片配置以在提供给这些单元中之至少一者(例如，微电子芯片)的焊锡凸块回焊后使这两个单元电气连接。在其他的技术中，可能必须形成要连接至对应接线的焊锡凸块，或可使焊锡凸块与用作散热器之另一基板的对应垫片区接触。结果，有必要形成可能分布于整个芯片区的大量焊锡凸块，借此依照现代微电子芯片之高频应用系统的要求来提供，例如，I/O(输入/输出)能力以及所欲低电容配置，其中现代微电子芯片常包含复杂的电路，例如微处理器、储存电路及其类似者及/或包含形成完整复杂电路系统的多个集成电路。
用于连接芯片与封装体的另一方法包括打线接合技术(wire bondingtechnique)，数十年来其基于铝成功地发展且仍被公认有效以及为用于使大量半导体芯片连接至载体基板的主导技术，其中常常提供铝基焊垫，其与由铝、铜、金及其类似者制成的适当接线接触。在打线接合制程期间，则使焊线的末端与焊垫接触。在施加压力、升高温度及超音波能量后，使接线(必要时，在其上形成小球)焊接至焊垫以便形成介金属连接(intermetallic connection)。之后，焊线的另一端接合至封装体的引脚(lead pin)，其中在接合期间以机械方式固定该半导体芯片。
不过，在制造各种不同产品的设施中，许多先进半导体装置鉴于装置效能、整合密度及制程相容性(process compatibility)而可能有铜基金属化结构，然而其中，至载体基板或封装体的连接是要用打线接合建立，因为相比于例如CPU及其他高度复杂IC，对于I/O能力的要求较小，以及打线接合技术有高于基于复杂凸块之技术的经济优势。例如，精密记忆装置可能要求极复杂高效能的金属化系统，然而基于打线接合容易实现I/O能力。不过，在生产环境中，铜焊垫的打线接合非常难以实现，因为铜表面会不均匀地自我氧化以及广泛地腐蚀，这可能导致高度不可靠的焊接。亦即，焊垫和与其连接的焊线受苦于显著的腐蚀，特别是暴露于精密环境条件时，这在正常操作下可能发生，特别是在以升高温度进行测试的期间。
不过，在制造各种不同产品的半导体设施中，多种先进半导体装置鉴于装置效能、整合密度及制程相容性而可能有铜基金属化结构，然而其中至载体基板或封装体是要用打线接合建立，因为相比于例如CPU及其他高度复杂集成电路，对于I/O能力的要求较小，以及打线接合技术有高于基于复杂凸块之技术的经济优势。例如，精密记忆装置可能要求极复杂高效能的金属化系统，然而基于打线接合容易实现I/O能力。在生产环境中，铜焊垫的打线接合可能要求无腐蚀的表面区域以便让焊线与含铜接触面之间有可靠的介金属连接(inter-metallic connection)。
不论是要用复杂凸块结构还是打线接合技术来连接半导体芯片与适当载体材料或封装体，通常不同的制造环境一方面涉及形成复杂金属化系统，而另一方面涉及执行最终制造步骤，包括半导体芯片的切晶(dicing)及封装。制程的对应分裂，这在当前半导体制造架构公认有效，可能涉及与复杂铜基金属化系统有关的其他问题，这在说明图1a至图1d时会更详细地描述。
图1a的横截面图示意图示处于很前面制造阶段的半导体装置100。装置100包含有电路元件103形成于其中及上方的基板101，例如硅材料，或任何其他适当载体材料用于形成半导体层102于其上。例如，按照实作想要的电路功能的要求，电路元件103可包含晶体管、电容器、电阻器及其类似者。此外，金属化系统150形成于电路元件103上方以及通常包含多个金属化层151、...、154，它们每个至少包含对应金属线路以便提供内层电气连接，同时也提供垂直接触或通孔以便使一个金属化层与相邻金属化层电气连接。例如，金属化层151包含适当介电材料151a，它可包含埋藏金属线路或区域151b的精密低k值介电材料，如上述，它通常基于铜材料来形成。同样，金属化层152可包含介电材料152a以及金属特征152b，其中也可提供帽盖层152c以便可靠地覆盖金属化层151的任何金属特征以及在图案化介电材料152a时也用作蚀刻中止材料。例如，帽盖层的典型材料为氮化硅，富含氮的碳化硅及其类似者。同样，金属化层153可包含介电材料153a与对应金属特征153b，接着是帽盖层154c。金属化层154为系统150的最终或最后金属化层以及包含适当介电材料154a与金属区域154b，金属区域154b也可视为接触区域以便在后面制造阶段接受适当凸块元件或接受焊线。如上述，金属区域154b可包含铜材料从而有含铜表面154s，也可称它为接触面。此外，帽盖层155c由金属化层154形成以便适当局限金属特征154b以及使得能够对钝化层堆栈160执行适当图案化制程，钝化层堆栈160可包含多个不同材料层，例如层161、162及其类似者。钝化层堆栈160通常可包含诸如二氧化硅、氮氧化硅、氮化硅及之类的材料。
如图1a所示的半导体装置100是基于任何适当制程策略来形成，其中基板101的加工是以晶片为基础，亦即，在基板101中或上提供多个半导体晶粒区以便形成多个实质相同的半导体装置。为此目的，半导体设施通常包含多个制程模块，例如光刻模块、蚀刻模块、回火模块、植入模块及其类似者，其中基板101的加工是根据与半导体装置100之要求一致的专属制程处方。因此，在完成基于半导体的电路元件103后，利用精密制程技术来形成金属化系统150，这通常可能包括沉积及图案化适当的介电材料以便各自形成开口于其中，随后会用铜基材料及适当阻障材料(未图示)填满这些开口，接着移除任何多余材料。因此，通过应用基本上相同的制程策略，一层接一层地形成多个金属化层151、...、154，然而其中，可能必须适应考量下的金属化层的对应关键尺寸。最后，形成最终金属化层154以便包含接触区域154b而有与进一步加工一致的适当定位及适当横向尺寸，亦即，形成焊锡凸块或提供用于打线接合制程之接合区(bond area)者。在形成帽盖层155c后，基于公认有效之制程技术来沉积层堆栈160，其中通常可应用基于光刻技术及基于电浆之蚀刻处方的另一图案化制程。
图1b示意图示处于更进一步制造阶段的装置100。如图示，开口160a形成于钝化层堆栈160中以及也可延伸穿过帽盖层155c从而暴露表面154s之一部份。为此目的，可应用任何适当基于电浆之蚀刻处方与光刻技术。如图示，基于包含多个晶粒区110的基板101可执行到达此制造阶段的加工。经常，在远端制造设施中可继续该进一步加工，其中实作专属加工设备及制造策略以便完成装置100，这通常包括在把基板切成个别半导体芯片后形成适当凸块结构或执行打线接合制程。结果，如140所示，基板101可输送至不同的制造环境，不过，这可能导致一定程度的表面污染，例如通过氧化及其类似者，通过形成高度不规则表面，在基于在输送140期间被污染的表面154s来形成适当凸块结构或执行打线接合制程时，这可能产生对应的良率损失。
结果，已有人建议，在实际图案化钝化层堆栈160(参考图1b)之前输送装置100，不过，这在远端制造设施可能需要许多附加资源，因为必须执行光刻制程与基于电浆之蚀刻制程。在其他方法中，接触区域154b可接受例如由铝构成的最终金属层(terminal metallayer，未图示)，铝公认有效可用于形成凸块结构于其上或执行打线接合制程的材料。不过，就此情形而言，在制造金属化系统150的制造环境中必须提供许多附加资源。
图1d的横截面图示意图示处于更进一步制造阶段的装置100，其中可装设另一钝化层170，例如聚酰胺层，其中可形成数个焊锡凸块171以便连接至接触面154s。为此目的，对于聚酰胺材料为公认有效的制程技术，可用来铺设材料170以及随后予以图案化，接着是沉积导电材料，例如材料171b，以便提供与另一材料171a(例如，无铅焊锡材料及其类似者)有关的适当介面特性。结果，如果在远端制造场所完成用于形成聚酰胺材料170的装置100加工及凸块结构171，则劣化表面154s(参考图1c)可能造成大量的良率损失，除非做大量的再加工(reworking)，不过，这可能需要通常在任何此类制造场所无法取得的额外加工工具资源。另一方面，在形成金属化系统150的制造设施中提供专属最终金属层(例如，铝)或形成凸块结构171，可能需要经常与半导体制造设施之现有设备及组态不兼容的附加资源。
鉴于上述情形，本揭示内容有关于数种制造策略及半导体装置，其中可形成到达在远端制造环境可完成之制造阶段(亦即，聚酰胺加工及接触加工)的复杂铜基金属化系统，同时避免或至少减少上述问题中之一或更多的影响。
发明内容
本揭示内容大体提供数种制造技术及半导体装置，其中形成于最终或最后金属化层上方的钝化层可适当地予以图案化以避免在进一步加工期间的基于电浆之精密蚀刻制程，同时可钝化最终金属化层之接触区域的敏感含铜接触面以便允许输送及相当长的等候时间(queue time)，而表面实质不会恶化。因此，可在远端制造设施继续该进一步加工而不需要与基于电浆之蚀刻制程有关的附加资源。为此目的，可加入适当保护层以便能可靠地钝化敏感含铜接触面，同时可实现该保护层的移除而不需要基于电浆之精密蚀刻策略。
揭示于本文的示范方法包括：在第一制造环境中，形成半导体装置之金属化系统的最终金属化层。该金属化系统形成于包含多个晶粒区之基板上方，其中该最终金属化层包含有含铜接触面的接触区域。该方法更包括：形成钝化层堆栈于该最终金属化层上方以及图案化该钝化层堆栈以便形成开口于该接触区域中之每一者之该含铜接触面的一部份上方。此外，该方法包括：于在远离该第一制造环境的第二制造环境中加工该半导体装置之前，形成保护层至少于每个接触区域之该含铜接触面的该部份上。
揭示于本文的另一示范方法包括：在一制造环境中，基于铜形成半导体装置之金属化系统，其中该金属化系统包含含有多个金属接触区域的最终金属化层。该方法更包括：形成保护层于该最终金属化层上以及形成钝化层堆栈于该保护层上方。另外，该方法包括：在该制造环境中执行蚀刻制程以便在不蚀刻穿过该保护层下，在该多个金属接触区域中之每一者上方形成开口于该钝化层堆栈中。
揭示于本文的示范半导体装置包括：形成于载体材料上的多个晶粒区，其中该晶粒区中之每一者包含金属化系统，接着该金属化系统包含具有含铜接触面之铜基金属区域的最终金属化层。该半导体装置更包含形成于该最终金属化层上方的帽盖层。此外，钝化层堆栈形成于该帽盖层上方以及包含位于该含铜接触面之一部份上方及与该部份对齐的开口。另外，该半导体装置包含形成于该含铜接触面之该部份上的保护层。
附图说明
本揭示内容的其他具体实施例皆定义于随附申请专利范围中，阅读以下参考附图的详细说明可更加明白该等具体实施例。
图1a及图1b的横截面图示意图示根据习知策略在形成复杂铜基金属化系统之各种制造阶段期间的半导体装置，其中图1b也图示在特定制造环境中加工包含多个晶粒区之半导体基板的上视图；
图1c的横截面图根据习知制程策略示意图示于输送至远端制造设施之后的半导体装置；
图1d示意图示处于更进一步制造阶段的半导体装置；
图2a至图2c的横截面图根据示范具体实施例示意图示在形成金属化系统之各种制造阶段期间的半导体装置，该金属化系统包含有数个铜基接触区域及一钝化层堆栈的最终金属化层，在用于形成该金属化系统的制造环境中，可图案化该钝化层堆栈；
图2d示意图示处于更进一步制造阶段的装置200，其中根据示范具体实施例，该装置在远端制造设施可基于含铜接触面的优异表面条件来加工；以及
图2e及图2f根据其他示范具体实施例示意图示在图案化钝化层堆栈及实作附加保护层时的横截面图。
具体实施方式
尽管用如以下详细说明及附图所图解说明的具体实施例来描述本揭示内容，然而应了解，以下详细说明及附图并非旨在限定本揭示内容为所揭示的特定示范具体实施例，而是所描述的具体实施例只是用来举例说明本揭示内容的各种方面，本发明的范畴系由随附的权利要求定义。
本揭示内容提供数种制造技术及半导体装置，其中一方面在形成复杂铜基金属化系统及钝化层堆栈以及另一方面在包括提供适当接触方案的进一步加工(包括半导体基板的切晶及封装)之后，基本上可实现想要的制造流程分离。为此目的，可在用来形成金属化系统的制造环境内实现钝化层堆栈的图案化，其中，不过，为了提供有优异表面特性的含铜接触面，可实作附加保护层，它可提供有充分完整性的敏感接触面同时使得在远端制造场所能够有效快速地移除而不需要基于电浆之蚀刻策略。例如，在有些示范具体实施例中，在暴露接触面上可形成适当保护材料，例如含硅及氧之介电材料，例如形式为氮氧化硅及其类似者，借此确保接触面的完整性同时使得基于湿化学蚀刻化学法，例如使用氢氟酸(HF)及其类似者，可有效地移除。在任何适当制造阶段可加入该保护层，例如在有些示范具体实施例中，在形成介电帽盖层及沉积钝化层堆栈之前，其中该保护层随后在图案化钝化层堆栈及打开介电帽盖层时可用作有效的蚀刻中止或蚀刻控制层。在其他示范具体实施例中，在图案化该钝化层堆栈以及该介电帽盖层后在暴露敏感接触面之一部份时可形成该保护层，借此可在任何暴露表面区上形成该保护层，因此使得在远端制造场所基于湿化学蚀刻化学法能够有效地移除而不会不当地影响底下的任何介电材料，例如钝化层堆栈及其类似者的材料。在其他示范具体实施例中，在图案化钝化层堆栈及介电帽盖层后，可选择性地形成该保护层于暴露接触面上。为此目的，例如基于氧化制程可提供均匀氧化物层，例如氧化铜，其中，由于所得氧化物层有均匀的特性，因此在远端制造场所可基于无掩膜湿化学蚀刻制程来实现有效及可靠的移除。
参考图2a至图2f，此时更详细地描述其他的示范具体实施例，其中必要时也会参考图1a至图1d。
图2a的横截面图示意图示处于进一步制造阶段的半导体装置200。装置200可包含任何适当载体材料201，例如半导体材料及其类似者，可提供适当半导体材料于其中及上方以便形成基于半导体的电路元件，也如在说明图1a之装置100时所解释的。为了方便，图2a不图示此类电路元件。此外，装置200可包含通常含有多个金属化层的金属化系统250，如图示装置100之金属化系统150的图1a所示。为了方便，图2a不图示此类金属化层。此外，金属化系统250可包含最终金属化层254，最终金属化层254可包含经适当地定位及有适当横向尺寸的适当接触区域254b以便致能形成适当的接触方案或执行适当的打线接合制程，也如以上所述。应了解，金属化系统250的形成可基于铜，以及至少在一些金属化层中基于低k值介电材料，也如以上所述。结果，金属区域254b也可包含铜，有可能结合适当阻障材料，例如氮化钽、钽及其类似者，为了方便，这些未图示于图2a。因此，区域254b包含含铜接触面254s，在后面制造阶段它会有至少一部份暴露以便与仍待形成的所欲接触方案一致。此外，在图示具体实施例中，装置200可包含保护层220，它可形成于金属化层254的介电材料254a上及每个区域254b的接触面254s上。在有些示范具体实施例中，保护层220可为含硅及氧之介电材料，例如氮氧化硅，或任何其他适当介电材料，基于湿化学蚀刻处方能可靠地移除它而不会造成其他介电材料的严重材料腐蚀，特别是，在接触区域254b内者。例如，基于氢氟酸可有效地移除多种材料，这对基于氧化硅之材料可提供快速的移除速率同时不会不当地影响其他介电材料，例如氮化硅及其类似者，特别是湿化学蚀刻化学法不会不当地影响区域254b。可提供厚度约10至50纳米的保护层220，借此在图案化钝化层堆栈时的进一步加工期间可提供足够的蚀刻中止能力，然而应了解，可根据进一步加工来选择任何其他厚度值。
如图2a所示的半导体装置200可在特定制造环境290内形成以便形成基于半导体的电路元件与多个金属化层，例如先前在说明半导体装置100时提及的金属化层。此外，在制程的最终阶段，金属化层254的形成可通过沉积及图案化介电材料254a以便形成随后可用阻障材料及铜材料填满的适当开口，其中可用CMP(化学机械研磨法)及其类似者移除任何多余材料。之后，例如用电浆增强CVD(化学气相沉积法)及其类似者可沉积保护层220。应了解，在制造环境290内的加工是以“晶片为基础”进行，其中系同时加工多个晶粒区，也如以上在说明装置100之多个晶粒区110时所述。
图2b示意图示在制造环境290内处于更进一步制造阶段的装置200。如图示，介电帽盖层255c，例如氮化硅材料、富含氮的碳化硅材料及其类似者，可形成于有任何适当厚度的保护层220上方，或在有些示范具体实施例中于保护层220上以便符合整体装置要求。此外，钝化层堆栈260形成于帽盖层255c上以及按需要可包含一或更多层，例如层261、262、263。例如，经常可提供氮化硅、二氧化硅、氮氧化硅。应了解，在有些示范具体实施例中，如果认为在进一步加工期间有不当对应材料腐蚀的话，至少最外层263可具有与保护层220不同的材料组合物。在其他情形下，可选定层堆栈260的厚度，使得可纳入考虑在后面制造阶段移除一部份保护层220时的特定材料腐蚀。层255c及堆栈260的形成可基于任何适当及公认有效的制程策略。
图2c示意图示在制造环境290内处于更进一步制造阶段的装置200。在此制造阶段中，可应用基于适当蚀刻掩膜294(例如，光刻胶掩膜)的蚀刻制程295以便在钝化层堆栈260及介电帽盖层255c中形成开口260a。为此目的，可应用适当基于电浆之蚀刻处方以便蚀刻穿过堆栈260，有可能使用层255c作为蚀刻中止材料，其中随后可应用另一蚀刻步骤以便蚀刻穿过层255c，同时使用保护层220作为蚀刻中止材料或作为蚀刻控制材料。例如，多个公认有效之电浆辅助蚀刻处方可用来以对于基于氧化硅之材料(例如，二氧化硅、氮氧化硅及其类似者)有高度选择性地蚀刻穿过层255c中以氮化硅为基础的材料。以此方式，蚀刻制程295能可靠地中止于保护层220上或内而不会暴露接触面254s。因此，敏感表面积254s仍可靠地被保护层220覆盖。结果，在蚀刻制程295及蚀刻掩膜294的移除之后，在通过形成接触元件(例如，凸块结构)继续该加工，或制备用于打线接合制程策略之装置及其类似者之前，装置200对于任何其他输送活动及等待时间有适当的钝化。结果，如240所示，在有些示范具体实施例中，装置200可输送至远端制造环境。
图2d示意图示在制造环境280之中的装置200，可适当地装备制造环境280以致能装置200的进一步加工。在有些示范具体实施例中，在环境280内可执行蚀刻制程281以便移除保护层220的任何暴露部份，借此重新暴露接触面区域254s或其至少一部份，如由钝化层堆栈260定义者。为此目的，在有些示范具体实施例中，蚀刻制程281可以湿化学蚀刻制程完成而不需要任何电浆辅助制程环境。为此目的，可应用适当的湿化学蚀刻化学法，例如HF，以便移除保护层220的暴露部份而不会不当地影响区域254b。应了解，由于保护层220的厚度减少，一定程度的腐蚀，如260r所示，对于进一步加工及最终所得装置特性不会有负面影响，其中，如有必要，在选择层堆栈260的初始厚度以及选择初始厚度减少的开口260a时，可轻易地纳入考虑任何此类材料腐蚀。结果，表面区域254s的暴露可基于无掩膜蚀刻制程，亦即不需要专属的带图案光刻胶材料，其中中高蚀刻速率可造成有效率的整体加工流程。基于暴露表面区254s，可继续该进一步加工，例如通过形成适当凸块结构，如在说明图1d之半导体装置100时所解释的。就此情形而言，可提供对应介电材料，例如形式为聚酰胺，以及可应用适当制程顺序用来形成阻障材料及凸块材料，随后可基于任何公认有效之制程策略来图案化该凸块材料。在其他情形下，表面区域254s可为在后面制造阶段用以执行打线接合制程的接合区。就此情形而言，可在实际打线接合制程之前的任何适当阶段执行蚀刻制程281，借此可确保接触面区域254s的完整性从而致能与焊线直接连接。
图2e根据其他示范具体实施例示意图示半导体装置200。应了解，装置200可在制造环境290中加工，如图2a至图2c所示。如图示，可图案化钝化层堆栈260及介电帽盖层255c(此时其直接形成于介电材料254a及接触面254s上)，以便形成开口260a而暴露部份接触面254s。在此制造阶段中，可基于任何适当沉积技术来沉积保护内衬220，其中也可选定材料组合物以便允许基于湿化学蚀刻化学法来快速及有效地移除保护层220，如上述。例如，可使用二氧化硅、氮氧化硅、非晶碳及其类似者，只要这些材料在任何延长等待时间及输送活动期间可保证表面254s的充分完整性。结果，在如图2e所示的状态下，装置200可输送至制造环境280(参考图2d)以及可应用对应蚀刻制程，从而有效地移除保护层220。就此情形而言，可避免不当地暴露钝化层堆栈260及帽盖层255c，因为这些组件可能只在最终阶段(亦即在某一过度蚀刻时期)暴露于可能允许可靠地暴露表面254s的反应性蚀刻环境。之后，可继续该进一步加工，如上述。
图2f根据其他示范具体实施例示意图示半导体装置200。如图示，在钝化层堆栈260及帽盖层255c中可装设开口260a，借此初始暴露表面254s之一部份。之后，可高度选择性地形成保护层220，例如通过执行电化学沉积制程以便形成作为导电帽盖材料的层220，它在专属湿化学蚀刻化学法中有想要的高移除速率。例如，基于无电镀覆技术，可有效地形成多种公认有效之导电阻障材料，例如钽、钛、包含钨、钴、磷及其类似者的二元或三元合金。基于适当蚀刻化学法，也可移除这些材料，这也可能导致移除形成于钝化层堆栈260上的任何金属残留物。在其他情形下，基于氧化制程205，可实现保护层220的选择性形成，其中铜材料的氧化可基于高度可控制的制程条件，借此在层厚度及材料组合物方面，可形成均匀及有可预测、可再制材料特性的层220。以此方式，可用层220、其余区域254b之介面来形成实际接触面254s。因而，层220可钝化区域254b从而在输送装置200至远端制造环境时可提供有必要完整性的区域254b。之后，可应用适当湿化学蚀刻制程以便有效地移除高度均匀的保护层220以及可继续进一步加工，如上述。
结果，本揭示内容可提供数种制造技术及半导体装置，其中可图案化钝化层堆栈，然而不会危及含铜接触面的完整性。为此目的，加入适当保护材料以便至少覆盖该接触面中在远端制造场所之进一步加工期间不得不暴露的一部份，这可基于有效的湿化学蚀刻制程来实现而不需要电浆辅助蚀刻处方及任何光刻掩膜。
本领域技术人员基于本说明可明白本揭示内容的其他修改及变体。因此，本说明应被视为仅供图解说明而且目的是用来教导本领域技术人员实施本文提供之教导的一般方式。应了解，应将图示及描述于本文的形式应视为目前为较佳的具体实施例。

Claims (8)

1.一种用于制造集成电路的方法，其包含下列步骤：
在第一制造环境中，形成半导体装置的金属化系统的最终金属化层，该金属化系统形成于包含多个晶粒区的基板上方，该最终金属化层包含有含铜接触面的接触区域；
执行沉积制程以于该接触区域中的每一者的该含铜接触面的暴露部份上及该最终金属化层的介电材料上形成保护层；
接触形成介电帽盖层于该保护层的上表面及该含铜接触面上，其中，该介电帽盖层是选自氮化硅或富含氮的碳化硅；
形成钝化层堆栈于该最终金属化层上方，且该钝化层堆栈接触形成在该介电帽盖层的上表面上；
图案化该钝化层堆栈及该介电帽盖层以便形成暴露该接触区域中的每一者的该含铜接触面的一部份的穿过该钝化层堆栈及该介电帽盖层的开口；以及
于在远离该第一制造环境的第二制造环境中加工该半导体装置，在该第二制造环境中至少由该含铜接触面的所暴露部分的该暴露部分上方通过执行湿化学蚀刻制程移除该保护层，其中，该湿化学蚀刻制程是以无掩膜蚀刻制程执行。
2.如权利要求1所述的方法，其中形成该保护层成为氧化铜层。
3.如权利要求1所述的方法，其中形成该保护层的步骤包括：形成含硅及氧的材料层。
4.如权利要求1所述的方法，其中该湿化学蚀刻制程是基于氢氟酸(HF)来执行。
5.一种用于制造集成电路的方法，其包含下列步骤：
在制造环境中，基于铜形成半导体装置的金属化系统，该金属化系统包含含有多个金属接触区域的最终金属化层；
形成介电帽盖层于该最终金属化层上且接触于该最终金属化层，其中，该介电帽盖层是选自氮化硅或富含氮的碳化硅；
接触形成钝化层堆栈于该介电帽盖层的上表面上；
图案化该钝化层堆栈及该介电帽盖层以便形成暴露该多个金属接触区域中的每一者的一部份的穿过该钝化层堆栈及该介电帽盖层的开口；
执行沉积制程以于在远离第一制造环境的第二制造环境中加工该半导体装置之前，形成保护层于该多个金属接触区域的暴露部分上、于该图案化的钝化层堆栈的上表面上及于该图案化的介电帽盖层上；以及
输送该半导体装置至第二制造环境且至少由该多个金属接触区域的所暴露部分上方通过执行湿化学蚀刻制程移除该保护层，其中，该湿化学蚀刻制程是以无掩膜蚀刻制程执行。
6.如权利要求5所述的方法，其中该湿化学蚀刻制程是基于氢氟酸(HF)来执行。
7.如权利要求5所述的方法，其中形成该保护层成为氧化铜层。
8.如权利要求5所述的方法，其中形成该保护层的步骤包括：形成含硅及氧的材料层。
CN201210071418.2A 2011-03-16 2012-03-16 通过装设附加保护层以在运送期间保护半导体装置的反应性金属表面的技术 Expired - Fee Related CN102915921B (zh)

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TWI483314B (zh) 2015-05-01
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US8828888B2 (en) 2014-09-09
TW201239987A (en) 2012-10-01
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US20120235285A1 (en) 2012-09-20
SG184671A1 (en) 2012-10-30

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