US20020000665A1 - Semiconductor device conductive bump and interconnect barrier - Google Patents

Semiconductor device conductive bump and interconnect barrier Download PDF

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Publication number
US20020000665A1
US20020000665A1 US09/285,666 US28566699A US2002000665A1 US 20020000665 A1 US20020000665 A1 US 20020000665A1 US 28566699 A US28566699 A US 28566699A US 2002000665 A1 US2002000665 A1 US 2002000665A1
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United States
Prior art keywords
layer
barrier layer
semiconductor device
interconnect
conductive barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US09/285,666
Inventor
Alexander L. Barr
Suresh Venkatesan
David B. Clegg
Rebecca G. Cole
Olubunmi Adetutu
Stuart E. Greer
Brian G. Anthony
Ramnath Venkatraman
Gregor Braeckelmann
Douglas M. Reber
Stephen R. Crown
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Motorola Solutions Inc
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Motorola Solutions Inc
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Publication date
Application filed by Motorola Solutions Inc filed Critical Motorola Solutions Inc
Priority to US09/285,666 priority Critical patent/US20020000665A1/en
Assigned to MOTOROLA, INC. reassignment MOTOROLA, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CLEGG, DAVID B., COLE, REBECCA G., ADETUTU, OLUBUNMI, ANTHONY, BRIAN G., BARR, ALEXANDER L., BRAECKELMANN, GREGOR, CROWN, STEPHEN R., GREER, STUART E, REBER, DOUGLAS M., VENKATESAN, SURESH, VENKATRAMAN, RAMNATH
Priority claimed from US09/609,523 external-priority patent/US6500750B1/en
Publication of US20020000665A1 publication Critical patent/US20020000665A1/en
Application status is Abandoned legal-status Critical

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Abstract

An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).

Description

    FIELD OF THE INVENTION
  • This invention relates in general to processes for forming semiconductor devices, and more particularly to processes for forming semiconductor devices including interconnect barrier layers. [0001]
  • RELATED ART
  • Forming conductive bumps over semiconductor device bond pads is becoming increasingly common as the sizes and packages of the semiconductor devices continue to shrink. The bumps are used instead of wires to electrically connect the bond pads to their respective packaging leads. One specific type of bump includes a controlled-collapse chip-connection (C[0002] 4) bump. Bumps generally require that a pad limiting metal layer be formed between the bond pad and the bump. Pad limiting metal layers typically include chrome and chromium alloys. However, these chromium-containing films can have defects, such as cracks and irregular grain boundaries, which limit the ability of the chromium layer to adequately separate the bond pad and the bump materials.
  • The bump typically includes elements such as tin (Sn) and lead (Pb). In the event the barrier fails to keep the bond pad and the bump separated, material from the bond pad can react with the lead or tin in the bump and intermetallic alloys of these materials can be formed. If the bond pad includes a copper-containing material, a brittle intermetallic alloy can be the result. The brittle intermetallic alloy can subsequently crack and result in bump failure. In addition, voids can form as a result of the alloying process and degrade adhesion between the bond pad and the bump. In extreme cases this can produce high resistance that can negatively impact the semiconductor device's performance and even result in failure of the semiconductor device.[0003]
  • BRIEF DESCRIPTION OF THE FIGURES
  • The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which: [0004]
  • FIGS. [0005] 1-7 include illustrations of cross-sectional views of forming a semiconductor device having copper interconnects and bumps in accordance with a first set of embodiments.
  • FIGS. [0006] 8-12 include illustrations of cross-sectional views of forming a semiconductor device having copper interconnects and bumps in accordance with a second set of embodiments.
  • Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention. [0007]
  • DETAILED DESCRIPTION
  • In accordance with embodiments of the present invention a semiconductor device and its method of formation are disclosed. In one embodiment, a conductive barrier layer overlies an interconnect, a passivation layer overlies the conductive barrier layer, and the passivation layer has an opening that exposes portions of the conductive barrier layer. In an alternate embodiment, a passivation layer overlies the interconnect, the passivation layer has an opening that exposes the interconnect, and a conductive barrier layer overlies the interconnect within the opening. [0008]
  • FIG. 1 includes an illustration of a cross-sectional view of a portion of a semiconductor device. The semiconductor device includes a semiconductor device substrate [0009] 100, field isolation regions 102, and doped regions 104 formed within the semiconductor device substrate 100. A gate dielectric layer 106 overlies portions of the semiconductor device substrate 100 and a gate electrode 108 overlies the gate dielectric layer 106.
  • A first interlevel dielectric layer (ILD) [0010] 110 is formed over the gate electrode 108 and the semiconductor device substrate 100. The first interlevel dielectric layer 110 is pattered to form dual inlaid openings that are filled with a adhesion/barrier layer 112 and a copper fill material 114. The adhesion/barrier layer 112 is typically a refractory metal, a refractory metal nitride, or a combination of refractory metals or their nitrides. The copper fill material 114 is typically copper or a copper alloy, wherein the copper content is at least 90 atomic percent. The copper can be alloyed with magnesium, sulfur, carbon, or the like to improve adhesion, electromigration, or other properties of the interconnect. After depositing the adhesion/barrier layer 112 and the copper fill material 114, the substrate is polished to remove portions of the adhesion/barrier layer 112 and copper fill material 114 outside of the opening.
  • After forming the first interconnect level, an insulating barrier layer [0011] 122 is formed over the copper filled interconnect and first ILD layer 110. This insulating barrier layer 122 includes silicon nitride, silicon oxynitride or the like. Using an insulating material to form the insulating barrier layer 122 eliminates the need to form additional patterning and etch processes that would otherwise be required to electrically isolate the interconnects from one another if a conductive barrier would be used. A second ILD layer 124 is formed over the insulating barrier layer 122. A dual inlaid interconnect comprising a conductive adhesion/barrier layer 126 and a copper fill material 128 is formed within the second ILD 124. The dual inlaid interconnect is formed using processes and materials similar to those used to form the dual inlaid interconnect structure in the first ILD layer 110.
  • A passivation layer [0012] 22 is then formed over the second ILD layer 124 and the dual inlaid interconnect, as shown in FIG. 2. The passivation layer can include one or more films of silicon nitride, silicon oxynitride, silicon dioxide, or the like. Portions of the passivation layer 22 closest to the copper fill material 128 typically include silicon nitride or a silicon oxynitride film having a higher concentration of atomic nitrogen relative to atomic oxygen. The passivation layer 22 is patterned to form a bond pad opening 24 that extends through the passivation layer to the copper fill material 128.
  • A conductive barrier layer [0013] 32 is deposited over the passivation layer 22 and the copper fill material 128, as shown in FIG. 3. The conductive barrier layer 32 can be deposited using processes that can include chemical vapor deposition, physical vapor deposition, evaporation deposition, electroplating, electroless plating, or the like. The thickness of this layer is generally in a range of approximately 50 to 300 nanometers (nm). Typically, the conductive barrier layer 32 includes a refractory metal, a refractory metal nitride, or a combination thereof. In one embodiment the conductive barrier layer 32 includes a combination of titanium (Ti) and titanium nitride (TiN). The titanium/titanium nitride stack improves adhesion to the underlying copper fill material 128 and passivation layer 22. Additionally, the titanium nitride forms a barrier that prevents the copper fill material from reacting with subsequently deposited conductive bumps. Alternatively, the conductive barrier layer 32 can include other materials such as tantalum (Ta), tantalum nitride (TaN), tungsten (W), titanium tungsten nitride (TiWN), titanium tungsten (TiW), tungsten nitride (WN), molybdenum nitride (MoN), cobalt nitride (CoN), or a combination of thereof. In other embodiments, oxygen tolerant materials can be used. These materials can include platinum (Pt), palladium (Pd), nickel (Ni), conductive metal oxides or their corresponding metals, or the like. The conductive metal oxides and their corresponding metals can further include iridium (Ir) and iridium oxide (IrO2); ruthenium (Ru) and ruthenium oxide (RuO2); rhenium (Re) and rhenium oxide (ReO2 and ReO3) or osmium (Os) and osmium oxide (OsO2).
  • A resist layer [0014] 34 is then formed over the conductive barrier layer 32. The resist layer 34 exposes portions of the conductive barrier layer 32 overlying the passivation layer 22. The resist is formed such that it covers the bond pad opening 34. In addition, it can also be patterned to extend slightly over surface portions of the conductive barrier layer 32 lying above passivation layer 22, as shown in FIG. 3.
  • The conductive barrier layer [0015] 32 is then etched, using conventional etching processes, to remove the exposed portions of the conductive barrier layer 32 overlying passivation layer 22. After the etch, the patterned resist layer 34 is removed using a plasma ashing process or, alternatively, using a wet chemical process that uses organic chemicals, such as N-methyl-2-pyrrolidone, acetone, methyl isobutyl ketone (MIBK) or the like.
  • Alternatively, if a plating process such as electroplating or electroless plating is used to form the conductive barrier layer, the previously described patterning process may not be necessary. Instead, the conductive barrier layer can be plated directly over the exposed portions of the copper fill material [0016] 128 after forming opening 24. If so desired, plating can proceed to the extent where the plated material overlies a portion of the passivation layer to form the conductive barrier layer 32, as shown in FIG. 4.
  • A die coat layer [0017] 52 is then formed over the semiconductor device and patterned to form a die coat opening 54 overlying the bond pad opening 24, as shown in FIG. 5. In this specific embodiment, the peripheral portion of the conductive barrier layer 32 have edges that are exposed within the die coat opening 54. The die coat layer 52 can be formed as a photo-imagable polyimide film or, alternatively, as a polyimide film that is patterned using conventional resist and etch processing.
  • Prior to forming a pad limiting metal layer [0018] 62, as shown in FIG. 6, exposed portions of the conductive barrier layer 32 are processed through a radio frequency (RF) sputter clean. The RF sputter clean improves contact resistance between the barrier layer and the pad limiting metal layer 62 by removing uppermost portions of the conductive barrier layer 32 that can contain impurities, such as oxygen, carbon, fluorine, and chlorine. In one embodiment, the RF sputter clean process is performed as part of an in-situ process prior to depositing the pad limiting metal (underbump) layer. In one embodiment, the processing parameters for performing the RF sputter clean are as follows: RF power is in a range of approximately 1200 to 1500 Watts (W), direct current (DC) bias voltage is in a range of approximately −300 to −600 volts (V), pressure is in a range of approximately 0.1 to 0.5 Pascals, and time is in a range of approximately 150 to 250 seconds. The RF sputter clean process removes approximately 20-40 nm of barrier material from the surface of the barrier layer 32.
  • The pad limiting metal layer [0019] 62 is then formed within the die coat opening 54 as illustrated in FIG. 6. A Pad limiting metal layer typically includes a functional combination of films that can include an adhesion film, an intermediate coupling/solderable film and an antioxidation barrier film. In one embodiment, the pad limiting metal layer 62 includes a composite of four different films: a chromium film 622, a chromium-copper alloy film 624, a copper film 626, and a gold film 628. The chromium film 622 and the chromium-copper alloy film 624 each have a thickness in a range of approximately 50 to 500 nm, the copper film 626 has a thickness in a range of approximately 700 to 1300 nm, and the gold film 628 has a thickness in a range of 80 to 140 nm. Alternatively, the pad limiting metal can include other combinations of films such as a composite of titanium, copper and gold or a composite of titanium, nickel, copper and gold. The pad limiting metal layer 62 is typically formed by evaporation using a shadow mask. However, other methods, such as sputtering can alternatively be used to form the pad limiting metal.
  • In accordance with one embodiment, following the formation of pad limiting metal layer, a bump material, such as a lead tin solder material [0020] 72 is deposited over the pad limiting metal layer 62 as shown in FIG. 7. The lead tin solder material 72 can be evaporated using a shadow mask or, alternatively, it can be formed using other conventional methods, such as plating or solderjetting. A reflow processing step is then performed to round the corners of the lead tin solder material 72 and form the bump as shown in FIG. 7.
  • At this point in the process, a substantially completed semiconductor device has been made. This device can subsequently be attached to a packaging substrate such as a flip chip or ball grid array package. Although not shown, other levels of interconnects can be formed as needed. Similarly, other interconnects can also be made to the gate electrode [0021] 108 and the doped region 104. If additional interconnects would be formed, they would be formed using processes similar to those used to form and deposit insulator barrier layer 122, second ILD layer 124, adhesion/barrier layer 126, and copper fill material 128.
  • FIGS. [0022] 8-12 illustrate an alternative embodiment of the present invention. Referring to FIG. 8, a conductive barrier layer 82 is formed over the second ILD layer 124 and copper fill material 128. The conductive barrier layer 82 is formed by any of the methods or materials described in forming the conductive barrier layer 32 as first shown in FIG. 3. The thickness of the conductive barrier layer 82 is typically in a range of approximately 50 to 300 nm. In this particular embodiment, an optional oxidation-resistant layer 84 is then formed over the conductive barrier layer 82. The oxidation-resistant layer can include any material that either prevents oxidation of the underlying layer or is more readily oxidized in preference to the underlying layer. Examples of materials that can be used include silicon nitride, polysilicon, amorphous silicon, or a conductive metal oxide or its corresponding conductive metal. The oxidation-resistant layer 84 has a thickness in a range of approximately 10-50 nm. A resist layer 86 is then formed over the conductive barrier layer 82 and the oxidation-resistant layer 84. The resist layer 86 is patterned to cover portions of the conductive barrier layer 82 and the oxidation-resistant layer 84 overlying the copper fill material 128 and the adhesion/barrier layer 126.
  • The unpatterned portions of conductive barrier layer [0023] 82 and oxidation-resistant layer 84 are then removed using conventional etching processes. The resist is then removed, and a passivation layer 92 is formed over the stack comprising conductive barrier layer 82 and oxidation-resistant layer 84, and portions of the dielectric layer 124 as shown in FIG. 9. The passivation layer 92 is similar to the passivation layer 22, first introduced in FIG. 2. In this particular embodiment, the passivation layer 92 is patterned to form a bond pad opening 94. As illustrated in FIG. 9, not all of the passivation layer within the bond pad opening is removed. Therefore, the bond pad opening is only partially formed during the patterning process. A residual portion 96 is left to remain over the oxidation-resistant layer 84 after patterning in complete.
  • A die coat layer [0024] 1001 is then formed and patterned to form a die coat opening 1003, as shown in FIG. 10. The die coat layer 1001 is similar to the die coat 52, as first introduced in FIG. 5. The die coat opening 1003 exposes portions of the passivation layer 92, including the residual portion 96. After forming the die coat opening 1003, an etch is performed to remove the residual portion 96 and the underlying oxidation-resistant layer 84. This forms the die coat opening 1103, as shown in FIG. 11. During this etch, portions of the passivation layer 92 exposed by the die coat layer 1001 are also etched, as indicated by the removed passivation layer portions 1102. In one particular embodiment, the passivation layer 92 includes silicon and nitrogen, such as silicon nitride or silicon oxynitride, and the oxidation-resistant layer 84 includes silicon nitride. Therefore, the same or similar etch chemistries can be used to remove the residual portions 96 of the passivation layer 92 and the oxidation-resistant layer 84.
  • Processing is continued to form a substantially completed device as shown in FIG. 12. A pad limiting metal layer [0025] 1220 is formed similar to the one previously described and includes the chromium film 1222, the chromium-copper alloy film 1224, copper film 1226, and gold film 1228, and the lead tin solder 1230. If necessary, an RF sputter cleaning process, similar to that described previously, can be used to prepare the surface of the barrier layer prior to forming the pad limiting metal layer 1220. In this particular embodiment, a reflow step is performed to round the shape of the lead tin solder, giving it a dome-like appearance, as shown in FIG. 12.
  • In the embodiments described in FIGS. [0026] 9-12, the insulating barrier layer 122 is used for all interconnect levels except for the uppermost interconnect level. The uppermost interconnect level is the interconnect level over which the bond pads are formed. Therefore, it is the only interconnect level that uses the conductive barrier layer 82.
  • There are many other embodiments that are possible with the present invention. Turning to FIG. 3, the conductive barrier layer [0027] 32 can also include an overlying oxidation-resistant layer similar to the oxidation-resistant layer 84 described in the second set of embodiments in FIGS. 8-12. Similarly, the second set of embodiments do not necessarily require the use of the oxidation-resistant layer 84 because the residual portion 96 of the passivation layer 92 allows an oxygen-containing plasma to be used without damaging the conductive barrier layer 82. This can be important when the conductive barrier layers 82 or 32 include tantalum nitride, titanium nitride, or the like, which can adversely react with oxygen-containing plasmas or other chemicals used to remove or develop resist or polyimide. Examples of these chemicals can include tetramethyl ammonium hydroxide, N-methyl-2-pyrrolidone, acetone, MIBK, and the like.
  • In addition to forming the conductive barrier layer over the bond pad as described in FIGS. [0028] 9-12, the conductive barrier material can also be used to form focused energy-alterable, or laser-alterable, connections between conductive regions of the semiconductor device. The conductivity of these connections can be modified, using the laser, to program or adjust the circuitry of the device.
  • Forming the laser-alterable connections using the conductive barrier layer has advantages over the prior art. The conductive barrier layer is typically much thinner, less thermally conductive, and less reflective than the interconnect layer, which is normally used to form the laser-alterable connection. The conductive barrier layer is also self-passivating as compared to the interconnect layer. Therefore, reliability of the laser alteration is generally improved because the potential for shorting after laser alteration is reduced. In addition the laser-alterable connection is formed closer to uppermost surface of the semiconductor device. This allows the laser to use less power to affect the conductivity of the laser-alterable connection, which correspondingly reduces the potential of causing shorts, damaging adjacent connections, and damaging the surrounding passivation layer. Furthermore, the conductive barrier layer and the laser-alterable connections can be formed simultaneously using the same layer. Therefore, the process integration requires no additional processing steps. [0029]
  • Although specific materials were listed with respect to the pad limiting metal layer [0030] 62, other materials and other variations of this integration scheme can alternatively be used. For example, the conductive barrier layer can be incorporated as part of the pad limiting metal layer. In this case, it can be evaporated or sputtered onto the wafer before forming the other respective pad limiting metal layer films. In yet another embodiment, the pad limiting metal layer and the solder material can collectively be formed by physical vapor deposition or by jet printing, whereby individual molten solder drops are deposited into place by an orifice.
  • The embodiments described herein can be integrated into an existing process flow without a need to use exotic materials, develop new processes, or purchase new processing equipment. The conductive barrier layers [0031] 32 and 82 are sufficient to prevent the copper from the interconnect and the lead tin solder from the bump from reacting with each other. Therefore, integrity is maintained at the interface between the bump and the interconnect. This improves the mechanical integrity of the bump as well as helps to reduce the electrical resistance between the bump and the interconnect.
  • In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. Benefits, other advantages, and solutions to problems have been described with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. [0032]

Claims (31)

What is claimed is:
1. A semiconductor device, comprising:
a first interconnect that overlies a semiconductor device substrate;
a insulating barrier layer that overlies the first interconnect;
a second interconnect that overlies portions of the first interconnect and the insulating barrier layer;
a conductive barrier layer that overlies a portion the second interconnect, the conductive barrier layer extending beyond an edge region of the portion of the second interconnect; and
a passivation layer that overlies the conductive barrier layer, the passivation layer having an opening that exposes portions of the conductive barrier layer.
2. The semiconductor device of claim 1, wherein the second interconnect includes mostly copper.
3. The semiconductor device of claim 1, wherein the conductive barrier layer includes a refractory metal nitride.
4. The semiconductor device of claim 1, wherein the conductive barrier layer includes a material selected from a group consisting of titanium, tantalum, tungsten, iridium, and nickel.
5. The semiconductor device of claim 1, further comprising an oxidation-resistant layer that overlies the conductive barrier layer.
6. The semiconductor device of claim 5, wherein the oxidation-resistant layer includes nitrogen.
7. The semiconductor device of claim 5, wherein the oxidation-resistant layer is a silicon layer.
8. The semiconductor device of claim 1, wherein the portion of the second interconnect is further characterized as a bond pad.
9. The semiconductor device of claim 8, wherein a portion of the conductive barrier layer is a laser-alterable connection between at least two conductive regions.
10. The semiconductor device of claim 8, further comprising
a conductive bump that overlies the bond pad.
11. A semiconductor device, comprising:
an interconnect over a semiconductor device substrate;
a passivation layer that overlies the interconnect, the passivation layer having an opening that exposes a portion of the interconnect; and
a conductive barrier layer within the opening that overlies the portion of the interconnect.
12. The semiconductor device of claim 11, wherein the conductive barrier layer covers a sidewall portion of the opening.
13. The semiconductor device of claim 12, wherein the conductive barrier layer extends over a surface portion of the passivation layer adjacent the sidewall portion.
14. The semiconductor device of claim 11, wherein the interconnect includes mostly copper.
15. The semiconductor device of claim 11, wherein the conductive barrier layer includes a refractory metal nitride.
16. The semiconductor device of claim 11, wherein the conductive barrier layer includes a material selected from a group consisting of tantalum, titanium, tungsten, iridium, and nickel.
17. The semiconductor device of claim 11, further comprising forming an oxidation-resistant layer over the conductive barrier layer.
18. The semiconductor device of claim 17, wherein the oxidation-resistant layer includes nitrogen.
19. The semiconductor device of claim 17, wherein the oxidation-resistant layer is a silicon layer.
20. The semiconductor device of claim 11, further comprising a conductive bump over the conductive barrier layer.
21. A method of forming a semiconductor device comprising:
forming a first interconnect overlying a semiconductor device substrate;
forming an insulating barrier layer overlying the first interconnect;
forming a second interconnect overlying portions of the first interconnect and the insulating barrier layer;
forming a conductive barrier layer overlying a portion of the second interconnect, the conductive barrier layer extending beyond an edge region of the portion of the second interconnect;
forming a passivation layer overlying the conductive barrier layer; and
forming an opening in the passivation layer, wherein the opening exposes portions of the conductive barrier layer.
22. The method of claim 21, further comprising forming an oxidation-resistant layer overlying conductive barrier layer.
23. The method of claim 22, wherein the oxidation-resistant layer includes a material selected from a group consisting of nitrogen and silicon.
24. The method of claim 21, wherein a portion of the conductive barrier layer forms a laser-alterable connection between at least two conductive regions.
25. The method of claim 21, wherein forming an opening in the passivation layer further comprises:
forming a partial opening in the passivation layer, wherein a depth of the partial opening is less than a thickness of the passivation layer in a region of the passivation layer where the partial opening is formed;
forming a die coat layer over the passivation layer;
forming an opening in the die coat layer, wherein forming the opening in the die coat layer exposes the partial opening in the passivation layer; and
etching the partial opening in the passivation layer to expose an underlying layer after forming an opening in the die coat layer.
26. The method of claim 21, further comprising:
removing a portion of the conductive barrier layer after forming an opening in the passivation layer, wherein the portion of the conductive barrier layer has a depth; and
forming a conductive bump over the conductive barrier layer after removing a portion of the conductive barrier layer.
27. The method of claim 26, wherein the depth is in a range of approximately 20-40 nanometers.
28. A method of forming a semiconductor device, comprising:
forming an interconnect over a semiconductor device substrate;
forming a passivation layer over the interconnect;
forming an opening in the passivation layer, the opening exposing portions of the interconnect; and
forming a conductive barrier layer within the opening, the conductive barrier layer overlying exposed portions of the interconnect.
29. The method of claim 28, further comprising forming an oxidation-resistant layer over the conductive barrier layer, wherein the oxidation-resistant layer includes a material selected from a group consisting of nitrogen and silicon.
30. The method of claim 28, wherein the conductive barrier layer covers a sidewall portion of the opening and extends over a surface portion of the passivation layer adjacent the sidewall portion.
31. The method of claim 28, wherein the interconnect includes copper.
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Cited By (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010026952A1 (en) * 1998-09-23 2001-10-04 Manfred Engelhardt Integrated circuit configuration and production method
US20020015128A1 (en) * 2000-06-21 2002-02-07 Hirokazu Sakaguchi LCD driver IC chip
US20020066959A1 (en) * 2000-12-04 2002-06-06 Rajeev Joshi Passivation scheme for bumped wafers
US20020142576A1 (en) * 1999-08-10 2002-10-03 Hitachi, Ltd. Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device
US6577011B1 (en) * 1997-07-10 2003-06-10 International Business Machines Corporation Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
US20030222295A1 (en) * 1998-12-21 2003-12-04 Megic Corporation High performance system-on-chip inductor using post passivation process
US20040053483A1 (en) * 2002-06-25 2004-03-18 Nair Krishna K. Methods of forming electronic structures including conductive shunt layers and related structures
US6798050B1 (en) * 1999-09-22 2004-09-28 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor element with copper pad mounted on wiring substrate and method for fabricating the same
US20040188851A1 (en) * 2003-03-26 2004-09-30 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20040206801A1 (en) * 2001-09-27 2004-10-21 Mis J. Daniel Electronic devices including metallurgy structures for wire and solder bonding
US20040209406A1 (en) * 2003-02-18 2004-10-21 Jong-Rong Jan Methods of selectively bumping integrated circuit substrates and related structures
US20040224497A1 (en) * 2003-05-05 2004-11-11 Hans-Joachim Barth Method to form selective cap layers on metal features with narrow spaces
US20050023590A1 (en) * 2000-12-28 2005-02-03 Jingyu Lian Multi-layer electrode and method of forming the same
US20050083592A1 (en) * 2003-09-10 2005-04-21 Yaakov Amitai High Brightness optical device
US20050082552A1 (en) * 2003-10-21 2005-04-21 Ming Fang Large bumps for optical flip chips
US6900545B1 (en) * 1999-06-25 2005-05-31 International Business Machines Corporation Variable thickness pads on a substrate surface
US20050184358A1 (en) * 1998-12-21 2005-08-25 Megic Corporation High performance system-on-chip using post passivation process
US20050206067A1 (en) * 2004-03-18 2005-09-22 Cook William P Input tray and drive mechanism using a single motor for an image forming device
US20050218527A1 (en) * 2002-07-31 2005-10-06 Fujitsu Limited Semiconductor device for preventing defective filling of interconnection and cracking of insulating film
US20050269697A1 (en) * 2004-06-04 2005-12-08 Seiko Epson Corporation Semiconductor device, circuit board, and electronic instrument
US20050279809A1 (en) * 2000-11-10 2005-12-22 Rinne Glenn A Optical structures including liquid bumps and related methods
US20060022343A1 (en) * 2004-07-29 2006-02-02 Megic Corporation Very thick metal interconnection scheme in IC chips
US20060030139A1 (en) * 2002-06-25 2006-02-09 Mis J D Methods of forming lead free solder bumps and related structures
US20060076679A1 (en) * 2002-06-25 2006-04-13 Batchelor William E Non-circular via holes for bumping pads and related structures
US20060205204A1 (en) * 2005-03-14 2006-09-14 Michael Beck Method of making a semiconductor interconnect with a metal cap
US20060205170A1 (en) * 2005-03-09 2006-09-14 Rinne Glenn A Methods of forming self-healing metal-insulator-metal (MIM) structures and related devices
US20060289961A1 (en) * 2005-06-23 2006-12-28 Seiko Epson Corporation Semiconductor device
US20070045855A1 (en) * 2005-07-22 2007-03-01 Megica Corporation Method for forming a double embossing structure
US7205221B2 (en) * 1999-09-02 2007-04-17 Micron Technology, Inc. Under bump metallization pad and solder bump connections
US20070182004A1 (en) * 2006-02-08 2007-08-09 Rinne Glenn A Methods of Forming Electronic Interconnections Including Compliant Dielectric Layers and Related Devices
US20070190776A1 (en) * 2003-09-09 2007-08-16 Intel Corporation Methods of Processing Thick ILD Layers Using Spray Coating or Lamination for C4 Wafer Level Thick Metal Integrated Flow
US20070262457A1 (en) * 1998-12-21 2007-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US20080001290A1 (en) * 2006-06-28 2008-01-03 Megica Corporation Integrated circuit (IC) chip and method for fabricating the same
US20080006905A1 (en) * 2003-01-15 2008-01-10 Infineon Technologies Ag Method for production of an integrated circuit bar arrangement, in particular comprising a capacitor assembly, as well as an integrated circuit arrangement
US20080035974A1 (en) * 1998-12-21 2008-02-14 Megica Corporation High performance system-on-chip using post passivation process
US20080042280A1 (en) * 2006-06-28 2008-02-21 Megica Corporation Semiconductor chip structure
US20080099913A1 (en) * 2006-10-31 2008-05-01 Matthias Lehr Metallization layer stack without a terminal aluminum metal layer
US20080102540A1 (en) * 2006-10-31 2008-05-01 Tobias Letz Technique for forming a passivation layer without a terminal metal
WO2008054680A2 (en) * 2006-10-31 2008-05-08 Advanced Micro Devices, Inc. A metallization layer stack without a terminal aluminum metal layer
US20080284014A1 (en) * 2007-03-13 2008-11-20 Megica Corporation Chip assembly
US20080284032A1 (en) * 2005-03-29 2008-11-20 Megica Corporation High performance system-on-chip using post passivation process
DE102007057689A1 (en) * 2007-11-30 2009-06-04 Advanced Micro Devices, Inc., Sunnyvale A semiconductor device having a chip area which is designed for an aluminum-free Lothöckerverbindung, and a test structure that is designed for an aluminum-free wire connection
US20090184394A1 (en) * 1998-12-21 2009-07-23 Megica Corporation High performance system-on-chip inductor using post passivation process
US7674701B2 (en) 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
US20100283073A1 (en) * 2007-09-28 2010-11-11 Osram Opto Semiconductors Gmbh Thin-Film LED Having a Mirror Layer and Method for the Production Thereof
US7973629B2 (en) 2001-09-04 2011-07-05 Megica Corporation Method for making high-performance RF integrated circuits
US8008775B2 (en) 2004-09-09 2011-08-30 Megica Corporation Post passivation interconnection structures
US8018060B2 (en) 2004-09-09 2011-09-13 Megica Corporation Post passivation interconnection process and structures
US20110233796A1 (en) * 2010-03-23 2011-09-29 Kim Deok-Kee Semiconductor Devices and Electronic Systems
DE102011005642A1 (en) * 2011-03-16 2012-09-20 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG A method for protecting reactive metal surfaces of semiconductor devices during transport by providing an additional protective layer
US20130029483A1 (en) * 2008-07-15 2013-01-31 Semiconductor Manufacturing International (Shanghai) Corporation Method and system for forming conductive bumping with copper interconnection
US8878365B2 (en) 2005-07-13 2014-11-04 Seiko Epson Corporation Semiconductor device having a conductive layer reliably formed under an electrode pad
TWI460820B (en) * 2006-06-28 2014-11-11 Qualcomm Inc Integrated circuit (ic) chip and method for fabricating the same

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340265A (en) * 1998-05-22 1999-12-10 Sony Corp Semiconductor device and its manufacture
US7405149B1 (en) * 1998-12-21 2008-07-29 Megica Corporation Post passivation method for semiconductor chip or wafer
US6544880B1 (en) * 1999-06-14 2003-04-08 Micron Technology, Inc. Method of improving copper interconnects of semiconductor devices for bonding
US7494927B2 (en) 2000-05-15 2009-02-24 Asm International N.V. Method of growing electrical conductors
WO2002052646A1 (en) * 2000-12-22 2002-07-04 Koninklijke Philips Electronics N.V. Integrated circuit device
JP2003045877A (en) * 2001-08-01 2003-02-14 Sharp Corp Semiconductor device and its manufacturing method
US7049226B2 (en) * 2001-09-26 2006-05-23 Applied Materials, Inc. Integration of ALD tantalum nitride for copper metallization
US6916398B2 (en) * 2001-10-26 2005-07-12 Applied Materials, Inc. Gas delivery apparatus and method for atomic layer deposition
JP4340416B2 (en) * 2002-02-26 2009-10-07 Spansion Japan株式会社 The method of manufacturing a semiconductor memory device
JP2004214594A (en) * 2002-11-15 2004-07-29 Sharp Corp Semiconductor device and its manufacturing method
JP4170103B2 (en) * 2003-01-30 2008-10-22 Necエレクトロニクス株式会社 The method of manufacturing a semiconductor device, and semiconductor device
US6869878B1 (en) * 2003-02-14 2005-03-22 Advanced Micro Devices, Inc. Method of forming a selective barrier layer using a sacrificial layer
US7026714B2 (en) * 2003-03-18 2006-04-11 Cunningham James A Copper interconnect systems which use conductive, metal-based cap layers
US7238610B2 (en) * 2003-03-31 2007-07-03 Intel Corporation Method and apparatus for selective deposition
US7566964B2 (en) * 2003-04-10 2009-07-28 Agere Systems Inc. Aluminum pad power bus and signal routing for integrated circuit devices utilizing copper technology interconnect structures
DE10335182B4 (en) * 2003-07-30 2007-03-01 Infineon Technologies Ag Arrangement to improve module reliability
DE10337569B4 (en) * 2003-08-14 2008-12-11 Infineon Technologies Ag Integrated terminal assembly and manufacturing processes
US6977435B2 (en) * 2003-09-09 2005-12-20 Intel Corporation Thick metal layer integrated process flow to improve power delivery and mechanical buffering
US7294565B2 (en) * 2003-10-01 2007-11-13 International Business Machines Corporation Method of fabricating a wire bond pad with Ni/Au metallization
US7381642B2 (en) * 2004-09-23 2008-06-03 Megica Corporation Top layers of metal for integrated circuits
DE102004048202B4 (en) * 2004-09-30 2008-05-21 Infineon Technologies Ag Method for separating of surface mount semiconductor devices and for equipping them with external contacts
TWI313914B (en) 2005-01-31 2009-08-21 Sanyo Electric Co Semiconductor device and a method for manufacturing thereof
US8025922B2 (en) * 2005-03-15 2011-09-27 Asm International N.V. Enhanced deposition of noble metals
US7666773B2 (en) 2005-03-15 2010-02-23 Asm International N.V. Selective deposition of noble metal thin films
US20070014919A1 (en) * 2005-07-15 2007-01-18 Jani Hamalainen Atomic layer deposition of noble metal oxides
US7960838B2 (en) 2005-11-18 2011-06-14 United Microelectronics Corp. Interconnect structure
KR100735526B1 (en) * 2006-02-08 2007-06-28 삼성전자주식회사 Semiconductor device having improved wire bonding reliability, reticle used in fabricating method for the same and fabrication method thereof
US20080038913A1 (en) * 2006-08-10 2008-02-14 International Business Machines Corporation Methods of forming aluminum-free wire bond pad and pad so formed
US7435484B2 (en) * 2006-09-01 2008-10-14 Asm Japan K.K. Ruthenium thin film-formed structure
US7682959B2 (en) * 2007-03-21 2010-03-23 Stats Chippac, Ltd. Method of forming solder bump on high topography plated Cu
US7964934B1 (en) 2007-05-22 2011-06-21 National Semiconductor Corporation Fuse target and method of forming the fuse target in a copper process flow
US8030733B1 (en) 2007-05-22 2011-10-04 National Semiconductor Corporation Copper-compatible fuse target
US20090087339A1 (en) * 2007-09-28 2009-04-02 Asm Japan K.K. METHOD FOR FORMING RUTHENIUM COMPLEX FILM USING Beta-DIKETONE-COORDINATED RUTHENIUM PRECURSOR
KR101544198B1 (en) * 2007-10-17 2015-08-12 한국에이에스엠지니텍 주식회사 Ruthenium film forming method
US7829450B2 (en) * 2007-11-07 2010-11-09 Infineon Technologies Ag Method of processing a contact pad, method of manufacturing a contact pad, and integrated circuit element
KR20090067505A (en) * 2007-12-21 2009-06-25 에이에스엠지니텍코리아 주식회사 Method of depositing ruthenium film
US8084104B2 (en) * 2008-08-29 2011-12-27 Asm Japan K.K. Atomic composition controlled ruthenium alloy film formed by plasma-enhanced atomic layer deposition
US7709956B2 (en) * 2008-09-15 2010-05-04 National Semiconductor Corporation Copper-topped interconnect structure that has thin and thick copper traces and method of forming the copper-topped interconnect structure
US8133555B2 (en) 2008-10-14 2012-03-13 Asm Japan K.K. Method for forming metal film by ALD using beta-diketone metal complex
US9379011B2 (en) 2008-12-19 2016-06-28 Asm International N.V. Methods for depositing nickel films and for making nickel silicide and nickel germanide
US20100155949A1 (en) * 2008-12-24 2010-06-24 Texas Instruments Incorporated Low cost process flow for fabrication of metal capping layer over copper interconnects
US20110020546A1 (en) * 2009-05-15 2011-01-27 Asm International N.V. Low Temperature ALD of Noble Metals
US8329569B2 (en) * 2009-07-31 2012-12-11 Asm America, Inc. Deposition of ruthenium or ruthenium dioxide
US8003515B2 (en) * 2009-09-18 2011-08-23 Infineon Technologies Ag Device and manufacturing method
KR101652386B1 (en) * 2009-10-01 2016-09-12 삼성전자주식회사 Integrated circuit chip and method of manufacturing the same and flip chip package having the integrated chip and method of manufacturing the same
JP5342532B2 (en) 2010-10-05 2013-11-13 三菱重工業株式会社 Method of manufacturing a vehicle body frame
US8492892B2 (en) 2010-12-08 2013-07-23 International Business Machines Corporation Solder bump connections
US8871617B2 (en) 2011-04-22 2014-10-28 Asm Ip Holding B.V. Deposition and reduction of mixed metal oxide thin films
US8716858B2 (en) * 2011-06-24 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure with barrier layer on post-passivation interconnect
US8946000B2 (en) 2013-02-22 2015-02-03 Freescale Semiconductor, Inc. Method for forming an integrated circuit having a programmable fuse
US10121752B2 (en) * 2015-02-25 2018-11-06 Intel Corporation Surface finishes for interconnection pads in microelectronic structures
US9607842B1 (en) 2015-10-02 2017-03-28 Asm Ip Holding B.V. Methods of forming metal silicides
US10204859B2 (en) * 2017-01-25 2019-02-12 Macronix International Co., Ltd. Interconnect structure and fabricating method thereof

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63293951A (en) * 1987-05-27 1988-11-30 Hitachi Ltd Semiconductor element electrode structure
US5220199A (en) * 1988-09-13 1993-06-15 Hitachi, Ltd. Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wiring substrate
JP3290459B2 (en) * 1991-06-27 2002-06-10 株式会社日立製作所 The semiconductor integrated circuit device and manufacturing method thereof
US5470787A (en) * 1994-05-02 1995-11-28 Motorola, Inc. Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same
US5656858A (en) 1994-10-19 1997-08-12 Nippondenso Co., Ltd. Semiconductor device with bump structure
JP2985692B2 (en) * 1994-11-16 1999-12-06 日本電気株式会社 Wiring structure and a method of manufacturing a semiconductor device
JPH08191104A (en) * 1995-01-11 1996-07-23 Hitachi Ltd Semiconductor integrated circuit device and manufacturing method thereof
EP1441388A3 (en) * 1995-03-20 2004-09-22 Unitive International Limited Solder bump fabrication methods and structure including a titanium barrier layer
US5731624A (en) 1996-06-28 1998-03-24 International Business Machines Corporation Integrated pad and fuse structure for planar copper metallurgy
JP3660799B2 (en) * 1997-09-08 2005-06-15 株式会社ルネサステクノロジ The method of manufacturing a semiconductor integrated circuit device
JP3697044B2 (en) * 1997-12-19 2005-09-21 株式会社ルネサステクノロジ The semiconductor integrated circuit device and manufacturing method thereof
JPH11340265A (en) * 1998-05-22 1999-12-10 Sony Corp Semiconductor device and its manufacture
US6187680B1 (en) 1998-10-07 2001-02-13 International Business Machines Corporation Method/structure for creating aluminum wirebound pad on copper BEOL

Cited By (150)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6577011B1 (en) * 1997-07-10 2003-06-10 International Business Machines Corporation Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
US20040038507A1 (en) * 1998-09-23 2004-02-26 Infineon Technologies Ag Method of producing an integrated circuit configuration
US6998338B2 (en) 1998-09-23 2006-02-14 Infineon Technologies Ag Method of producing an integrated circuit configuration
US20010026952A1 (en) * 1998-09-23 2001-10-04 Manfred Engelhardt Integrated circuit configuration and production method
US6828680B2 (en) * 1998-09-23 2004-12-07 Infineon Technologies Ag Integrated circuit configuration using spacers as a diffusion barrier and method of producing such an integrated circuit configuration
US8471384B2 (en) 1998-12-21 2013-06-25 Megica Corporation Top layers of metal for high performance IC's
US20030222295A1 (en) * 1998-12-21 2003-12-04 Megic Corporation High performance system-on-chip inductor using post passivation process
US7884479B2 (en) 1998-12-21 2011-02-08 Megica Corporation Top layers of metal for high performance IC's
US20070262457A1 (en) * 1998-12-21 2007-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US20070284752A1 (en) * 1998-12-21 2007-12-13 Mou-Shiung Lin Top layers of metal for high performance IC's
US7863654B2 (en) 1998-12-21 2011-01-04 Megica Corporation Top layers of metal for high performance IC's
US20070288880A1 (en) * 1998-12-21 2007-12-13 Mou-Shiung Lin Top layers of metal for high performance IC's
US20070290358A1 (en) * 1998-12-21 2007-12-20 Mou-Shiung Lin Top layers of metal for high performance IC's
US20080035974A1 (en) * 1998-12-21 2008-02-14 Megica Corporation High performance system-on-chip using post passivation process
US20090184394A1 (en) * 1998-12-21 2009-07-23 Megica Corporation High performance system-on-chip inductor using post passivation process
US8531038B2 (en) 1998-12-21 2013-09-10 Megica Corporation Top layers of metal for high performance IC's
US20080042238A1 (en) * 1998-12-21 2008-02-21 Megica Corporation High performance system-on-chip using post passivation process
US20070262456A1 (en) * 1998-12-21 2007-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US20070273033A1 (en) * 1998-12-21 2007-11-29 Mou-Shiung Lin Top layers of metal for high performance IC's
US20070278691A1 (en) * 1998-12-21 2007-12-06 Mou-Shiung Lin Top layers of metal for high performance IC's
US8022545B2 (en) 1998-12-21 2011-09-20 Megica Corporation Top layers of metal for high performance IC's
US20080042289A1 (en) * 1998-12-21 2008-02-21 Megica Corporation High performance system-on-chip using post passivation process
US20090045516A1 (en) * 1998-12-21 2009-02-19 Megica Corporation TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC's
US20050184358A1 (en) * 1998-12-21 2005-08-25 Megic Corporation High performance system-on-chip using post passivation process
US7459761B2 (en) * 1998-12-21 2008-12-02 Megica Corporation High performance system-on-chip using post passivation process
US7999384B2 (en) 1998-12-21 2011-08-16 Megica Corporation Top layers of metal for high performance IC's
US20080093745A1 (en) * 1998-12-21 2008-04-24 Megica Corporation High performance system-on-chip using post passivation process
US8487400B2 (en) 1998-12-21 2013-07-16 Megica Corporation High performance system-on-chip using post passivation process
US8178435B2 (en) * 1998-12-21 2012-05-15 Megica Corporation High performance system-on-chip inductor using post passivation process
US8415800B2 (en) 1998-12-21 2013-04-09 Megica Corporation Top layers of metal for high performance IC's
US20070281458A1 (en) * 1998-12-21 2007-12-06 Mou-Shiung Lin Top layers of metal for high performance IC's
US20070278686A1 (en) * 1998-12-21 2007-12-06 Mou-Shiung Lin Top layers of metal for high performance IC's
US6900545B1 (en) * 1999-06-25 2005-05-31 International Business Machines Corporation Variable thickness pads on a substrate surface
US20020142576A1 (en) * 1999-08-10 2002-10-03 Hitachi, Ltd. Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device
US20080138979A1 (en) * 1999-08-10 2008-06-12 Junji Noguchi Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device
US7205221B2 (en) * 1999-09-02 2007-04-17 Micron Technology, Inc. Under bump metallization pad and solder bump connections
US20040238955A1 (en) * 1999-09-22 2004-12-02 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US6798050B1 (en) * 1999-09-22 2004-09-28 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor element with copper pad mounted on wiring substrate and method for fabricating the same
US20020015128A1 (en) * 2000-06-21 2002-02-07 Hirokazu Sakaguchi LCD driver IC chip
US20050279809A1 (en) * 2000-11-10 2005-12-22 Rinne Glenn A Optical structures including liquid bumps and related methods
US20070152020A1 (en) * 2000-11-10 2007-07-05 Unitive International Limited Optical structures including liquid bumps
US7008868B2 (en) * 2000-12-04 2006-03-07 Fairchild Semiconductor Corporation Passivation scheme for bumped wafers
US20020066959A1 (en) * 2000-12-04 2002-06-06 Rajeev Joshi Passivation scheme for bumped wafers
US20040241977A1 (en) * 2000-12-04 2004-12-02 Fairchild Semiconductor Corporation Passivation scheme for bumped wafers
US6753605B2 (en) * 2000-12-04 2004-06-22 Fairchild Semiconductor Corporation Passivation scheme for bumped wafers
US20050023590A1 (en) * 2000-12-28 2005-02-03 Jingyu Lian Multi-layer electrode and method of forming the same
US7319270B2 (en) * 2000-12-28 2008-01-15 Infineon Technologies Ag Multi-layer electrode and method of forming the same
US20110175195A1 (en) * 2001-09-04 2011-07-21 Megica Corporation Method for making high-performance rf integrated circuits
US8384508B2 (en) 2001-09-04 2013-02-26 Megica Corporation Method for making high-performance RF integrated circuits
US7973629B2 (en) 2001-09-04 2011-07-05 Megica Corporation Method for making high-performance RF integrated circuits
US7665652B2 (en) 2001-09-27 2010-02-23 Unitive International Limited Electronic devices including metallurgy structures for wire and solder bonding
US20040206801A1 (en) * 2001-09-27 2004-10-21 Mis J. Daniel Electronic devices including metallurgy structures for wire and solder bonding
US20060076679A1 (en) * 2002-06-25 2006-04-13 Batchelor William E Non-circular via holes for bumping pads and related structures
US7839000B2 (en) 2002-06-25 2010-11-23 Unitive International Limited Solder structures including barrier layers with nickel and/or copper
US20040053483A1 (en) * 2002-06-25 2004-03-18 Nair Krishna K. Methods of forming electronic structures including conductive shunt layers and related structures
US20110084392A1 (en) * 2002-06-25 2011-04-14 Nair Krishna K Electronic Structures Including Conductive Layers Comprising Copper and Having a Thickness of at Least 0.5 Micrometers
US20090212427A1 (en) * 2002-06-25 2009-08-27 Unitive International Limited Solder Structures Including Barrier Layers with Nickel and/or Copper
US7879715B2 (en) 2002-06-25 2011-02-01 Unitive International Limited Methods of forming electronic structures including conductive shunt layers and related structures
US8294269B2 (en) 2002-06-25 2012-10-23 Unitive International Electronic structures including conductive layers comprising copper and having a thickness of at least 0.5 micrometers
US20060009023A1 (en) * 2002-06-25 2006-01-12 Unitive International Limited Methods of forming electronic structures including conductive shunt layers and related structures
US20060030139A1 (en) * 2002-06-25 2006-02-09 Mis J D Methods of forming lead free solder bumps and related structures
US8829681B2 (en) 2002-07-31 2014-09-09 Fujitsu Semiconductor Limited Semiconductor device having groove-shaped via-hole
US9105640B2 (en) 2002-07-31 2015-08-11 Fujitsu Semiconductor Limited Semiconductor device including two groove-shaped patterns
US9224689B2 (en) 2002-07-31 2015-12-29 Socionext Inc. Semiconductor device having groove-shaped via-hole
US9082771B2 (en) 2002-07-31 2015-07-14 Fujitsu Semiconductor Limited Semiconductor device including two groove-shaped patterns that include two bent portions
US8872353B2 (en) 2002-07-31 2014-10-28 Fujitsu Semiconductor Limited Semiconductor device having groove-shaped via-hole
US9224690B2 (en) 2002-07-31 2015-12-29 Socionext Inc. Semiconductor device having groove-shaped via-hole
US8410613B2 (en) * 2002-07-31 2013-04-02 Fujitsu Semiconductor Limited Semiconductor device having groove-shaped pattern
US8872352B2 (en) 2002-07-31 2014-10-28 Fujitsu Semiconductor Limited Semiconductor device having groove-shaped via-hole
US9406611B2 (en) 2002-07-31 2016-08-02 Socionext Inc. Semiconductor device having groove-shaped via-hole
US7446418B2 (en) * 2002-07-31 2008-11-04 Fujitsu Limited Semiconductor device for preventing defective filling of interconnection and cracking of insulating film
US8872347B2 (en) 2002-07-31 2014-10-28 Fujitsu Semiconductor Limited Semiconductor device having groove-shaped via-hole
US20050218527A1 (en) * 2002-07-31 2005-10-06 Fujitsu Limited Semiconductor device for preventing defective filling of interconnection and cracking of insulating film
US9406613B2 (en) 2002-07-31 2016-08-02 Socionext Inc. Semiconductor device having groove-shaped via-hole
US8633595B2 (en) 2002-07-31 2014-01-21 Fujitsu Semiconductor Limited Semiconductor device having groove-shaped via-hole
US9406610B2 (en) 2002-07-31 2016-08-02 Socionext Inc. Semiconductor device having groove-shaped via-hole
US9406612B2 (en) 2002-07-31 2016-08-02 Socionext Inc. Semiconductor device having groove-shaped via-hole
US9412698B2 (en) 2002-07-31 2016-08-09 Socionext Inc. Semiconductor device having groove-shaped via-hole
US9412697B2 (en) 2002-07-31 2016-08-09 Socionext Inc. Semiconductor device having groove-shaped via-hole
US8633594B2 (en) 2002-07-31 2014-01-21 Fujitsu Semiconductor Limited Semiconductor device having groove-shaped via-hole
US9412696B2 (en) 2002-07-31 2016-08-09 Socionext Inc. Semiconductor device having groove-shaped via-hole
US9412699B2 (en) 2002-07-31 2016-08-09 Socionext Inc. Semiconductor device having groove-shaped via-hole
US9502353B2 (en) 2002-07-31 2016-11-22 Socionext Inc. Semiconductor device having groove-shaped via-hole
US20110115091A1 (en) * 2002-07-31 2011-05-19 Fujitsu Semiconductor Limited Semiconductor device having groove-shaped via-hole
US8791576B2 (en) 2002-07-31 2014-07-29 Fujitsu Semiconductor Limited Semiconductor device having groove-shaped via-hole
US8853861B2 (en) 2002-07-31 2014-10-07 Fujitsu Semiconductor Limited Semiconductor device having groove-shaped via-hole
US8847403B2 (en) 2002-07-31 2014-09-30 Fujitsu Semiconductor Limited Semiconductor device including two groove-shaped patterns
US8841775B2 (en) 2002-07-31 2014-09-23 Fujitsu Semiconductor Limited Semiconductor device having groove-shaped via-hole
US9972531B2 (en) 2002-07-31 2018-05-15 Socionext Inc. Method of manufacturing a semiconductor device having groove-shaped via-hole
US7755196B2 (en) * 2003-01-15 2010-07-13 Infineon Technologies Ag Method for production of an integrated circuit bar arrangement, in particular comprising a capacitor assembly, as well as an integrated circuit arrangement
US20080006905A1 (en) * 2003-01-15 2008-01-10 Infineon Technologies Ag Method for production of an integrated circuit bar arrangement, in particular comprising a capacitor assembly, as well as an integrated circuit arrangement
US20040209406A1 (en) * 2003-02-18 2004-10-21 Jong-Rong Jan Methods of selectively bumping integrated circuit substrates and related structures
US20060231951A1 (en) * 2003-02-18 2006-10-19 Jong-Rong Jan Electronic devices including offset conductive bumps
US20040188851A1 (en) * 2003-03-26 2004-09-30 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US7312535B2 (en) * 2003-03-26 2007-12-25 Nec Electronics Corporation Semiconductor device having an anti-oxidizing layer that inhibits corrosion of an interconnect layer
US6893959B2 (en) 2003-05-05 2005-05-17 Infineon Technologies Ag Method to form selective cap layers on metal features with narrow spaces
US20040224497A1 (en) * 2003-05-05 2004-11-11 Hans-Joachim Barth Method to form selective cap layers on metal features with narrow spaces
WO2004100257A1 (en) * 2003-05-05 2004-11-18 Infineon Technologies Ag Method to form selective cap layers on metal features with narrow spaces
US20070190776A1 (en) * 2003-09-09 2007-08-16 Intel Corporation Methods of Processing Thick ILD Layers Using Spray Coating or Lamination for C4 Wafer Level Thick Metal Integrated Flow
US20050083592A1 (en) * 2003-09-10 2005-04-21 Yaakov Amitai High Brightness optical device
US7279720B2 (en) * 2003-10-21 2007-10-09 Intel Corporation Large bumps for optical flip chips
US20050082552A1 (en) * 2003-10-21 2005-04-21 Ming Fang Large bumps for optical flip chips
US20050206067A1 (en) * 2004-03-18 2005-09-22 Cook William P Input tray and drive mechanism using a single motor for an image forming device
US20050269697A1 (en) * 2004-06-04 2005-12-08 Seiko Epson Corporation Semiconductor device, circuit board, and electronic instrument
US7560814B2 (en) 2004-06-04 2009-07-14 Seiko Epson Corporation Semiconductor device that improves electrical connection reliability
US20070228560A1 (en) * 2004-06-04 2007-10-04 Seiko Epson Corporation Semiconductor device that improves electrical connection reliability
US7230338B2 (en) * 2004-06-04 2007-06-12 Seiko Epson Corporation Semiconductor device that improves electrical connection reliability
US8552559B2 (en) 2004-07-29 2013-10-08 Megica Corporation Very thick metal interconnection scheme in IC chips
US20060022343A1 (en) * 2004-07-29 2006-02-02 Megic Corporation Very thick metal interconnection scheme in IC chips
US8018060B2 (en) 2004-09-09 2011-09-13 Megica Corporation Post passivation interconnection process and structures
US8008775B2 (en) 2004-09-09 2011-08-30 Megica Corporation Post passivation interconnection structures
US20060205170A1 (en) * 2005-03-09 2006-09-14 Rinne Glenn A Methods of forming self-healing metal-insulator-metal (MIM) structures and related devices
US20060205204A1 (en) * 2005-03-14 2006-09-14 Michael Beck Method of making a semiconductor interconnect with a metal cap
US8384189B2 (en) 2005-03-29 2013-02-26 Megica Corporation High performance system-on-chip using post passivation process
US20080284032A1 (en) * 2005-03-29 2008-11-20 Megica Corporation High performance system-on-chip using post passivation process
US7598569B2 (en) * 2005-06-23 2009-10-06 Seiko Epson Corporation Semiconductor device
US20060289961A1 (en) * 2005-06-23 2006-12-28 Seiko Epson Corporation Semiconductor device
US8878365B2 (en) 2005-07-13 2014-11-04 Seiko Epson Corporation Semiconductor device having a conductive layer reliably formed under an electrode pad
US20070045855A1 (en) * 2005-07-22 2007-03-01 Megica Corporation Method for forming a double embossing structure
US20110215469A1 (en) * 2005-07-22 2011-09-08 Megica Corporation Method for forming a double embossing structure
US7960269B2 (en) 2005-07-22 2011-06-14 Megica Corporation Method for forming a double embossing structure
US7932615B2 (en) 2006-02-08 2011-04-26 Amkor Technology, Inc. Electronic devices including solder bumps on compliant dielectric layers
US20070182004A1 (en) * 2006-02-08 2007-08-09 Rinne Glenn A Methods of Forming Electronic Interconnections Including Compliant Dielectric Layers and Related Devices
US7674701B2 (en) 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
US8592977B2 (en) * 2006-06-28 2013-11-26 Megit Acquisition Corp. Integrated circuit (IC) chip and method for fabricating the same
US20080001290A1 (en) * 2006-06-28 2008-01-03 Megica Corporation Integrated circuit (IC) chip and method for fabricating the same
US8421227B2 (en) * 2006-06-28 2013-04-16 Megica Corporation Semiconductor chip structure
US20080042280A1 (en) * 2006-06-28 2008-02-21 Megica Corporation Semiconductor chip structure
TWI460820B (en) * 2006-06-28 2014-11-11 Qualcomm Inc Integrated circuit (ic) chip and method for fabricating the same
WO2008054680A3 (en) * 2006-10-31 2008-06-26 Advanced Micro Devices Inc A metallization layer stack without a terminal aluminum metal layer
US20080102540A1 (en) * 2006-10-31 2008-05-01 Tobias Letz Technique for forming a passivation layer without a terminal metal
WO2008054680A2 (en) * 2006-10-31 2008-05-08 Advanced Micro Devices, Inc. A metallization layer stack without a terminal aluminum metal layer
DE102006051490A1 (en) * 2006-10-31 2008-05-08 Advanced Micro Devices, Inc., Sunnyvale Technique for producing a passivation layer without a final metal
GB2456120A (en) * 2006-10-31 2009-07-08 Advanced Micro Devices Inc A metallization layer stack without a terminal aluminium metal layer
DE102006051490B4 (en) * 2006-10-31 2010-07-08 Advanced Micro Devices, Inc., Sunnyvale Technique for producing a passivation layer without a final metal
US20080099913A1 (en) * 2006-10-31 2008-05-01 Matthias Lehr Metallization layer stack without a terminal aluminum metal layer
US8841140B2 (en) 2006-10-31 2014-09-23 Advanced Micro Devices, Inc. Technique for forming a passivation layer without a terminal metal
US20080284014A1 (en) * 2007-03-13 2008-11-20 Megica Corporation Chip assembly
US8193636B2 (en) 2007-03-13 2012-06-05 Megica Corporation Chip assembly with interconnection by metal bump
US9252331B2 (en) * 2007-09-28 2016-02-02 Osram Opto Semiconductors Gmbh Thin-film LED having a mirror layer and method for the production thereof
US20100283073A1 (en) * 2007-09-28 2010-11-11 Osram Opto Semiconductors Gmbh Thin-Film LED Having a Mirror Layer and Method for the Production Thereof
DE102007057689A1 (en) * 2007-11-30 2009-06-04 Advanced Micro Devices, Inc., Sunnyvale A semiconductor device having a chip area which is designed for an aluminum-free Lothöckerverbindung, and a test structure that is designed for an aluminum-free wire connection
US8283247B2 (en) 2007-11-30 2012-10-09 Advanced Micro Devices, Inc. Semiconductor device including a die region designed for aluminum-free solder bump connection and a test structure designed for aluminum-free wire bonding
US20130029483A1 (en) * 2008-07-15 2013-01-31 Semiconductor Manufacturing International (Shanghai) Corporation Method and system for forming conductive bumping with copper interconnection
US8581366B2 (en) * 2008-07-15 2013-11-12 Semiconductor Manufacturing International (Shanghai) Corporation Method and system for forming conductive bumping with copper interconnection
US8536703B2 (en) * 2010-03-23 2013-09-17 Samsung Electronics Co., Ltd. Semiconductor devices and electronic systems
US20110233796A1 (en) * 2010-03-23 2011-09-29 Kim Deok-Kee Semiconductor Devices and Electronic Systems
DE102011005642B4 (en) * 2011-03-16 2012-09-27 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG A method for protecting reactive metal surfaces of semiconductor devices during transport by providing an additional protective layer
DE102011005642A1 (en) * 2011-03-16 2012-09-20 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG A method for protecting reactive metal surfaces of semiconductor devices during transport by providing an additional protective layer
US8828888B2 (en) 2011-03-16 2014-09-09 Globalfoundries Inc. Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer

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