JP2012507163A - 金属ピラーのための低減された応力構造を含む半導体デバイス - Google Patents
金属ピラーのための低減された応力構造を含む半導体デバイス Download PDFInfo
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- JP2012507163A JP2012507163A JP2011533584A JP2011533584A JP2012507163A JP 2012507163 A JP2012507163 A JP 2012507163A JP 2011533584 A JP2011533584 A JP 2011533584A JP 2011533584 A JP2011533584 A JP 2011533584A JP 2012507163 A JP2012507163 A JP 2012507163A
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- passivation layer
- final passivation
- stress distribution
- semiconductor device
- forming
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Abstract
洗練された半導体デバイスのメタライゼーションシステムにおいて、そこに与えられる任意の機械的な応力を分配する場合の効率の増大を提示するように、金属ピラー271が設けられてよい。このことは、例えばピラー271及び最終不動態化層260に接触する追加的な応力分配要素272を設けることによって、金属ピラーとの強固な機械的接触状態にある最終不動態化層260の表面積を顕著に増大させることにより達成され得る。
【選択図】図2d
Description
Claims (20)
- 基板の上方に形成され、複数のメタライゼーション層とコンタクトパッドを含む最終コンタクト層とを備えているメタライゼーションシステムと、
前記最終コンタクト層の上方に形成され、前記コンタクトパッドに対して位置合わせされる開口を備えている最終不動態化層と、
前記最終不動態化層から延びて前記コンタクトパッドと接触する金属ピラーと、
前記最終不動態化層と接触して形成され、前記金属ピラーから前記最終不動態化層への応力転移のための実効面積を増加させるように前記金属ピラーの一部分と接触する応力分配要素とを備えた半導体デバイス。 - 前記応力分配要素は前記金属ピラーの前記一部分の周囲を取り囲むように前記最終不動態化層上に形成されている請求項1の半導体デバイス。
- 前記応力分配要素は金属からなる請求項1の半導体デバイス。
- 前記応力分配要素は前記最終不動態化層内に形成されている請求項1の半導体デバイス。
- 前記応力分配要素は前記最終不動態化層の第1のサブ層上に形成され且つ前記最終不動態化層の第2のサブ層の材質によって覆われている請求項4の半導体デバイス。
- 前記最終不動態化層は前記コンタクトパッド上に形成される第1のサブ層と前記第1のサブ層上に形成される第2のサブ層とを備えており、前記応力分配要素は前記第2のサブ層内に埋め込まれている請求項4の半導体デバイス。
- 前記金属ピラーは銅からなる請求項1の半導体デバイス。
- 前記金属ピラーの幅は概ね30μm乃至100μmである請求項1の半導体デバイス。
- 前記応力分配要素は概ね50μm乃至200μmの範囲内の幅を有している請求項1の半導体デバイス。
- 前記応力分配要素は銅からなる請求項8の半導体デバイス。
- 半導体デバイスのメタライゼーションシステムであってコンタクトパッドを備えているメタライゼーションシステムの上方に最終不動態化層を形成することと、
前記最終不動態化層内に前記コンタクトパッドに対して位置合わせされる開口を形成することと、
前記最終不動態化層と接触する応力分配領域を前記応力分配領域の横方向のサイズを規定するマスクに基き形成することと、
前記最終不動態化層の上方に堆積マスクを形成することと、
前記堆積マスクを用いて前記応力分配領域から延びる金属ピラーを形成することとを備えた方法。 - 前記応力分配領域を形成することは、前記開口を中心として前記最終不動態化層の少なくともサブ層の一部分を露出させるように前記マスクを形成することと、金属を堆積させることとを備えている請求項11の方法。
- 前記マスクを除去することと、前記最終不動態化層の前記少なくともサブ層の上方に誘電体材質を形成することとを更に備えた請求項12の方法。
- 前記誘電体材質及び前記少なくともサブ層は同一の材質からなる請求項13の方法。
- 前記応力分配領域を形成することは前記最終不動態化層の第1のサブ層を形成することを備えており、前記マスクは前記第1のサブ層上に形成され、前記方法は前記応力分配領域の前記金属を堆積させた後に第2のサブ層を形成することを更に備えている請求項11の方法。
- 前記開口を形成することは前記第2のサブ層を通ってエッチングすることを備えている請求項15の方法。
- 前記応力分配領域は誘電体材質から形成される請求項11の方法。
- 半導体デバイスを形成する方法であって、
複数のメタライゼーション層の上方に最終不動態化層を形成することと、
コンタクトパッドの一部分を露出させるように前記最終不動態化層内に開口を形成することと、
前記最終不動態化層から延び且つ前記コンタクトパッドに接続する金属ピラーを形成することと、
概ね0.5以上であるべき前記最終不動態化層の厚みと前記金属ピラーの直径の比、及び概ね1.5以上であるべき前記金属ピラーの直径と前記開口の直径の比の少なくとも一方を制御することとを備えた方法。 - 前記最終不動態化層の厚みと前記金属ピラーの直径の比は概ね1.0以上であるように制御される請求項18の方法。
- 前記金属ピラーの直径と前記開口の直径の比は概ね2.0以上であるように制御される請求項18の方法。
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DE102008054054A DE102008054054A1 (de) | 2008-10-31 | 2008-10-31 | Halbleiterbauelement mit einem Aufbau für reduzierte Verspannung von Metallsäulen |
DE102008054054.4 | 2008-10-31 | ||
US12/575,618 US8039958B2 (en) | 2008-10-31 | 2009-10-08 | Semiconductor device including a reduced stress configuration for metal pillars |
US12/575,618 | 2009-10-08 | ||
PCT/EP2009/007549 WO2010049087A2 (en) | 2008-10-31 | 2009-10-21 | A semiconductor device including a reduced stress configuration for metal pillars |
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US8431492B2 (en) | 2010-02-02 | 2013-04-30 | Sandisk 3D Llc | Memory cell that includes a sidewall collar for pillar isolation and methods of forming the same |
US9312230B2 (en) * | 2010-02-08 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive pillar structure for semiconductor substrate and method of manufacture |
CN102064135B (zh) * | 2010-10-21 | 2015-07-22 | 日月光半导体制造股份有限公司 | 具有金属柱的芯片及具有金属柱的芯片的封装结构 |
US9159638B2 (en) * | 2011-05-26 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive via structure |
FR2978296A1 (fr) * | 2011-07-20 | 2013-01-25 | St Microelectronics Crolles 2 | Puce electronique comportant des piliers de connexion, et procede de fabrication |
US8922006B2 (en) * | 2012-03-29 | 2014-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Elongated bumps in integrated circuit devices |
CN104124213B (zh) * | 2013-04-28 | 2017-10-10 | 无锡华润安盛科技有限公司 | 一种平衡dbc板上应力的方法及dbc板封装结构 |
US9136234B2 (en) | 2013-07-09 | 2015-09-15 | Globalfoundries Inc. | Semiconductor device with improved metal pillar configuration |
KR102574452B1 (ko) | 2018-07-03 | 2023-09-04 | 삼성전자 주식회사 | 반도체 칩 및 이를 포함하는 반도체 패키지 |
US20210125948A1 (en) * | 2019-10-28 | 2021-04-29 | Nanya Technology Corporation | Semiconductor device and method for fabricating the same |
US11322458B2 (en) * | 2020-04-27 | 2022-05-03 | Nanya Technology Corporation | Semiconductor structure including a first substrate and a second substrate and a buffer structure in the second substrate |
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