JP2012501077A - チップ・パッケージ相互作用安定性を高めるための応力緩和ギャップを含む半導体デバイス。 - Google Patents
チップ・パッケージ相互作用安定性を高めるための応力緩和ギャップを含む半導体デバイス。 Download PDFInfo
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Abstract
単一チップ区域を個々のサブ区域(1つ以上の応力緩和領域280a、280bに基く200a、200b、200c)に分割することによって、サブ区域の各々内に熱的に誘起される応力は、複雑な集積回路の動作の間に低減することができ、それにより低k誘電体材質又はULK材質を備えた複雑なメタライゼーションシステムの全体的な信頼性を高めることができる。その結果、従来の戦略と比較して、多数の積層メタライゼーション層を半導体チップ(200)の大きな横方向寸法との組み合わせにおいて用いることができる。
【選択図】図2c
Description
Claims (25)
- 半導体材質の内部及び上方に形成される複数の回路要素と、
前記複数の回路要素の上方に形成されるメタライゼーションシステムと、
応力緩和領域とを備えた半導体デバイスであって、
前記メタライゼーションシステムは1つ以上のメタライゼーション層とパッケージ基板に接続される最後のコンタクト層とを備えており、
前記応力緩和領域は、少なくとも前記メタライゼーションシステム内に設けられ、前記メタライゼーションシステムを少なくとも第1の部分及び第2の部分に分割し、前記第1の部分及び前記第2の部分を電気的に接続するように前記1つ以上のメタライゼーション層の少なくとも1つの内部に金属線部分を備えている半導体デバイス。 - 前記応力緩和領域は前記基板内にまで延在している、請求項1の半導体デバイス。
- 前記応力緩和領域は前記基板を通過して延在している、請求項2の半導体デバイス。
- 前記応力緩和領域は前記半導体材質の熱膨張係数とは異なる熱膨張係数を有する充填材質を備えている、請求項1の半導体デバイス。
- 前記充填材質は前記前記パッケージ基板の熱膨張係数と実質的に等しい熱膨張係数を有している、請求項1の半導体デバイス。
- 前記応力緩和領域は少なくとも前記メタライゼーションシステムを3以上の部分に分割しており、
前記3以上の部分の少なくとも幾つかは前記1つ以上のメタライゼーション層の1つ以上の金属線によって電気的に接続されている、請求項1の半導体デバイス。 - 前記最後のコンタクト層にバンプ構造によって接続される前記パッケージ基板を更に備えた、請求項1の半導体デバイス。
- 前記1つ以上のメタライゼーション層の少なくとも1つは概ね3.0以下の誘電定数を有する誘電体材質を備えている、請求項1の半導体デバイス。
- 前記応力緩和領域は概ね1μm〜50μmの範囲にある幅を有している、請求項1の半導体デバイス。
- 前記金属線部分は非直線的な線部分を代表している、請求項1の半導体デバイス。
- 前記回路要素の少なくとも幾つかは概ね50nm以下の臨界的寸法を有している、請求項1の半導体デバイス。
- 半導体材質の内部及び上方に形成される複数のトランジスタ要素と、
少なくともその1つが低k誘電体材質内に形成される金属線を備えている複数の積層メタライゼーション層と、
前記複数の積層メタライゼーション層の各々を通過して前記半導体材質内にまで延在する膨張ギャップとを備えた半導体デバイス。 - 前記メタライゼーション層の少なくとも幾つかの内部の前記膨張ギャップを越えて延在する金属線部分を更に備えた、請求項12の半導体デバイス。
- 前記金属線部分は前記膨張ギャプの幅における変動に適合するように非直線的である、請求項13の半導体デバイス。
- 前記膨張ギャップは前記基板の熱膨張係数とは異なる熱膨張係数を有する充填材質を備えている、請求項12の半導体デバイス。
- 前記充填材質は有機材質である、請求項15の半導体デバイス。
- 前記膨張ギャップは前記基板を通過して延在している、請求項12の半導体デバイス。
- 前記複数のトランジスタ要素の少なくとも幾つかの最小臨界的設計寸法は概ね50ナノメートル以下である、請求項12の半導体デバイス。
- 半導体デバイスを形成する方法であって、
複数のトランジスタ要素を備えている半導体層の上方に1つ以上のメタライゼーション層を形成することと、
前記1つ以上のメタライゼーション層の少なくとも1つを通過するように延在する少なくとも1つの溝を形成することとを備え、
前記溝は前記1つ以上のメタライゼーション層の前記少なくとも1つを第1の部分及び第2の部分に分割している方法。 - 前記1つ以上のメタライゼーション層を形成することは前記1つ以上のメタライゼーション層の前記少なくとも1つの内部に非直線的な金属線部分を設けることを備えており、
前記非直線的な金属線部分は前記溝を越えて延在している、請求項19の方法。 - 前記基板の熱膨張係数とは異なる熱膨張係数を有する充填材質で前記溝を充填することを更に備えた、請求項20の方法。
- 前記溝は前記1つ以上のメタライゼーション層の各々を通過して延在するように形成される、請求項20の方法。
- 前記溝は前記1つ以上のメタライゼーション層の最後の1つを形成した後に形成される、請求項22の方法。
- 前記溝は前記半導体層がその上に形成される基板内にまで延在するように形成される、請求項22の方法。
- 前記複数のトランジスタ要素における第1の機能群及び第2の機能群を識別することを更に備え、
前記第1の機能群は前記第1の部分によって電気的に接続され、前記第2の機能群は前記第2の部分によって電気的に接続される、請求項22の方法。
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Application Number | Priority Date | Filing Date | Title |
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DE102008044984A DE102008044984A1 (de) | 2008-08-29 | 2008-08-29 | Halbleiterbauelement mit Verspannungsrelaxationsspalte zur Verbesserung der Chipgehäusewechselwirkungsstabilität |
DE102008044984.9 | 2008-08-29 | ||
US12/507,348 | 2009-07-22 | ||
US12/507,348 US7982313B2 (en) | 2008-08-29 | 2009-07-22 | Semiconductor device including stress relaxation gaps for enhancing chip package interaction stability |
PCT/EP2009/006258 WO2010022970A1 (en) | 2008-08-29 | 2009-08-28 | A semiconductor device including stress relaxation gaps for enhancing chip package interaction stability |
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US (1) | US7982313B2 (ja) |
JP (1) | JP2012501077A (ja) |
KR (1) | KR101542887B1 (ja) |
CN (1) | CN102132406B (ja) |
DE (1) | DE102008044984A1 (ja) |
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US7982313B2 (en) | 2011-07-19 |
KR20110057196A (ko) | 2011-05-31 |
US20100052147A1 (en) | 2010-03-04 |
DE102008044984A1 (de) | 2010-07-15 |
CN102132406A (zh) | 2011-07-20 |
KR101542887B1 (ko) | 2015-08-07 |
CN102132406B (zh) | 2015-01-07 |
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