CN102239555A - 包含降低金属柱应力之组构的半导体器件 - Google Patents

包含降低金属柱应力之组构的半导体器件 Download PDF

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Publication number
CN102239555A
CN102239555A CN2009801437874A CN200980143787A CN102239555A CN 102239555 A CN102239555 A CN 102239555A CN 2009801437874 A CN2009801437874 A CN 2009801437874A CN 200980143787 A CN200980143787 A CN 200980143787A CN 102239555 A CN102239555 A CN 102239555A
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Prior art keywords
passivation layer
final passivation
metal
stress distribution
semiconductor device
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CN2009801437874A
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A·普拉茨
F·库亨麦斯特
M·莱尔
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority claimed from PCT/EP2009/007549 external-priority patent/WO2010049087A2/en
Publication of CN102239555A publication Critical patent/CN102239555A/zh
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Abstract

在精密的半导体器件的金属化系统中，可设置金属柱271，以便增进分散施加在其上的任何机械性应力的效率。此目的可通过显着地增加最终钝化层260与金属柱紧密机械性接触的表面积，例如通过设置与金属柱271和最终钝化层260接触的额外应力分布元件272而达成。

Description

包含降低金属柱应力之组构的半导体器件
技术领域
一般而言，本发明系关于积体电路，更详而言之，系关于用于降低通过该晶片与该封装件之间的热不匹配所造成的晶片-封装件交互作用之技术。
背景技术
典型上，半导体器件系形成在实质上通过任何适当材料所制成且为圆盘状的基板上。在目前及可预见的未来，包含高复杂度电子电路的大多数半导体器件将以硅为基础进行制造，藉此提供硅基板及含硅之基板，如SOI(绝缘体上硅)基板、可用于形成半导体器件(如微处理器、SRAM、ASIC(特殊应用积体电路)、晶片上系统(SoC)、及类似器件)之基底材料。个别的积体电路系以阵列形式排列在晶圆上，其中，除了光微影制程、计量制程及切割该基板之后封装个别器件以外，大部份的制造步骤(可能涉及数百道或更多道个别制程步骤)系同时实施在该基板上所有的晶片面积。因此，成本上的约束驱使半导体制造商持续地增加该基板尺寸，也藉此增加能够用于制造实际半导体器件之面积，并且因而增进产品良率。
除了增加该基板面积以外，对于给定之基板尺寸进行基板面积使用的最佳化也非常重要，以尽可能将实际较多的基板面积用于半导体器件及/或可用于制程控制之测试结构。试图对于给定之基板尺寸得到最大的可使用表面积，电路元件之特征尺寸持续地缩减。由于对于高精密度半导体器件之特征尺寸缩减的持续性需求，铜结合低K介电材料已成为经常用以形成所谓互连结构(interconnect structure)的替代材料，该互连结构包括金属线路层及中间的介层窗层(via layer)，该介层窗层包含作为层内(intra-layer)连接之金属线路及作为层间(inter-layer)连接之介层窗，该互连结构共同连接至个别电路元件，以提供该积体电路所需之功能性。典型上，堆叠在彼此顶上的复数个金属线路层与介层窗层必须实现所有内部电路元件及I/O(输入/输出)、电源及接地垫片之间的连接。
对于极度微缩之积体电路而言，信号传递延迟不再受到电路元件(如场效电晶体)所限制，反之，由于线对线电容值(line-to-linecapacitance)增加结合因截面积缩减而降低的线路传导能力，故信号传递延迟系受邻近的金属线路所限制(因为电路元件的密度增加，需要更大量的电性连接)。基于这个原因，传统的介电材料(如二氧化硅(k＞4)及氮化硅(k＞7))系通过具有较低介电常数(permittivity)的介电材料所取代，该等介电材料也因此称为低k介电材料，具有3或更低的相对介电常数。然而，低k材料的密度与机械稳定度或强度明显较经良好印证的介电材料(二氧化硅及氮化硅)稍差。如此一来，在形成该金属化系统以及任何接下来的积体电路制造程序期间，产品良率可能取决于敏感介电材料(如低k介电层)的机械特性以及该敏感介电材料与其他材料之黏接。
除了先进介电材料(具有3.0或更低的介电常数)机械稳定度较低的问题以外，由于不同材料热膨胀所对应的热不匹配所造成该晶片与该封装件之间的交互作用，故使得这些材料可能在精密半导体器件的运作期间对器件的可靠度造成影响。举例而言，在复杂积体电路的制造中，不断增加的接点技术可用于将封装件载体连接至该晶片，系为了习知的覆晶封装技术。与经良好建立的导线接合技术(其中，可在该晶片非常后端之金属层周遭置放适当的接触垫片，该接触垫片可通过介层窗连接至该封装件对应之端点)相反，在覆晶技术中，可在该最后金属化层上形成个别的凸块结构(例如：通过焊锡材料所组成)，该凸块结构可与该封装件之个别接触垫片相接触。因此，在回流焊接(reflow)该凸块材料之后，可在该最后金属化层与该封装件载体的接触垫片之间建立可靠的电性及机械连接。以这种方式，可在该最后金属化层之整体晶片面积上设置非常大量的电性连接，具有降低的接点电阻值及寄生电容值，藉此提供复杂积体电路(如CPU、储存记忆体及类似电路)所需之IO(输入/输出)能力。在连接该凸块结构与封装件载体之对应制程序列期间，某种程度的压力及/或热能可能施加在该混合器件，以在形成在该晶片上的各个凸块及可能设置在该封装件基板上的凸块或垫片之间建立可靠的连接。然而，热诱导应力或机械诱导应力也可能作用于较下层的金属化层，该较下层的金属化层典型上可能包含低k介电材料或甚至极低k(ULK)介电材料，由于机械稳定度及对其他材料的黏接性下降，因此可能使得通过这些敏感材料的剥离所造成的缺陷显著增加。
此外，因为精密积体电路量产的成本约束典型上该封装件必须使用特定基板材料(如有机材料)，该基板材料典型上可显现出不同在硅晶片的热传导能力及热膨胀系数，故由于硅基(silicon-based)半导体晶片与该封装件基板之热膨胀行为的明显不匹配，造成在经附接至对应封装件基板的最终半导体器件之运作期间，可能发生明显的机械性应力。
在最近的研究发展中，通过设置铜柱体而非设置焊锡凸块或焊锡球，可增进”凸块结构(bump stucture)”的热效能及电性效能，藉此降低个别接点元件所需之平面空间(floor space)，也因为铜较典型上所使用之焊锡材料具有更优异的特性，而加强热及电性传导能力。然而，由于相较在该凸块结构，铜柱体典型上较无法变形，故这些铜柱体可能在该晶片的封装件与金属化系统之间造成更严重的交互作用，以电性及热行为的观点而言，铜柱体较有利，但是可能以非常受限的方式局部地造成机械性应力成份的增加，如同将参照第1a及1b图所详述。
第1a图示意地描绘包括经连接至封装件基板170之半导体晶粒或晶片100之积体电路150之剖面图式，该封装件基板170实质上系通过有机材料(如适当的聚合物材料(polymer material)及类似的材料)所组成，其中，可通过柱体结构160达成该晶片100与该封装件基板170之间的连接。根据电路布局的总体组构以及该积体电路150之效能，该半导体晶片100典型上可包括基板101(例如：硅基板或SOI基板)。此外，硅基半导体层102典型上可设置在该基板101”上方”，其中，该半导体层102可包括该积体电路150所欲之功能行为所需非常大量的电路元件(如电晶体、电容器、电阻器及类似的元件)。如先前所讨论，电路元件关键尺寸的持续缩减可能造成电晶体关键尺寸达到50奈米与明显小在目前精密半导体器件量产所能达到的等级。该半导体晶片100包括金属化系统100，在先进的器件中，该金属化系统100包括复数个金属化层(亦即，器件层次)，其中，金属线路与介层窗系镶嵌在适当的介电材料中。如先前所讨论，为了产生邻近金属线路的寄生电容值，各种金属化层中所采用的至少一部份对应的介电材料通常系通过经降低机械稳定度的材料所组成。如同先前所说明，可设置该柱体结构160作为一部份该金属化系统110，其中，该对应的铜柱体系设置在该系统1000之非常后端的金属化层中。另一方面，在施加热及/或机械压力之后，为了建立个别的机械性及电性连接，该封装件基板170包括经适当放置且具适当尺寸的接触垫片(未显示)，该接触垫片可与对应的柱体或形成在其上的任何焊锡材料相接触。再者，为了连接该柱体结构160之上侧柱体及对应的端点(terminal)，该封装件基板170通常包括适当的传导线路，该端点接着建立与其他周围组件(如印刷电路板等)的电性介面。为了方便起见，并未显示任何此类传导线路。
在该积体电路150的运作期间，在该半导体晶片100内产生热，例如由于形成在该半导体晶片100中及形成在该半导体层102上方的电路元件所产生。根据该基板101之总体热传导能力，此废热系通过例如该金属化系统110及该主体结构160以高效率的方式及/或经通过该基板101而散逸。举例而言，由于经埋藏的绝缘氧化物层(buriedinsulating oxide layer)的热传导能力明显降低，该经埋藏的绝缘氧化物层将该半导体层102与剩下的基板材料分隔开，故SOI基板的热散逸能力明显较纯硅基板为差。因此，主要的热散逸路径系通过该柱体结构160及该封装件基板170所提供。如此一来，适度的高平均温度系产生在该半导体晶片100及该封装件基板170中，其中，如先前所讨论，这两种组件之间的热膨胀系数的不匹配可能造成明显的机械性应力。例如箭头103与173所示，该封装件基板170相较在该半导体晶片100可能具有较大的热膨胀，其中，对应的不匹配可能因而造成明显的热应力，尤其是在该半导体晶片与该封装件基板170之间的”介面”，也就是说，在该积体电路150的运作期间，该柱体结构160与该金属化系统110可能面临通过热不匹配造成的纯力量(sheerforce)。由于机械稳定度的降低以及精密介电材料之黏接性下降，造成可能发生对应的缺陷，该缺陷可能影响该积体电路150之总体可靠度。具体而言，该柱体结构160之个别柱体之刚性(stiffness)可能造成局部的纯力量(sheer force)，该力量系转移进入该整体金属化系统，因而造成剥离缺陷及类似的缺陷。因此，尽管晶片与封装件基板之间先进的接点体制(contact regime)能够对于减少的平面空间提供明显较佳的热散逸能力及电性传导能力，因而能够加强用于热散逸之接点元件及/或假元件(dummy element)的密度，但是在该金属化系统中所诱导增加的机械性应力无法符合该半导体器件之可靠度需求。基于这个原因，经常降低该铜柱体的高度，但是可能对应地降低该封装件基板与该晶片之间的间隔，如此一来，可能造成底部填充材料(underfillmaterial)的不可靠填入(non-reliable filling in)。因此，该底部填充材料中的对应空洞亦可能造成高度的非可靠性，例如：热传导能力的不均匀及类似特性。因此，在一些习知的方法中，系通过增加无引脚焊锡罩盖(lead-free solder cap)补偿经降低的柱体高度，藉此维持该封装件基板与该晶片之间所欲的距离。然而，由于在该铜柱体之顶部上设置焊锡材料将明显增加制造上的复杂度，故对应的制造策略可能造成成本的增加。在其他习知方法中，为了加强该金属化系统之机械稳定度，可基于较不敏感的低k材料或极低k材料形成该金属化系统，然而，由于寄生电容值的增加，可能显著降低电性效能，造成信号传递延迟的增加。
有鉴于上述情形，本发明所揭露之内容系关于在设置柱体结构的同时，也能够避免或至少降低上述所提及的一种或多种问题的方法及半导体器件。
发明内容
一般而言，本发明所揭露之内容系关于半导体器件及制造技术，其中，经通过柱体结构(pillar structure)自封装件基板转移进入复杂积体电路之金属化系统的机械性应力可经”分散”在增加的表面积，藉此相较在习知策略降低局部应力负载(local stress load)。即便采用精密的界电材料，仍可通过增加该金属化系统之最终钝化层之表面部份而达成该机械性应力分布，该表面部份系与该柱体紧密机械接触，使得该最终钝化层可作为应力缓冲层或可更有效地分散该机械性应力，藉此降低产生与遍及整体金属化系统的缺陷相关的应力之可能性。在本说明所揭露的一些说明态样中，经通过应力分布元件或组件可达成该应力分布，该应力分布元件可经理解为与该柱体直接机械接触且亦与该最终钝化层之介电材料直接机械接触的元件，藉此增加能够使得应力自该柱体转移进入该最终钝化层的介电材料之表面积。在一些说明实施例中，该应力分布元件可置放在该最终钝化层内，如此可达到与该介电材料的大面积接触，藉此作为该柱体之”靠山(anchor)”。在其他情况下，该应力分布层可形成在该最终钝化层上，藉此环绕包围该柱体。在本说明书所揭露之其他说明态样中，在形成该柱体结构之制程序列期间，可适当地选定适当的参数(如该最终钝化层之厚度、连接至该接触垫片之对应开口之直径及该柱体之直径)，以便提供增加的表面积，可容置该柱体之机械性应力，且该机械性应力最终可转移进入该最终钝化层。因此，该局部应力负载可维持在可接受的程度，同时也提供维持该柱体所欲之间隔或高度且无须过度增加制程复杂度的可能性。
本说明书所揭露之一个说明半导体器件，包括形成在基板上方之金属化系统，其中，该金属化系统包括复数个金属化层及最终接点层，该最终接点层包括接触垫片。再者，最终钝化层系形成在该最终接点层上方且包括开口，该开口系对准该接触垫片。再者，金属柱系延伸自该最终钝化层，且系与该接触垫片电性接触。此外，该半导体器件包括应力分布元件，该应力分布元件系经形成为与该最终钝化层接触，其中，该应力分布元件系与一部份该金属柱接触，以便增加用于使应力自该金属柱转移至该最终钝化层之有效面积(effective area)。
本说明书所揭露之一个说明方法，包括在半导体器件之金属化系统上方形成最终钝化层，其中，该金属化系统包括接触垫片。再者，开口系形成在该最终钝化层中，该开口对准该接触垫片。此外，以...为基础定义该应力分布区域之侧向尺寸之遮罩而形成应力分布区域，其中，该应力分布区域系与该最终钝化层相接触。再者，沉积遮罩系形成在该最终钝化层上方，而金属柱系利用该沉积遮罩所形成，其中，该金属柱系延伸自该应力分布区域。
本说明书所揭露之另一个说明方法，系关于形成半导体器件。该方法包括在复数个金属化层上方形成最终钝化层，并且在该最终钝化层中形成开口，以便曝露一部份接触垫片。该方法复包括形成延伸自该最终钝化层且连接至该接触垫片之金属柱。该方法额外包括控制以下条件之至少一者：
该最终钝化层之厚度与该金属柱之直径的比例为大约0.5或更高；以及
该金属柱之该直径与该开口之直径的比例为大约1.5或更高。
附图说明
本发明所揭露之内容之进一步实施例系定义在附加的申请专利范围中，且通过详细说明书内容参考附加图式将更清楚了解本发明所揭露之内容，其中：
第1图根据习知之设计示意地描绘包含通过柱体结构进行连接之半导体晶片与封装件基板之积体电路的剖面图式；
第2a-2d图根据说明实施例示意地描绘半导体器件在以用于降低局部应力负载之应力分布组件为基础之金属化系统中形成柱体之各种制造阶段期间的剖面图式；
第2e图根据进一步的说明实施例示意地描绘半导体器件的剖面图式，其中，对应的应力分布元件或柱体之侧向延伸可镶嵌在最终钝化层之子层中；
第2f及2g图根据说明实施例示意地描绘当对应的应力分布组件或柱体之侧向延伸可形成在该最终钝化层之第一子层上时，该半导体器件在不同制造阶段期间的剖面图式；
第2h图根据进一步的说明实施例示意地描绘金属化系统在先进的制造阶段中之剖面图式，其中，最终钝化层中开口之直径相对于柱体之直径的比例系经适当地调整，以便加强该应力分布；以及
第2i图根据另一说明实施例示意地描绘包含柱体之金属化系统，该柱体可基于该最终钝化层之厚度与该柱体之直径经适当选定的比例而形成，用于加强该最终钝化层之应力缓冲效果。
具体实施方式
尽管本发明所揭露之内容系参考如下详细说明书以及图式所说明之实施例进行描述，但是应了解到，以下详细说明书以及图式并非意图将本发明所揭露之内容限定在所揭露之特定说明实施例，反之，所述之说明实施例仅仅体现本发明所揭露之内容的各种态样，本发明的各种态样之范畴系定义在附加的申请专利范围。
一般而言，本发明所揭露之内容提供半导体器件及技术，其中，可有效地使用包含金属柱之精密金属化系统，而无须过度增加该金属化系统之局部应力负载，藉此提供使用高度精密的介电材料之可能性，如先前所述，高度精密的介电材料相较在习知介电材料可能具有较低的机械稳定度。对于给定之柱体组构而言，通过分散或缓冲该机械性应力，可有效地降低该局部应力负载，此目的可通过显著增加该最终钝化层之表面积而达成，该表面积系紧密地机械连接至该柱体。基于这个原因，在一些说明实施例中，可设置有应力分布组件或元件，以便作为该柱体之”靠山”，使得该应力分布组件能够黏接至该最终钝化层所增加的表面积，因此可施加明显较低的应力水平至该金属化系统之潜在区域(underlying region)。举例而言，该应力分散组件(stressed distribution component)可镶嵌在该最终钝化层中，或者可经形成使得本身一部份系设置在该最终钝化层之表面上。除了设置对应该金属柱的应力分布元件或靠山以外，又或者替代地，可相对于该金属柱所欲之直径适当地选定该最终钝化层之尺寸及/或形成在其中的对应开口，以便在该金属柱及该最终钝化层之间提供增加的接触面积(contact area)。也就是说，在增加该最终钝化层的厚度之后，可适当地增加该最终钝化层与一部份透过该钝化层延伸至该接触垫片的金属柱相接触之表面层(surface layer)，使得大量机械性应力可转移进入该钝化层，可接着提供该机械性应力成份所欲之分散程度。除了此测量以外，又或者可相对于该金属柱之直径降低该钝化层中对应之开口之宽度或直径(亦即，相对于延伸自该最终钝化层之组件)，使得位在该最终钝化层上之金属柱之表面积明显增加，亦可加强应力分布效率。因此，可依据经良好建立之制程策略来选定该金属柱之个别几何组构，也就是说，可采用适当的金属柱高度，以便确保该半导体晶片与对应的封装件基板之间的适度间隔，但同时在该对应之金属柱附近可能发生局部应力负载的降低，藉此容许使用精密的金属化体制。
参照第2a-2h图，现在将更详细地说明进一步的说明实施例，其中，倘若适当的话，亦可参照第1图。
第2a图示意地描绘半导体器件200在先进的制造阶段中之剖面图式。如图所示，该半导体器件200可包括基板201(如硅基板、SOI基板、及类似的基板)，作为该半导体器件200之总体组构所需。此外，器件层次(device level)或半导体层202可形成在该基板201上方，且可包括大量的电路元件(如电晶体、电容器、电阻器及类似的元件)，该等电路元件可基于对应该器件200之适当设计规则而形成。举例而言，取决于总体器件需求，该器件层次202中的电路元件的关键尺寸可为大约50奈米或更小。应该体认到，虽然本说明书所揭露之技术相当有利在复杂的半导体器件，但是用于形成柱体结构之对应体制亦可有利在应用在更小的关键半导体器件，其中，该电路元件可具有50奈米及更小的关键尺寸。再者，该半导体器件200可包括金属化系统210，该金属化系统210典型上包含复数个金属化层220、…、240，在一些说明实施例中，至少一些金属化层可包含如先前所讨论的敏感介电材料。此外，最后的金属化层240(亦可称作为最终接点层)可能在其中形成有接触垫片241形式之金属区域，该金属区域可通过任何适当的材料(如铜、铝、铜/铝及类似的材料)所形成。应该体认到，在精密的金属化系统中，如同先前所讨论，由于有鉴于铜材料优异的热及电性传导能力，故可以铜材料为基础来设置该金属线路(metal line)与介层窗(via)。然而，应该体认到，金属化系统亦包含其他材料(如铝、银、及类似材料)，在本说明书中也考量到结合其他金属之可能性。此外，倘若需要的话，当认为该金属与周围的介电材料242直接接触系不适当时，为了可靠地限定对应之金属(如铜)，该接触垫片241亦可包括任何适当的阻障材料(barrier material)。此外，有鉴于钝化、机械整合性及类似的总体特性，最终钝化层260可形成在该最后金属化层240上方，且可包括两个或多个子层261、262。举例而言，该第一子层261可通过二氧化硅(silicon dioxide)、氮化硅(silicon nitride)及类似的材料所组成，同时该第二子层262可代表钝化材料(如聚酰胺(polyamide)及类似的材料)。在所示之制造阶段中，开口263可形成在该最终钝化层260中，以便延伸至该接触垫片241，其中，可基于经适当定义之条件来选定该开口对应之侧向尺寸及该最终钝化层260之厚度，用于加强该最终钝化层260之应力分布效果，如同稍后将参考第2h及2i进行更详细说明者。在其他说明实施例中，可依据经良好建立的制程策略来形成该开口263之宽度或直径，使得该最终钝化层260及该开口263之对应特性可与在该最终钝化层260上方形成柱体之习知策略相容。再者，可设置有遮罩264，以便定义连接至仍有待形成在该最终钝化层260上方之金属柱之应力分布组件或元件的位置及侧向尺寸。应该体认到，该遮罩264所定义之侧向尺寸明显大在仍有待形成之对应金属柱之对应侧向尺寸或直径。也就是说，对于对应之金属柱所欲大约30-100微米之直径而言，该遮罩264所曝露的侧向尺寸可能介在大约50-200微米的范围，藉此明显增加用于将应力自金属柱转移及分散进入该最终钝化层260之表面积。
可基于以下制程策略形成如第2a图所示之半导体器件200。可基于经良好建立的制程策略形成该器件层次202中之电路元件以及包含该金属化层220、230与240之金属化系统210，可维持与所欲之技术标准及制程流程的高度相容性。在那之后，可通过例如沉积对应的介电材料(如子层261与262)形成该最终钝化层260，并且接着通过经良好建立的微影技术来图案化该介电材料。举例而言，该聚酰胺材料262可经设置成光敏材料之形式，且可在蚀刻该子层261之前，通过对应的显影制程对该聚酰胺材料262进行图案化。在其他情况下，为了曝露一部份接触垫片241，可设置对应的光阻遮罩，以便蚀刻透过该最终钝化层260。倘若与该最终钝化层260之材料直接接触被认为不适当，倘若需要的话，则为了限定对应的反应金属(reactive metal)(如铜)，倘若需要的话，可沉积任何适当的阻障材料265。此外，该阻障层265可有利在加强黏接欲形成在该开口263中及该最终钝化层260之曝露部份上的金属。基于此原因，可采用任何适当的材料，如铬、铜、钽、氮化钽(tantalum nitride)及类似的材料、或者各种材料之组合。在那之后，该遮罩264可设置成例如光阻材料(resist material)之形式。在一些说明实施例中，当填充进入该遮罩264之开口的材料无法与所要求的热及电性效能相容时，该遮罩264亦可覆盖该开口263(如同该遮罩部份264a所指出)，以便将该接触垫片241连接至仍有待形成之金属柱。举例而言，在形成该遮罩264之后，可通过例如电化学沉积技术沉积金属材料，其中，倘若设置有该阻障层265，则该阻障层265可作为电流分散层(current distribution layer)，藉此实行电镀制程(electroplating process)。在其他情况下，尤其当无法设置该阻障层265时，可实施无电电镀制程(electroless plating process)，使得对应的金属族群(metal group)可在与接触垫片241接触之后被接纳。在其他情况下，当该遮罩部份264a可覆盖该开口263时，在无电沉积制程期间，可基于该阻障层265得到适当的底部至顶部填充行为(bottom-to-top fill behaviour)。应该体认到，可填入任何适当的金属，如铜、铝、钨(tungsten)及类似的金属。举例而言，倘若所欲之材料本身对该最终钝化层260或该材料265提供高度的黏接性，且亦可牢固地黏接至欲用于该金属柱之金属，则可基于该遮罩部份264a形成此材料对应的靠山或环(ring)。在其他说明实施例中，该遮罩264之开口可填充有亦可用于设置该金属柱之相同的金属，使得亦可在对应的填充制程期间基于经良好建立的沉积技术填充该开口263。举例而言，可将铜填充进入该遮罩264之开口。在那之后，该遮罩264(可能结合该部份264a)可经移除，且(倘若需要的话)可例如基于湿式化学蚀刻配方实施对应的清洁制程。
第2b图示意地描绘在上述制程序列之后的半导体器件200。如图所示，应力分布组件或元件272可形成在该最终钝化层260上方，且在所示之实施例中，可延伸进入该开口263，以便经通过该阻障层265(倘若有设置)电性连接至该接触垫片241。在其他说明实施例中，当该遮罩部份264a(如第2a图所示)已经在该对应的材料之沉积期间经使用时，该应力分布元件272未包括内部部份(interiorportion)272a(如虚线所指示)。在所示之实施例中，该元件272可通过高传导性金属(如铜及类似金属)所组成。
第2c图示意地描绘在进一步先进的制造阶段中之半导体器件200，其中，沉积遮罩203(如光阻遮罩)系形成在该金属化系统210上方，包括开口203a，该开口203a之侧向尺寸203w可符合欲形成在该开口203a中的金属柱之直径或侧向尺寸。应该体认到，根据欲用于将适当金属填充进入该开口203a之沉积技术，该阻障层265(如第2a图所示)可已自该最终钝化层206经曝露之部份移除，同时，在其他情况下，该阻障层265仍然可存在，以便作为电镀制程所使用之电流分散层。在其他情况下，可使用无电沉积配方，其中，该应力分布元件272可作为催化材料(catalyzing material)。
第2d图示意地描绘在先进的制造阶段中之半导体器件200，其中，金属柱271系形成在该最终钝化层260上方，以便向该最终钝化层260延伸，其中，在所示之实施例中，该金属柱271可形成在该应力分布元件272上。因此，如图所示，该应力分布元件272之侧向宽度(如272w所示)明显大在该直径或宽度271w，使得该柱体271可经通过该元件272而附接至该最终钝化层260，藉此有效率地分散通过附接该柱体271至封装件基板所造成的机械性应力203，如同先前参照第1图及该积体电路150所说明。因此，高强度之应力成份203可经通过该应力分布元件272而分散，藉此产生经降低的局部应力成份203a，该经降低的局部应力成份203a可分散在该金属化系统210所增加的侧向面积。
第2e图根据其他说明实施例示意地描绘该半导体器件200，其中，该应力分布元件272可镶嵌在该最终钝化层260中。在所示之实施例中，该应力分布元件272可形成在第二子层262内，可通过沉积该第二子层262之第一部份262a且基于对应之遮罩(如第2a图所示之遮罩264)在其上形成该应力分布元件272且沉积适当的材料(如金属)而达成。在那之后，可沉积并且图案化进一步部份262b，以便基于形成该金属柱271所需之侧向尺寸曝露一部份该应力分布元件272。因此，如先前所述，在开口该部份262b之后，可沉积所欲之金属。应该体认到，倘若认为可靠的限定(confinement)系适当的，则在形成该应力分布元件272之后，可在该应力分布元件272经曝露之表面积上形成适当的罩盖材料(cap material)或阻障材料。举例而言，可基于无电沉积技术达成复数个经良好建立的金属合金之选择性沉积。在那之后，可依据如先前所述之任何微影技术来沉积并图案化该部份262b。在那之后，可设置适当的遮置且可如上所述用于沉积该柱体271。因此，通过在该最终钝化层260中镶嵌该应力分布元件272，该最终钝化层260所进一步增加的表面积可与该应力分布元件272相接触，依序紧密地机械耦接至该柱体271。因此，该应力分布元件272可代表该柱体271之靠山，其中，所增加的表面积亦可用于有效率地分散作用于该柱体271上的任何机械性应力成份。
第2f图根据进一步的说明实施例示意地描绘该半导体器件200，其中，该应力分布元件272可形成在该子层261上，其中，应该体认到，对应的阻障材料265(倘若有设置)可经认为系该应力分布元件272之一部份。此外，应注意到，如先前所说明，根据总体制程策略，该应力分布元件272可经设置为不具有中央部份(centralportion)272a。如第2f图所示之应力分布元件272可基于如先前所讨论之类似制程技术而形成。也就是说，在沉积且图案化用于连接至该接触垫片241的子层261之后，为了设置如先前所述之应力分布元件272，可沉积该阻障材料265(倘若需要的话)且形成对应之遮罩，以便容许沉积适当的材料(如金属)。应体认到，倘若该应力分布元件272系经设置成不具有中央部份272a的环形组件(annular component)，则连接至该接触垫片241的对应开口亦可在稍后的阶段中形成。
第2g图示意地描绘在进一步先进制造阶段中之半导体器件200，其中，该第二子层262系经设置且图案化，以具有开口262a。在那之后，通过设置对应的沉积遮罩以及利用适当的金属(如铜)填充该开口262a与该沉积遮罩之对应开口，可继续进一步的处理，藉此亦形成对应的金属柱，亦如同先前所讨论。应体认到，倘若认为适当，则在沉积该子层262之前，该应力分布元件272可容置适当的阻障材料。基于此原因，可采用如先前所讨论之类似制程技术。
因此，在此情况下，该应力分布元件272亦可有效率地镶嵌在该最终钝化层262中，藉此提供经加强的机械稳定度及高效率的应力分布效果。
第2h图根据进一步的说明实施例示意地描绘该半导体器件200，其中，该金属柱271可形成在该最终钝化层260上，使得相较在习知策略，该最终钝化层260能够具有更多与该金属柱271相接触的表面积，此目的可通过例如在该金属柱271之形成期间适当地缩减先前已形成在该最终钝化层260中之开口263之侧向宽度263w并且以金属填充该开口263而达成。在一些说明实施例中，该宽度271w与该宽度263w之比例可选定为大约1.5或更高。由于该金属柱271所占据之表面积随着该宽度263w的缩减而呈现二次方(quadratically)增加，故基于上述特定尺寸选定对应之比例可得到明显增进的应力分布效果。在进一步的说明实施例中，该直径271w与该开口263之直径263w的比例可选定为大约2.0或更高。
在一些说明实施例中，适当选定该宽度271w与该宽度263的比例之概念可有利在结合设置应力分布元件(如第2e及2f图所描绘之元件272)，除了增加该柱体271在该层262上所占据的表面积以外，该经镶嵌的元件272能够额外地增进应力分布效果之效率。
第2i图根据进一步的说明实施例示意地描绘该半导体器件200，其中，通过适当选定该最终钝化层260之厚度260t与该柱体271之直径271w的比例为大约0.5或更高，可达到增进应力转移效率。也就是说，通过增加厚度260t，连接该柱体271之材料(亦即，自该最终钝化层260延伸至该接触垫片241之部份)可附接至该最终钝化层260所明显增加的表面积。因此，作用于该柱体271上的任何机械力皆可更有效率地经转移进入该最终钝化层260，藉此亦可得到所欲之应力分散效果。举例而言，在一个说明实施例中，该厚度260t与该直径271w之比例可经选定为1.0或更高。应该体认到，除了根据上述特定比例增加该厚度260t以外，亦可缩减该宽度263w，以便额外提供可通过该柱体271所占据之经加强的表面部份，如同参照第2h所说明者。再者，参照第2i图所描述之实施例亦可结合有关于第2d、2f及2g图所示之应力分布元件272之任何实施例。举例而言，该元件272可如先前所讨论般镶嵌在该最终钝化层260中，且/或该元件272可能结合设置在该最终钝化层260内之额外元件而形成在该最终钝化层260上。
如此一来，本发明所揭露之内容提供了半导体器件及制造技术，其中，通过有效率地将应力成份分散进入该钝化层，能够降低金属柱附近的局部应力水平。因此，例如有鉴于所欲之高度及侧向宽度，可采用适当的金属柱尺寸，同时亦可在该金属化系统中采用敏感的介电材料，而不致过度造成与应力相关之效应。
参照本说明书将使得所属技术领域中具有通常知识者更清楚了解本发明所揭露之内容的进一步修改及变化。因此，本说明书系经理解为仅仅作为说明之用，且目的在在教示所属技术领域中具有通常知识者实现本发明所揭露之原理之一般性方法。应理解到，本说明书中所显示及说明之形式系为目前的较佳实施例。

Claims (20)

1.一种半导体器件，包括：
金属化系统，系形成在基板上方，该金属化系统包括复数个金属化层及最终接点层，该最终接点层包括接触垫片；
最终钝化层，系形成在该最终接点层上方，该最终钝化层包括开口，该开口对准该接触垫片；
延伸自该最终钝化层之金属柱，该金属柱系与该接触垫片接触；以及
应力分布元件，系形成为与该最终钝化层接触，该应力分布元件系与一部份该金属柱接触，以便增加用于使应力自该金属柱转移至该最终钝化层之有效面积(effective area)。
2.如申请专利范围第1项所述之半导体器件，其中，该应力分布元件系形成在该最终钝化层上，以便环绕包围该一部份该金属柱。
3.如申请专利范围第1项所述之半导体器件，其中，该应力分布元件系通过金属所组成。
4.如申请专利范围第1项所述之半导体器件，其中，该应力分布元件系形成在该最终钝化层中。
5.如申请专利范围第4项所述之半导体器件，其中，该应力分布层系形成在该最终钝化层之第一子层(sub-layer)上，且系通过该最终钝化层之第二子层之材料所覆盖。
6.如申请专利范围第4项所述之半导体器件，其中，该最终钝化层包括形成在该接触垫片上之第一子层及形成在该第一子层上之第二子层，且其中，该应力分布元件系镶嵌在该第二子层中。
7.如申请专利范围第1项所述之半导体器件，其中，该金属柱包括铜。
8.如申请专利范围第1项所述之半导体器件，其中，该金属柱的宽度大约为30微米至100微米。
9.如申请专利范围第1项所述之半导体器件，其中，该应力分布区域的宽度大约为50微米至200微米。
10.如申请专利范围第8项所述之半导体器件，其中，该应力分布元件系通过铜所组成。
11.一种方法，包括：
在半导体器件之金属化系统上方形成最终钝化层，该金属化系统包括接触垫片；
在该最终钝化层中形成开口，该开口对准该接触垫片；
以定义该应力分布区域之侧向尺寸之遮罩为基础而形成应力分布区域，该应力分布区域系与该最终钝化层相接触；
在该最终钝化层上方形成沉积遮罩；以及
利用该沉积遮罩形成金属柱，该金属柱系延伸自该应力分布区域。
12.如申请专利范围第11项所述之方法，其中，形成该应力分布区域包括形成该遮罩，以便曝露围绕该开口之该最终钝化层之至少一子层之一部份，并且沉积金属。
13.如申请专利范围第12项所述之方法，复包括移除该遮罩，并且在该最终钝化层之该至少一子层上方形成介电材料。
14.如申请专利范围第13项所述之方法，其中，该介电材料及该至少一子层系通过相同材料所组成。
15.如申请专利范围第11项所述之方法，其中，形成该应力分布区域包括形成该最终钝化层之第一子层，其中，该遮罩系形成在该第一子层上，且其中，该方法复包括在沉积该应力分布区域的该金属之后形成第二子层。
16.如申请专利范围第15项所述之方法，其中，形成该开口包括蚀刻透过该第二子层。
17.如申请专利范围第11项所述之方法，其中，该应力分布区域系通过介电材料所形成。
18.一种形成半导体器件之方法，该方法包括：
在复数个金属化层上方形成最终钝化层；
在该最终钝化层中形成开口，以便曝露一部份接触垫片；
形成延伸自该最终钝化层且连接至该接触垫片之金属柱；以及
控制以下至少一者
该最终钝化层之厚度与该金属柱之直径的比例为大约0.5或更高，以及
该金属柱之该直径与该开口之直径的比例为大约1.5或更高。
19.如申请专利范围第18项所述之方法，其中，该最终钝化层之厚度与该金属柱之直径的该比例系经控制为大约1.0或更高。
20.如申请专利范围第18项所述之方法，其中，该金属柱之该直径与该开口之直径的比例系经控制为大约2.0或更高。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104124213A (zh) * 2013-04-28 2014-10-29 无锡华润安盛科技有限公司 一种平衡dbc板上应力的方法及dbc板封装结构

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8431492B2 (en) 2010-02-02 2013-04-30 Sandisk 3D Llc Memory cell that includes a sidewall collar for pillar isolation and methods of forming the same
US9312230B2 (en) * 2010-02-08 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pillar structure for semiconductor substrate and method of manufacture
CN102064135B (zh) * 2010-10-21 2015-07-22 日月光半导体制造股份有限公司 具有金属柱的芯片及具有金属柱的芯片的封装结构
US9159638B2 (en) * 2011-05-26 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive via structure
FR2978296A1 (fr) * 2011-07-20 2013-01-25 St Microelectronics Crolles 2 Puce electronique comportant des piliers de connexion, et procede de fabrication
US8922006B2 (en) 2012-03-29 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Elongated bumps in integrated circuit devices
US9136234B2 (en) 2013-07-09 2015-09-15 Globalfoundries Inc. Semiconductor device with improved metal pillar configuration
KR102574452B1 (ko) 2018-07-03 2023-09-04 삼성전자 주식회사 반도체 칩 및 이를 포함하는 반도체 패키지
US20210125948A1 (en) * 2019-10-28 2021-04-29 Nanya Technology Corporation Semiconductor device and method for fabricating the same
US11322458B2 (en) * 2020-04-27 2022-05-03 Nanya Technology Corporation Semiconductor structure including a first substrate and a second substrate and a buffer structure in the second substrate

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09321048A (ja) * 1996-05-29 1997-12-12 Toshiba Corp バンプ構造体、バンプ構造体の製造方法、ベアチップおよびベアチップの実装方法
US20030025202A1 (en) * 2001-07-17 2003-02-06 Nec Corporation Semiconductor device having an external electrode
US20040175914A1 (en) * 2003-03-06 2004-09-09 Yoshinori Shizuno Semiconductor device fabrication method
US20050017376A1 (en) * 2003-07-23 2005-01-27 Advanced Semiconductor Engineering Inc. IC chip with improved pillar bumps
CN1670954A (zh) * 2004-03-17 2005-09-21 恩益禧电子股份有限公司 半导体器件及其制造方法
US20080169562A1 (en) * 2006-12-28 2008-07-17 Siliconware Precision Industries Co., Ltd. Semiconductor device having conductive bumps and fabrication method thereof
US20080197490A1 (en) * 2007-02-16 2008-08-21 Chipmos Technologies Inc. Conductive structure for a semiconductor integrated circuit and method for forming the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05283412A (ja) * 1992-02-13 1993-10-29 Mitsubishi Electric Corp 半導体装置，およびその製造方法
JPH09139404A (ja) * 1995-11-16 1997-05-27 Toshiba Corp 半導体装置およびその製造方法
JP2003258014A (ja) * 2002-03-04 2003-09-12 Megic Corp 半導体表面上に金属バンプを形成する方法
JP2004119464A (ja) * 2002-09-24 2004-04-15 Kyocera Corp 半田バンプ付き配線基板およびその製造方法
JP2005064171A (ja) * 2003-08-11 2005-03-10 Renesas Technology Corp 半導体装置およびその製造方法
US7642653B2 (en) * 2006-10-24 2010-01-05 Denso Corporation Semiconductor device, wiring of semiconductor device, and method of forming wiring
JP2008141020A (ja) * 2006-12-01 2008-06-19 Rohm Co Ltd 半導体装置及び半導体装置の製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09321048A (ja) * 1996-05-29 1997-12-12 Toshiba Corp バンプ構造体、バンプ構造体の製造方法、ベアチップおよびベアチップの実装方法
US20030025202A1 (en) * 2001-07-17 2003-02-06 Nec Corporation Semiconductor device having an external electrode
US20040175914A1 (en) * 2003-03-06 2004-09-09 Yoshinori Shizuno Semiconductor device fabrication method
US20050017376A1 (en) * 2003-07-23 2005-01-27 Advanced Semiconductor Engineering Inc. IC chip with improved pillar bumps
CN1670954A (zh) * 2004-03-17 2005-09-21 恩益禧电子股份有限公司 半导体器件及其制造方法
US20080169562A1 (en) * 2006-12-28 2008-07-17 Siliconware Precision Industries Co., Ltd. Semiconductor device having conductive bumps and fabrication method thereof
US20080197490A1 (en) * 2007-02-16 2008-08-21 Chipmos Technologies Inc. Conductive structure for a semiconductor integrated circuit and method for forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104124213A (zh) * 2013-04-28 2014-10-29 无锡华润安盛科技有限公司 一种平衡dbc板上应力的方法及dbc板封装结构

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Application publication date: 20111109