JP2012204495A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2012204495A JP2012204495A JP2011066208A JP2011066208A JP2012204495A JP 2012204495 A JP2012204495 A JP 2012204495A JP 2011066208 A JP2011066208 A JP 2011066208A JP 2011066208 A JP2011066208 A JP 2011066208A JP 2012204495 A JP2012204495 A JP 2012204495A
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- barrier film
- film
- lower barrier
- etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
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- Manufacturing Of Printed Wiring (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
【解決手段】 基板の上に、下部バリア膜を形成する。下部バリア膜の上にシード膜を形成する。シード膜の一部の領域上に、導電部材を形成する。導電部材をエッチングマスクとして、シード膜をエッチングし、導電部材の形成されていない領域において、下部バリア膜を露出させる。下部バリア膜の表面には堆積しない条件で、導電部材の表面に選択的に上部バリア膜を成長させる。上部バリア膜をエッチングマスクとして、下部バリア膜をエッチングする。
【選択図】 図1−2
Description
基板の上に、下部バリア膜を形成する工程と、
前記下部バリア膜の上にシード膜を形成する工程と、
前記シード膜の一部の領域上に、導電部材を形成する工程と、
前記導電部材をエッチングマスクとして、前記シード膜をエッチングし、前記導電部材の形成されていない領域において、前記下部バリア膜を露出させる工程と、
前記下部バリア膜の表面には堆積しない条件で、前記導電部材の表面に選択的に上部バリア膜を成長させる工程と、
前記上部バリア膜をエッチングマスクとして、前記下部バリア膜をエッチングする工程と
を有する半導体装置の製造方法が提供される。
11 半導体チップ
12 充填部材
13 電極パッド
15 基板
20 下部バリア膜
21 シード膜
23 感光性レジスト膜
24 開口
25 導電部材
27 導電プラグ
28 上部バリア膜
29 層間絶縁膜
30 下部バリア膜
31 シード膜
35 導電部材
37 配線
38 上部バリア膜
39 層間絶縁膜
40 電極パッド
41 パッシベーション膜
50 付着物
51 異物
60 絶縁性バリア膜
61 剥離
62 クラック
Claims (5)
- 基板の上に、下部バリア膜を形成する工程と、
前記下部バリア膜の上にシード膜を形成する工程と、
前記シード膜の一部の領域上に、導電部材を形成する工程と、
前記導電部材をエッチングマスクとして、前記シード膜をエッチングし、前記導電部材の形成されていない領域において、前記下部バリア膜を露出させる工程と、
前記下部バリア膜の表面には堆積しない条件で、前記導電部材の表面に選択的に上部バリア膜を成長させる工程と、
前記上部バリア膜をエッチングマスクとして、前記下部バリア膜をエッチングする工程と
を有する半導体装置の製造方法。 - 前記下部バリア膜をエッチングする工程において、反応性イオンエッチングを用いる請求項1に記載の半導体装置の製造方法。
- 前記上部バリア膜は、P、W、及びBの少なくとも1つの元素とCoとを含む合金、またはCoで形成されている請求項1または2に記載の半導体装置の製造方法。
- 前記上部バリア膜は、P、W、及びBの少なくとも1つの元素とNiとを含む合金、またはNiで形成されている請求項1または2に記載の半導体装置の製造方法。
- 前記下部バリア膜をエッチングした後、さらに、前記上部バリア膜及び前記基板の上に、絶縁膜を形成する工程を有する請求項1乃至4のいずれか1項に記載の半導体装置の製造方法。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9553060B2 (en) | 2015-04-10 | 2017-01-24 | Renesas Electronics Corporation | Semiconductor device and manufacturing method therefor |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004304167A (ja) * | 2003-03-20 | 2004-10-28 | Advanced Lcd Technologies Development Center Co Ltd | 配線、表示装置及び、これらの形成方法 |
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- 2011-03-24 JP JP2011066208A patent/JP2012204495A/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2004304167A (ja) * | 2003-03-20 | 2004-10-28 | Advanced Lcd Technologies Development Center Co Ltd | 配線、表示装置及び、これらの形成方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9553060B2 (en) | 2015-04-10 | 2017-01-24 | Renesas Electronics Corporation | Semiconductor device and manufacturing method therefor |
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