CN101308829B - 半导体器件和用于制造boac/coa的方法 - Google Patents

半导体器件和用于制造boac/coa的方法 Download PDF

Info

Publication number
CN101308829B
CN101308829B CN2008100947595A CN200810094759A CN101308829B CN 101308829 B CN101308829 B CN 101308829B CN 2008100947595 A CN2008100947595 A CN 2008100947595A CN 200810094759 A CN200810094759 A CN 200810094759A CN 101308829 B CN101308829 B CN 101308829B
Authority
CN
China
Prior art keywords
film
metal
oxide
subsequently
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2008100947595A
Other languages
English (en)
Other versions
CN101308829A (zh
Inventor
金相喆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DB HiTek Co Ltd
Original Assignee
Dongbu Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dongbu Electronics Co Ltd filed Critical Dongbu Electronics Co Ltd
Publication of CN101308829A publication Critical patent/CN101308829A/zh
Application granted granted Critical
Publication of CN101308829B publication Critical patent/CN101308829B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0381—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11912—Methods of manufacturing bump connectors involving a specific sequence of method steps the bump being used as a mask for patterning other parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01059—Praseodymium [Pr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12528—Semiconductor component

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开了一种半导体器件及制造BOAC/COA的方法。半导体器件的BOAC/COA通过以下步骤制造：在半导体器件之上形成导电焊盘；在包括导电焊盘的半导体器件之上形成钝化氧化膜；在导电焊盘和钝化氧化膜的整个表面上形成氧化膜；在导电焊盘上形成限定结合焊盘区的氧化膜图案；在氧化膜图案、钝化氧化膜和导电焊盘之上依次地形成屏蔽膜和金属种子层；在金属种子层之上形成金属层；整平金属层，从而使氧化膜图案以及屏蔽膜和金属种子层的一部分露出；以及通过蚀刻工艺去除氧化膜图案。

Description

半导体器件和用于制造BOAC/COA的方法
相关申请交叉参考
本申请要求在35U.S.C.119的规定下对于韩国专利申请No.10-2007-0048576(于2007年5月18日提交)的优先权，其全文以引用方式整体结合于此。
技术领域
本发明涉及半导体器件制造领域。
背景技术
如示例图1所示，半导体器件中的有源电路结构上的连接(bonding)(BOAC/COA)可以通过示例图2A到2E中所示的加工方案制造。
例如，如示例图2A所示，金属焊盘203和钝化氧化膜205可以通过半导体工艺形成在半导体(硅)衬底201上面和/或上方。此后，可以将可以由TiW组成的屏蔽金属(barrier metal)207沉积在金属焊盘203和钝化氧化膜205的整个表面的上面和/或上方。
如示例图2B所示，随后可以利用化学气相沉积(CVD)工艺将可以由Cu组成的金属种子(metal seed)209沉积在沉积的屏蔽金属207的整个表面上面和/或上方。此后，可以将光刻胶PR沉积在金属(Cu)种子209的整个表面上面和/或上方。
如示例图2C所示，随后可以通过使用被设计成结合焊盘形成区的中间掩模的曝光和显影工艺选择性去除沉积在整个表面上面和/或上方的PR的一部分，由此在金属种子209的顶部上形成限定结合焊盘形成区的PR图案211。
如示例图2D所示，随后，通过使用硫酸浴执行电镀工艺可以将金属层213沉积在限定结合焊盘形成区的PR图案211中。
如示例图2E所示，随后可以通过汽蒸工艺(steaming process)去除残余的PR图案211，随后选择性去除金属种子209的一部分，由此实施BOAC/COA的制造。
然而，在上述BOAC/COA的制造中，当如上所述地并如示例图2D中所示地那样实施利用硫酸浴的电镀工艺时，这与利用硫酸浴的用于融化PR的金属双嵌刻(metal dual damascene)技术相反，并且因此，金属沉积就非正常地进行。此外，在进行用于选择性去除金属种子209的一部分的汽蒸工艺的情况下，沉积在结合焊盘形成区中的材料也可以被损坏，因为它是与金属种子209相同的金属材料，由此有损于所获得的半导体装置的产量和可靠性。
发明内容
实施方式涉及半导体器件和用于制造BOAC/COA的方法，它们可以通过借助金属双嵌刻工艺来实施BOAC/COA从而降低成本并提高器件性能。
实施方式涉及半导体器件，其可包括下列的至少一个：形成在半导体衬底的整个表面之上的导电焊盘；形成在导电焊盘上的钝化氧化膜；被形成以限定将被形成在导电焊盘和钝化氧化膜的顶部上的结合焊盘区的金属；形成在金属的两个侧壁上的部分屏蔽膜；以及形成在屏蔽膜的两个侧壁上的局部金属种子。
实施方式涉及用于制造半导体器件的BOAC/COA的方法，该方法可包括下列步骤的至少一个：在半导体器件上形成导电焊盘和钝化氧化膜并在导电焊盘和钝化氧化膜的整个表面之上沉积氧化膜；以及随后形成用于限定将被形成在导电焊盘和钝化氧化膜上的结合焊盘区的氧化膜图案；以及随后在于形成氧化膜图案的步骤中形成的氧化膜图案的整个表面之上沉积屏蔽膜和金属种子；以及随后在沉积的金属种子的整个表面之上沉积金属；以及随后整平沉积的金属，直到氧化膜图案以及屏蔽膜和金属种子的一部分露出；以及随后通过蚀刻去除在沉积屏蔽膜和金属种子的步骤中露出的氧化膜图案来制造BOAC/COA。
附图说明
图1和图2A-2E示出了半导体器件的BOAC/COA结构和用于制造该结构的方法。
图3和图4A-4D示出了根据实施例的半导体器件的BOAC/COA结构和用于制造该结构的方法。
具体实施方式
下文中，可以存在根据本发明的多个实施例，并且将参照附图详细描述优选的实施例。对于本领域技术人员，本发明的目的、特征和优点将通过下面这个实施例的描述变得更加显而易见。
图3示出了半导体器件的BOAC/COA结构的垂直横截面视图，该结构可包括形成在半导体衬底401上面和/或上方的金属焊盘403和钝化氧化膜405。用于限定结合焊盘形成区的金属413可在金属焊盘403和钝化氧化膜405上面和/或上方形成。金属413可由诸如铜(Cu)的金属构成。可以由TiW组成的局部屏蔽金属409a可以在金属413的两侧壁上形成。可以由铜(Cu)组成的局部金属种子411a可在已形成的屏蔽金属409a的两侧壁上形成。
结合焊盘形成区可通过在金属焊盘403和钝化氧化膜405的整个表面上沉积氧化膜并选择性去除该氧化膜的一部分而形成。随后，金属413、局部露出的屏蔽金属409a、以及金属种子411a可通过下述步骤形成：在氧化膜图案上面和/或上方形成屏蔽金属和金属(Cu)种子，在屏蔽金属和金属(Cu)种子的整个表面上面和/或上方沉积金属(Cu)413，通过在沉积的金属(Cu)上进行化学机械抛光(CMP)整平工艺而使氧化膜图案以及屏蔽金属409a和金属种子411a的一部分露出，以及随后通过诸如干法蚀刻工艺的氧化膜蚀刻工艺选择性地去除残留的氧化膜图案。因此，通过利用金属(Cu)双嵌刻工艺实施BOAC/COA，实施例可减少成本并提高器件性能。
实施例4A到4D示出了示出了根据实施例的用于制造半导体器件的BOAC/COA的方法。如示例图4A所示，由金属组成的导电焊盘403可在硅衬底401上面和/或上方形成。钝化氧化膜405可在包括导电焊盘403的硅衬底401上面和/或上方形成。随后可在金属焊盘403和钝化氧化膜405的整个表面上面和/或上方沉积氧化膜。随后可选择性地去除氧化膜的一部分从而使金属焊盘403露出，并由此在金属焊盘403和钝化氧化膜405上面和/或上方形成限定结合焊盘形成区的氧化膜图案407。
如示例图4B所示，随后可在氧化膜图案407、钝化氧化膜405和金属焊盘403的整个表面上面和/或上方沉积屏蔽金属(屏蔽膜)409。随后可通过CVD工艺在屏蔽金属409的整个表面上面和/或上方沉积金属种子411。
如示例图4C所示，随后可在金属种子411的整个表面上面和/或上方沉积金属层413。随后可通过CMP工艺整平金属层413，直到氧化膜图案407a以及屏蔽金属409a和金属种子411a的一部分露出。
如示例图4D所示，随后可进行诸如干法蚀刻的氧化膜蚀刻工艺以选择性去除残余的氧化层图案407a。因此，在保留屏蔽金属409a和金属种子411a的一部分的同时，可制造出BOAC/COA。
如上所述，实施方式可提高半导体工艺的产量和可靠性，因为它能解决归因于被硫酸浴引起的PR融化的不正常金属沉积问题。此外，在汽蒸工艺中由相同的金属材料造成的损坏问题可通过利用金属(Cu)嵌刻工艺实施BOAC/COA而解决。此外，本发明可通过提高半导体器件的产量和可靠性而降低成本并提高器件性能。
虽然在此描述了实施方式，但应当理解本领域技术人员可设计多种其它修改和实施方式，这些将落入本公开的原理的精神和范围之内。更具体的，在本说明书、附图和所附权利要求的范围内，在主题组合安排的组成部件和/或布置中各种变化和修改都是可能的。除了组成部件和/或布置中的变化和修改，对于本领域技术人员可选的应用也是显而易见的。

Claims (19)

1.一种半导体器件，包括：
形成在半导体衬底之上的导电焊盘；
形成在所述半导体衬底之上和所述导电焊盘的一部分之上的钝化氧化膜；
形成在所述导电焊盘和所述钝化氧化膜之上的屏蔽膜；
形成在所述屏蔽膜之上的金属种子层；以及
形成在包括所述金属种子层的所述导电焊盘之上的金属层，所述金属层限定结合焊盘区，其中所述屏蔽膜和所述金属种子层设置在所述金属层的侧壁上。
2.根据权利要求1所述的半导体器件，其中所述屏蔽膜包括TiW。
3.根据权利要求1所述的半导体器件，其中所述导电焊盘包括Cu。
4.一种用于制造半导体器件的有源电路结构上的连接的方法，包括：
在半导体器件之上形成导电焊盘；以及随后
在包括所述导电焊盘的所述半导体器件之上形成钝化氧化膜；以及随后
在所述导电焊盘和所述钝化氧化膜的整个表面上形成氧化膜；以及随后
在所述导电焊盘上形成限定结合焊盘区的氧化膜图案；以及随后
在所述氧化膜图案、所述钝化氧化膜和所述导电焊盘之上顺序地形成屏蔽膜和金属种子层；以及随后
在所述金属种子层之上形成金属层；以及随后整平所述金属层从而使所述氧化膜图案以及所述屏蔽膜和所述金属种子层的一部分露出；以及随后
通过蚀刻工艺去除所述氧化膜图案。
5.根据权利要求4所述的方法，其中所述金属层包含Cu。
6.根据权利要求4所述的方法，其中所述屏蔽膜包含TiW。
7.根据权利要求4所述的方法，其中整平所述金属层通过CMP工艺进行。
8.根据权利要求4所述的方法，其中所述蚀刻工艺包括干法蚀刻工艺。
9.一种制造半导体器件的方法，包括：
在硅衬底之上形成金属焊盘；以及随后
在所述硅衬底和所述金属焊盘之上形成作为钝化膜的第一氧化膜并接触所述硅衬底和所述金属焊盘；以及随后
在所述第一氧化膜之上形成第二氧化膜并接触所述第一氧化膜；以及随后
通过选择性去除所述第二氧化膜的一部分来形成氧化膜图案，从而使所述金属焊盘的一部分和所述第一氧化膜的一部分露出；以及随后
在所述氧化膜图案、所述第一氧化膜和所述金属焊盘之上形成作为屏蔽膜的第一金属膜并接触所述氧化膜图案、所述第一氧化膜和所述金属焊盘；以及随后
在所述第一金属膜之上形成作为种子膜的第二金属膜；
以及随后
在所述第二金属种子膜之上形成第三金属膜并接触所述第二金属种子膜；以及随后
通过整平所述第三金属膜而形成金属结合焊盘区，从而使所述氧化膜图案以及所述第一金属膜和所述第二金属膜的一部分露出；以及随后
去除所述氧化膜图案，从而使所述第一金属膜和所述第一氧化膜露出。
10.根据权利要求9所述的方法，其中所述氧化膜图案限定结合焊盘形成区。
11.根据权利要求9所述的方法，其中所述第二金属膜通过CVD工艺形成。
12.根据权利要求9所述的方法，其中整平所述第三金属膜通过CMP工艺进行。
13.根据权利要求9所述的方法，其中利用蚀刻工艺去除所述氧化膜图案。
14.根据权利要求9所述的方法，其中所述蚀刻工艺包括干法蚀刻工艺。
15.根据权利要求9所述的方法，其中所述第一金属膜包含TiW。
16.根据权利要求9所述的方法，其中所述第二金属膜包含Cu。
17.根据权利要求9所述的方法，其中所述第三金属膜包含Cu。
18.根据权利要求9所述的方法，其中所述第二金属膜和所述第三金属膜包含Cu。
19.根据权利要求9所述的方法，其中所述第一金属膜包含TiW而所述第二金属膜和所述第三金属膜包含Cu。
CN2008100947595A 2007-05-18 2008-05-16 半导体器件和用于制造boac/coa的方法 Expired - Fee Related CN101308829B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020070048576A KR100871768B1 (ko) 2007-05-18 2007-05-18 반도체 소자 및 ｂｏａｃ/ｃｏａ 제조 방법
KR10-2007-0048576 2007-05-18

Publications (2)

Publication Number Publication Date
CN101308829A CN101308829A (zh) 2008-11-19
CN101308829B true CN101308829B (zh) 2010-06-02

Family

ID=40026700

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008100947595A Expired - Fee Related CN101308829B (zh) 2007-05-18 2008-05-16 半导体器件和用于制造boac/coa的方法

Country Status (4)

Country Link
US (1) US20080284023A1 (zh)
KR (1) KR100871768B1 (zh)
CN (1) CN101308829B (zh)
TW (1) TW200849433A (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101313690B1 (ko) * 2011-12-30 2013-10-02 주식회사 동부하이텍 반도체 소자의 본딩 구조물 형성 방법
KR102492733B1 (ko) 2017-09-29 2023-01-27 삼성디스플레이 주식회사 구리 플라즈마 식각 방법 및 디스플레이 패널 제조 방법
US11024344B2 (en) 2018-10-09 2021-06-01 International Business Machines Corporation Landing pad in interconnect and memory stacks: structure and formation of the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1431681A (zh) * 2002-01-03 2003-07-23 台湾积体电路制造股份有限公司 利用弹性体电镀掩模做为芯片级封装的方法
CN1630039A (zh) * 2003-11-18 2005-06-22 国际商业机器公司 选择性电镀半导体器件的输入/输出焊盘的方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5953626A (en) * 1996-06-05 1999-09-14 Advanced Micro Devices, Inc. Dissolvable dielectric method
JPH11186309A (ja) 1997-12-19 1999-07-09 Sony Corp 半導体装置および半導体装置の製造方法
KR100385042B1 (ko) * 1998-12-03 2003-06-18 인터내셔널 비지네스 머신즈 코포레이션 내 일렉트로 마이그레이션의 구조물을 도핑으로 형성하는 방법
US7381642B2 (en) * 2004-09-23 2008-06-03 Megica Corporation Top layers of metal for integrated circuits
US6500750B1 (en) * 1999-04-05 2002-12-31 Motorola, Inc. Semiconductor device and method of formation
US6355153B1 (en) * 1999-09-17 2002-03-12 Nutool, Inc. Chip interconnect and packaging deposition methods and structures
US6252290B1 (en) * 1999-10-25 2001-06-26 Chartered Semiconductor Manufacturing Ltd. Method to form, and structure of, a dual damascene interconnect device
US6458683B1 (en) * 2001-03-30 2002-10-01 Taiwan Semiconductor Manufacturing Co., Ltd Method for forming aluminum bumps by CVD and wet etch
KR100499557B1 (ko) * 2001-06-11 2005-07-07 주식회사 하이닉스반도체 반도체소자의 배선 형성방법
US6403461B1 (en) * 2001-07-25 2002-06-11 Chartered Semiconductor Manufacturing Ltd. Method to reduce capacitance between metal lines
US6717265B1 (en) * 2002-11-08 2004-04-06 Intel Corporation Treatment of low-k dielectric material for CMP
KR100583957B1 (ko) * 2003-12-03 2006-05-26 삼성전자주식회사 희생금속산화막을 채택하여 이중다마신 금속배선을형성하는 방법
US7207096B2 (en) 2004-01-22 2007-04-24 International Business Machines Corporation Method of manufacturing high performance copper inductors with bond pads
US6995084B2 (en) * 2004-03-17 2006-02-07 International Business Machines Corporation Method for forming robust solder interconnect structures by reducing effects of seed layer underetching
KR100819557B1 (ko) * 2006-08-17 2008-04-07 삼성전자주식회사 금속 식각용액, 이를 이용하는 금속 식각방법 및 이를이용하는 반도체 제품의 제조방법
US7582966B2 (en) * 2006-09-06 2009-09-01 Megica Corporation Semiconductor chip and method for fabricating the same
US7800239B2 (en) * 2007-12-14 2010-09-21 Semiconductor Components Industries, Llc Thick metal interconnect with metal pad caps at selective sites and process for making the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1431681A (zh) * 2002-01-03 2003-07-23 台湾积体电路制造股份有限公司 利用弹性体电镀掩模做为芯片级封装的方法
CN1630039A (zh) * 2003-11-18 2005-06-22 国际商业机器公司 选择性电镀半导体器件的输入/输出焊盘的方法

Also Published As

Publication number Publication date
TW200849433A (en) 2008-12-16
US20080284023A1 (en) 2008-11-20
KR20080101446A (ko) 2008-11-21
KR100871768B1 (ko) 2008-12-05
CN101308829A (zh) 2008-11-19

Similar Documents

Publication Publication Date Title
TWI387018B (zh) 具有焊墊之互聯結構及在焊墊上形成凸塊部位之方法
US8791567B2 (en) Semiconductor device
US8211789B2 (en) Manufacturing method of a bump structure having a reinforcement member
US8653648B2 (en) Zigzag pattern for TSV copper adhesion
JP2005217419A (ja) 高ｑファクタ（ｑ値）の集積回路インダクタ
JP2010093284A (ja) 半導体装置の製造方法
JP4493516B2 (ja) 半導体装置の製造方法
JP2010508673A (ja) 終端アルミニウム金属層のないメタライゼーション層積層体
CN108461407B (zh) 用于恶劣介质应用的键合焊盘保护
WO1999034415A1 (en) A single step electroplating process for interconnect via fill and metal line patterning
US20120211884A1 (en) Wafer chip scale package connection scheme
JP3459234B2 (ja) 半導体装置およびその製造方法
US7553743B2 (en) Wafer bonding method of system in package
CN110875424A (zh) 半导体装置结构的制造方法
US20170271432A1 (en) Inductor structure and manufacturing method thereof
CN101308829B (zh) 半导体器件和用于制造boac/coa的方法
KR100787371B1 (ko) 전극 및 반도체 장치 제조 방법
CN109887880B (zh) 一种半导体连接结构及其制作方法
CN100367464C (zh) 制造金属凸块的方法
US6261939B1 (en) Pad metallization over active circuitry
JP5891753B2 (ja) 半導体装置の製造方法
JP2012119444A (ja) 半導体装置
CN101241866B (zh) 具有加强物的凸块结构的制造方法
KR20110008474A (ko) 반도체 패키지 및 그의 제조방법
KR100599636B1 (ko) 무 도금선 패턴을 갖는 비오씨 반도체 패키지용인쇄회로기판의 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20100602

Termination date: 20120516