CN108461407B - 用于恶劣介质应用的键合焊盘保护 - Google Patents

用于恶劣介质应用的键合焊盘保护 Download PDF

Info

Publication number
CN108461407B
CN108461407B CN201810107192.4A CN201810107192A CN108461407B CN 108461407 B CN108461407 B CN 108461407B CN 201810107192 A CN201810107192 A CN 201810107192A CN 108461407 B CN108461407 B CN 108461407B
Authority
CN
China
Prior art keywords
layer
noble metal
passivation layer
contact
continuous portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810107192.4A
Other languages
English (en)
Other versions
CN108461407A (zh
Inventor
A·J·范德维尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Melexis Technologies NV
Original Assignee
Melexis Technologies NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Melexis Technologies NV filed Critical Melexis Technologies NV
Publication of CN108461407A publication Critical patent/CN108461407A/zh
Application granted granted Critical
Publication of CN108461407B publication Critical patent/CN108461407B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3171Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/7685Barrier, adhesion or liner layers the layer covering a conductive structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01LMEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L19/00Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
    • G01L19/0061Electrical connection means
    • G01L19/0069Electrical connection means from the sensor to its support
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01LMEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L19/00Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
    • G01L19/14Housings
    • G01L19/141Monolithic housings, e.g. molded or one-piece housings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H01L23/53252Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02125Reinforcing structures
    • H01L2224/02126Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/031Manufacture and pre-treatment of the bonding area preform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346Plating
    • H01L2224/03462Electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/0347Manufacturing methods using a lift-off mask
    • H01L2224/03472Profile of the lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/0347Manufacturing methods using a lift-off mask
    • H01L2224/03474Multilayer masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181Tantalum [Ta] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05669Platinum [Pt] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05681Tantalum [Ta] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明涉及用于制造半导体器件的方法并且涉及用于在恶劣介质中使用的相关半导体器件(1,2,3,4,5,6)。所述半导体器件包括:硅管芯(420),所述硅管芯包括金属接触区(422);以及至少一个钝化层(421),所述至少一个钝化层覆盖所述半导体管芯(420)并且被图案化从而形成通向所述半导体管芯(420)的所述金属接触区(422)的开口。所述器件还包括接触层(428,128,528)的连续部分(301),所述接触层包括耐火金属。这个连续部分(301)与所述至少一个钝化层(421)中的所述开口重叠并完全覆盖所述开口,在所述开口中与所述金属接触区(422)接触并且沿着所述连续部分(301)的整个边缘粘合至所述至少一个钝化层(421)。所述接触层包括至少粘合层和至少扩散阻挡层。所述器件进一步包括:贵金属层,布置在所述接触层的上方并完全覆盖所述连续部分(301),其中,所述贵金属层在所述连续部分(301)的整个边缘上方延伸从而粘合至围绕所述连续部分(301)的边缘所述至少一个钝化层(421)。

Description

用于恶劣介质应用的键合焊盘保护
技术领域
本发明涉及用于在恶劣介质应用中使用的集成半导体器件领域。更确切地,本发明涉及用于制造用于在恶劣介质中使用的集成电路半导体器件的方法以及相关半导体器件。
背景技术
标准的半导体器件可能不太适合(例如,可能不适合)用于恶劣介质条件下,例如暴露于硫酸或发烟硝酸或暴露于碘下。例如,当暴露于此类化学品下时,键合焊盘金属(比如铝或铜)可能例如由于氧化而腐蚀。本领域中已知的是由金保护层来覆盖键合焊盘。然而,在键合焊盘与金之间可能需要扩散阻挡物。例如,在没有扩散阻挡物的情况下,铝和金可以轻易且快速地扩散到彼此当中,这在高温应用中可能甚至更加成问题。在器件上提供具有金、钯或铂的保护性贵金属层允许针对恶劣介质条件保持所述器件中标准CMOS处理的优势,比如高效批量生产以及互连金属与硅中的集成电路之间的良好电接触。然而,在所述器件暴露于恶劣环境下时确保粘合层和扩散阻挡物的完整性仍然具有挑战性。
图1示出了如本领域中已知的用于恶劣介质的示例性集成电路半导体器件(例如,混合压力传感器)的横截面。在这种混合压力传感器中,可以使用键合接线136将传感器130电连接至CMOS接口芯片120。另一示例性键合接线126可以将CMOS接口芯片连接至衬底110,比如引线框或印刷电路板(PCB)。可以通过模具化合物140针对恶劣介质对线126、136加以保护。在模制的过程中,可以创建所述器件顶部上的腔体,在所述腔体中可以安装传感器130,例如,压力传感器。因而,可以将键合接线136设置在此腔体中从而将传感器键合焊盘132连接至CMOS接口芯片的键合焊盘122。
例如,本领域中已知的是在腔体中设置CMOS接口芯片的键合焊盘122,并由金层124覆盖此键合焊盘122的铝。同样的,可以由金层134覆盖传感器130的键合焊盘132。可替代地,如图2中所示,本领域中还已知的是由模具化合物140覆盖CMOS接口芯片的键合焊盘222。在此类现有技术器件中,覆盖CMOS键合焊盘222的金层224可以延伸至腔体中,从而充当键合焊盘222与抵抗恶劣环境的键合接线136之间的信号导体。这种类型的延伸在本领域中被称为键合焊盘的“重分布”。这具有以下优点:模具化合物保护从键合焊盘至重分布的接口。
本领域中已知的是,通过无电镀将金沉积至铝键合焊盘上,例如,首先在铝键合焊盘上生长一层镍,紧接着无电镀薄的金层。所述镍然后可以形成合适的扩散阻挡物。然而,虽然通过无电镀法而设置在键合焊盘上的所述层可以牢固地粘合至键合焊盘金属,但是在保护层与键合焊盘周围的钝化物之间未实现机械连接。这具有化学品(诸如可存在于恶劣介质中的前述化学品)可能穿透钝化物与所镀金属之间的界面并腐蚀键合焊盘金属的缺点。例如,金层与钝化物之间的机械和耐化学连接可能是非常有利的。
例如,EP 1947439描述了通过无电镀将金沉积在键合焊盘的TiW阻挡物上。EP1947439中所描述的方法可能具有诸如碘等恶劣介质仍然可以穿透钝化层与金之间并攻击TiW层的缺点。一旦TiW受到蚀刻,则铝将暴露于碘下并且可能非常快速地受到蚀刻。而且,由于硅衬底并非完全覆盖有钝化物,因此穿过界面还会发生电流腐蚀,例如由部分通过衬底的电子交换。
本领域中还已知的是通过电镀来沉积金。例如,可以在整个衬底上方沉积晶种层从而将电镀电流分布在衬底上方。这个晶种层保持在CMOS金属与被镀在晶种层顶部的层之间。所述晶种层一般充当粘合层、CMOS金属与被镀在顶部的金属之间的扩散阻挡物,并且在电镀过程中充当用于均匀电流分布的低电阻层。因此,经常首先溅射TiW、Ti或TiN以提供粘合层和阻挡层,紧接着溅射诸如金或铜等高导电层从而允许高电镀电流。所溅射的晶种层还可以有利地形成与氮化硅钝化物的牢固机械连接。这种强粘合可能是由于所溅射的金属原子撞击衬底所产生的动能。不幸的是,在使用贵金属时,有机模具材料可能不会很好地粘合至晶种层。本领域中还已知的是,在高导电贵金属层顶部溅射第二粘合层,从而确保镀层与模具的良好粘合。
然而,在将金电镀在键合焊盘上之后,需要将晶种层蚀刻掉以确保未保留不同结构之间的电连接,从而使得晶种层在金结构底部的边缘暴露于环境下,例如暴露于恶劣介质应用中的前述腐蚀性化学品下。已知的是,在蚀刻晶种层之后施加附加有机保护层以覆盖晶种层的被暴露边缘。然而,此类保护层可能具有与金的较差粘合性,并且腐蚀性化学品可能已经穿透保护层与黄金金属之间的界面。
利用金来覆盖键合焊盘的已知策略的另一缺点是:依赖标准CMOS钝化来保护互连,例如铝互连或铜互连。然而,这种钝化可能不足以阻挡前述腐蚀性化学品。例如,当覆盖互连的钝化层中仅存在一个较小缺陷(例如,小针孔)时,尤其是碘可能趋于完全地移除铝接线。为此原因,已知的是利用诸如聚酰亚胺等附加层来覆盖钝化物。这种额外钝化层可以被称为‘重钝化层’。这种重钝化层在具有开口的键合焊盘处可以是打开的,所述开口小于钝化键合焊盘开口。然后可以在此聚酰胺层的顶部溅射晶种层。
发明内容
本发明的实施例的目标是提供集成电路半导体器件的良好和高效制造,以便用于恶劣介质环境。
本发明的实施例的优点是:贵金属层防止了恶劣介质环境中的腐蚀性化学品接触半导体器件的内层,比如粘合层。
本发明的实施例的优点是:可以确保半导体器件的保护性贵金属层与钝化层之间的良好机械接触和良好机械连接。进一步的优点是:可以确保贵金属与围绕键合焊盘的钝化物的这种良好机械接触和连接。当保护性贵金属层还用于重新分布键合焊盘时,这可能特别有利。
本发明的实施例的进一步优点是:贵金属的良好机械连接可以防止恶劣环境使半导体器件的键合焊盘和/或互连恶化。
本发明的实施例的优点是:可以在贵金属与键合焊盘金属之间设置粘合层和阻挡层从而防止贵金属与键合焊盘的顶部金属之间生长金属间合金。
本发明的实施例的优点是:可以在贵金属与键合焊盘金属之间设置粘合层和阻挡层以确保对与半导体器件的电连接的良好机械阻力,例如对键合接线。
本发明的实施例的优点是:可以在贵金属与键合焊盘金属之间设置粘合层和阻挡层以确保在升高温度下的较高级别的可靠性,例如在150℃或175℃或更高的温度下,例如在1000小时或2000小时或更多的过程中。
本发明的实施例的优点是:实现了制造适于在恶劣介质应用中使用的半导体器件的成本有效的方法,例如,加工成本可能较低和/或可以在高容量下进行制造轮次。
本发明的实施例的优点是:半导体器件的表面(包括金属结构的边缘)可以高度抵抗恶劣介质。
通过根据本发明的方法和器件来完成上述目标。
在第一方面,本发明涉及一种用于制造用于在恶劣介质中使用的半导体器件的方法。所述方法包括:提供包括金属接触区的半导体管芯,由至少一个钝化层来覆盖所述半导体管芯,并且对所述至少一个钝化层进行图案化,从而形成开口以便暴露所述半导体管芯的所述金属接触区。所述方法此外包括:在暴露金属接触区上形成包括耐火金属的接触层,其中,所述接触层包括至少粘合层和至少扩散阻挡层。所述方法还包括:对所述接触层进行图案化,从而通过围绕所述接触层的连续部分的整个边缘暴露所述至少一个钝化层来在所述暴露金属接触区上方限定所述连续部分,其中,所述接触层的所述连续部分与所述至少一个钝化层中的所述开口重叠并完全覆盖所述开口。所述方法进一步包括:在所述接触层上方提供贵金属层,从而完全覆盖所述接触层的所述连续部分,其中,所述贵金属层还在所述接触层的所述连续部分的边缘上方延伸,从而粘合至围绕所述连续部分的边缘的被暴露的所述至少一个钝化层。所述提供所述贵金属层包括:在所述接触层的所述连续部分上并且在围绕所述连续部分的边缘的被暴露的所述至少一个钝化层上溅射所述贵金属,从而通过在所述溅射的贵金属与所述接触层之间并且在所述溅射的贵金属与所述至少一个钝化层之间进行原子键合来建立机械连接。
在根据本发明的实施例的方法中,所述对所述接触层进行图案化可以包括:对所述接触层进行图案化,从而使得所述接触层的所述连续部分在远离所述开口的方向上延伸,从而形成在所述金属接触区上方并远离所述金属接触区而延伸的重分布键合焊盘区域。
在根据本发明的实施例的方法中,所述溅射所述贵金属可以包括:溅射贵金属晶种层,以便在所述接触层的所述连续部分上并且在围绕所述连续部分的边缘的被暴露的所述至少一个钝化层上进行电镀,并且所述提供所述贵金属层可以包括将所述贵金属电镀至所述贵金属晶种层上。
在根据本发明的实施例的方法中,提供所述贵金属层可以包括:在所述贵金属晶种层上方形成电镀模具,并且电镀所述贵金属可以包括:将所述贵金属电镀至由所述电镀模具限定的模具开口内部的所述贵金属晶种层上。
在根据本发明的实施例的方法中,所述模具开口可以在平行于所述半导体管芯的平面内具有比所述接触层的所述连续部分的相应占用区更大的占用区。
在根据本发明的实施例的方法中,所述模具开口的圆周边缘可以在所述连续部分的占用区的外部并在沿着圆周边缘的每个点中与所述连续部分的占用区间隔开(即在连续部分的外部并与所述连续部分间隔开)至少预定的裕度。
在根据本发明的实施例的方法中,提供所述贵金属层可以包括:在电镀所述贵金属之后移除所述电镀模具。
在根据本发明的实施例的方法中,提供所述贵金属层可以包括:在所述贵金属晶种层和/或所述接触层未被所述经电镀的贵金属覆盖之处移除所述贵金属晶种层和/或所述接触层。
在根据本发明的实施例的方法中,提供所述贵金属层可以包括:创建剥离掩模,所述剥离掩模限定了围绕所述接触层的所述连续部分的壁,并且在所述连续部分上并且在围绕所述连续部分的边缘的被暴露的所述至少一个钝化层上溅射所述贵金属可以包括:将所述贵金属溅射穿过所述剥离掩模。
在根据本发明的实施例的方法中,所述剥离掩模在基底处的占用区可以大于所述接触层的所述连续部分的占用区,所述剥离掩模在所述基底处粘合至所述至少一个钝化层。
在根据本发明的实施例的方法中,所述剥离掩模可以包括下掩模层和上掩模层,由所述下掩模限定的开口大于由所述上掩模限定的开口,从而创建所述上掩模层的悬突部以便在溅射所述贵金属时形成周缘部。
在根据本发明的实施例的方法中,提供所述贵金属层可以包括:在溅射所述贵金属之前施加溅射蚀刻剂。
在根据本发明的实施例的方法中,提供所述贵金属层可以包括:在将所述贵金属溅射穿过所述剥离掩模之前,通过所述剥离掩模直接在所述接触层上并且直接在被暴露的所述至少一个钝化层上溅射粘合层,例如,间接地在所述接触层上并间接地在被暴露的所述至少一个钝化层上溅射所述贵金属,例如直接在所述粘合层上溅射所述贵金属。
在根据本发明的实施例的方法中,所述粘合层可以被溅射至在所述接触层的厚度的五十分之一至五分之一的范围内且在所述溅射的贵金属的厚度的五十分之一至十分之一的范围内的厚度。
在根据本发明的实施例的方法中,提供所述贵金属层可以包括:对所述溅射的贵金属进行热退火,以放松机械应力。
在根据本发明的实施例的方法中,由所述至少一个钝化层覆盖所述半导体管芯可以包括:在所述半导体管芯上提供第一钝化层或第一钝化层堆叠并且在所述第一钝化层上或所述第一钝化层堆叠上提供至少一个重钝化层;并且对所述至少一个钝化层进行图案化可以包括:对所述第一钝化层或所述第一钝化层堆叠和所述重钝化层两者都进行图案化,从而形成开口以便通过所述第一钝化层或所述第一钝化层堆叠并通过所述重钝化层暴露所述半导体管芯的所述金属接触区。
在根据本发明的实施例的方法中,对所述至少一个钝化层进行图案化可以包括:在所述第一钝化层中或所述第一钝化层堆叠中形成第一开口并且在所述重钝化层中形成第二开口,其中,所述第二开口小于所述第一开口。
在根据本发明的实施例的方法中,对所述至少一个钝化层进行图案化可以包括:在所述第一钝化层中或所述第一钝化层堆叠中形成第一开口并且在所述重钝化层中形成第二开口,其中,所述第二开口大于所述第一开口,例如,大于所述第一开口并且小于所述接触层的与所述开口重叠并完全覆盖所述开口的连续部分。
在根据本发明的实施例的方法中,形成所述接触层可以包括:将至少所述耐火金属溅射至所述暴露金属接触区上以及所述至少一个钝化层上。
在第二方面,本发明还涉及一种用于在恶劣介质中使用的半导体器件,所述半导体器件包括:硅管芯,包括金属接触区;以及至少一个钝化层,覆盖所述半导体管芯。对所述至少一个钝化层进行图案化从而形成通向所述半导体管芯的所述金属接触区的开口。所述器件包括接触层的连续部分,所述接触层包括耐火金属。例如,所述器件可以包括具有连续部分的接触层,其中,所述接触层以及因此其连续部分包括耐火金属。所述连续部分与所述至少一个钝化层中的所述开口重叠并完全覆盖所述开口,在所述开口中与所述金属接触区接触并沿着所述连续部分的整个边缘接触所述至少一个钝化层。所述接触层(例如,以及因此其连续部分)包括至少粘合层和至少扩散阻挡层。所述器件包括:贵金属层,布置在所述接触层的上方,所述贵金属层完全覆盖所述接触层的所述连续部分,其中,所述贵金属层在所述接触层的所述连续部分的整个边缘上方延伸从而粘合至围绕所述连续部分的边缘的所述至少一个钝化层。
在根据本发明的实施例的半导体器件中,所述贵金属层可以包括围绕其整个圆周的朝向所述至少一个钝化层逐渐变窄的倾斜边缘,所述贵金属层在所述倾斜边缘处粘合至围绕所述连续部分的边缘的所述至少一个钝化层。
在根据本发明的实施例的半导体器件中,所述倾斜边缘可以相对于垂线以在1°至20°范围内的角度逐渐变窄,例如,所述锥度可以小于20°。
在所附独立权利要求和从属权利要求中陈列了本发明的具体和优选方面。来自从属权利要求的特征可以与独立权利要求的特征组合并且可以酌情并且并不仅仅如权利要求书中清楚陈列地与其他从属权利要求的特征组合。
本发明的这些和其他方面将从下文所描述的(多个)实施例清楚或将参照下文所描述的(多个)实施例对其进行阐述。
附图说明
图1示出了如本领域中已知的用于在恶劣介质中使用的示例性集成电路半导体器件。
图2示出了如本领域中已知的使用键合焊盘重分布的、用于在恶劣介质中使用的示例性集成电路半导体器件。
图3展示了根据本发明的实施例的方法中的以下步骤:由至少一个钝化层来覆盖半导体管芯并且对所述至少一个钝化层进行图案化从而形成暴露所述半导体管芯的金属接触区的开口。
图4展示了根据本发明的实施例的方法中的对所述接触层进行图案化的步骤。
图5展示了根据本发明的实施例的方法的第一示例性过程流中的以下步骤:提供溅射贵金属晶种层以便电镀。
图6展示了根据本发明的实施例的方法的第一示例性过程流中的以下步骤:在所述溅射的贵金属晶种层上方形成电镀模具并且在所述电镀模具内部电镀贵金属。
图7展示了根据本发明的实施例的方法的第一示例性过程流中的以下步骤:在电镀所述贵金属之后移除所述电镀模具。
图8示出了根据本发明的实施例的第一示例性器件。
图9展示了根据本发明的实施例的第二示例性器件,其中,所述接触层被图案化以使得所述接触层的连续部分在远离所述开口的方向上延伸从而形成重分布键合焊盘区域,所述接触层的所述连续部分与所述至少一个钝化层中的所述开口重叠并完全覆盖所述开口。
图10出于比较性目的而示出了与图9中所示的类似器件,所述器件可以通过并非依据本发明的实施例的方式来获得。
图11展示了根据本发明的实施例的第三示例性器件。
图12展示了根据本发明的实施例的第四示例性器件,其中,所述至少一个钝化层另外包括重钝化层。
图13展示了根据本发明的实施例的方法中的对所述接触层进行图案化的步骤。
图14展示了根据本发明的实施例的方法的第二示例性过程流中的以下步骤:创建剥离掩模并且将所述贵金属溅射穿过所述剥离掩模。
图15展示了根据本发明的实施例的第五示例性器件。
图16展示了根据本发明的实施例的第六示例性器件。
所述附图仅为示意性的并且是非限制性的。在附图中,出于示意性目的,所述元件中的一些的大小可能被夸大并且未按比例绘制。
权利要求书中的任何参考标记不应该被解释为限制范围。
在不同的附图中,相同的参考标记指代相同或相似的元件。
具体实施方式
将相对于具体实施例并参照某些附图对本发明进行描述,但本发明不限于此而仅受权利要求书的限制。所描述的附图仅为示意性的并且是非限制性的。在附图中,出于示意性目的,所述元件中的一些的大小可能被夸大并且未按比例绘制。尺寸和相对尺寸不对应于用于实践本发明的实际简化。
此外,说明书中和权利要求书中的术语“第一”、“第二”等用于在类似元件之间进行区分并且不一定用于描述顺序,无论是时序上、空间上、排序上还是以任何其他方式。要理解的是,这样使用的术语在适当的情况下是可互换的并且在此所描述的本发明的实施例与在此所描述或展示的相比能够以其他顺序运转。
而且,说明书和权利要求书中的术语“顶部”、“下方”等用于说明性目的并且不一定用于描述相对位置。要理解的是,这样使用的术语在适当的情况下是可互换的并且在此所描述的本发明的实施例与在此所描述或展示的相比能够以其他取向运转。
要注意的是,权利要求书中所使用的术语“包括”不应该被解释为限于其后所列出的装置;它不排除其他元件或步骤。因而,它将被解释为限定如提到的所阐明的特征、整体、步骤或部件的存在,但不排除一个或多个其他特征、整体、步骤或部件、或其组的存在或添加。因而,表达“包括装置A和B的设备”的范围不应该限于仅由部件A和B组成的设备。这意味着,相对于本发明,设备的仅有的相关部件是A和B。
贯穿本说明书提到“一个实施例”或“实施例”指结合该实施例所述的具体特征、结构或特性包含在本发明的至少一个实施例中。因而,短语“在一个实施例中”或“在实施例中”在贯穿本说明书中各地方的出现不一定、但可以全都指相同的实施例。此外,在一个实施例中,可以通过任何适当的方式组合具体的特征、结构、或特性,如从本公开中将对本领域技术人员明显的。
类似地,应该理解的是,在本发明的示例性实施例的描述中,有时在单个实施例、附图、或其描述中将本发明的各个特征聚集在一起以用于使本公开合理化并帮助理解各发明方面中的一个或多个方面。然而,本公开的方法并不被解释为反映以下意图:所要求保护的发明需要比每项权利要求中明确表述的特征更多的特征。而是被解释为:所附权利要求书反映了发明方面在于比单个前述公开的实施例的全部特征少。因此,据此将详细说明所附权利要求书清楚地结合到具体实施方式中,每一项权利要求独立地代表本发明的单独实施例。
此外,虽然在此所述的一些实施例包括其他实施例中所包括的一些而非其他特征,不同实施例的特征的组合旨在在本发明的范围内,并形成不同实施例,如本领域技术人员将理解的。例如,在所附权利要求书中,要求保护的实施例中的任一个实施例可以以任何组合使用。
在本文所提供的描述中,陈述了众多具体细节。然而,要理解的是,可以在不具有这些特定的细节的情况下实践本发明的实施例。在其他情况下,未详细示出公知的方法、结构和技术,以避免模糊对本说明书的理解。
在第一方面,本发明涉及一种用于制造用于在恶劣介质中使用的半导体器件的方法。所述方法包括:提供包括金属接触区的半导体管芯。
所述方法进一步包括:由至少一个钝化层覆盖所述半导体管芯,并且对所述至少一个钝化层进行图案化,从而形成开口以便暴露所述半导体管芯的所述金属接触区。
所述方法进一步包括:在所述金属接触区上形成接触层,其中,所述接触层包括耐火金属。所述接触层包括至少粘合层和至少扩散阻挡层。
所述方法还包括:对所述接触层进行图案化,从而使得通过围绕所述连续部分的整个边缘暴露所述至少一个钝化层来在所述暴露金属接触区上方限定所述连续部分,其中,所述接触层的这个连续部分与所述至少一个钝化层中的所述开口重叠并完全覆盖所述开口。
所述方法进一步包括:在所述接触层上方提供贵金属层,从而完全覆盖所述接触层的所述连续部分,其中,所述贵金属层还在所述接触层的所述连续部分的边缘上方延伸,从而接触围绕所述连续部分的边缘的被暴露的所述至少一个钝化层。
提供所述贵金属层的这个步骤包括以下步骤:将所述贵金属溅射至所述接触层的所述连续部分上和围绕所述连续部分的边缘的被暴露的所述至少一个钝化层上,从而通过在所述溅射的贵金属层与所述接触层和所述至少一个钝化层两者之间进行原子键合来建立机械连接。
溅射所述贵金属可以包括:溅射贵金属晶种层。可以溅射这个贵金属晶种层从而提供至所述接触层的与所述开口重叠并完全覆盖所述开口的所述连续部分的边缘的良好机械连接以及与所述被暴露钝化层的良好机械连接。
所述贵金属层可以包括抵抗腐蚀和氧化的金属或金属组合,比如合金。具体地,所述贵金属层可以包括金、银、钯和/或铂。所述贵金属层还可以包括钽,例如用于提供良好的粘合。
例如,所述贵金属层可以包括一层钽(例如,薄层的钽)与一层金、银、铂、钯或其金属合金的堆叠。所述薄层的钽可以形成粘合层,从而保证贵金属与钝化物(例如,与(多个)(重)钝化层)的良好粘合。
所述方法可以进一步包括:在晶种层上方形成电镀模具,从而限定模具开口。这个模具开口可以在平行于所述衬底的平面内具有比所述接触层的所述连续部分更大的占用区,所述接触层的所述连续部分与所述至少一个钝化层中的所述开口重叠并完全覆盖所述开口。
所述方法可以进一步包括:在由所述电镀模具限定的模具开口中电镀贵金属。所述方法还可以包括:在电镀所述贵金属之后移除所述电镀模具。
所述方法还可以包括:在所述贵金属晶种层未被所述经电镀的贵金属覆盖之处移除所述贵金属晶种层。而且,还可以在所述接触层未被所述经电镀的贵金属覆盖之处移除所述接触层。
可替代地,提供所述贵金属层可以包括:创建剥离掩模,所述剥离掩模限定了围绕所述接触层的所述连续部分的壁。在所述连续部分上并且在围绕所述连续部分的边缘的被暴露的所述至少一个钝化层上溅射所述贵金属可以包括:将所述贵金属溅射穿过这个剥离掩模。所述剥离掩模在其基底处的占用区可以大于所述接触层的所述连续部分的占用区,所述剥离掩模在所述基底处接触所述至少一个钝化层。
参照图3,根据本发明的实施例的一种方法包括:提供半导体管芯420,所述半导体管芯包括例如与键合焊盘相对应的金属接触区422。例如,所述金属接触区可以对应于在所述半导体管芯中形成的集成电路的键合焊盘。
例如,所述半导体器件可以包括有待互连的多个组成半导体器件,例如,在混合传感器设备中例如通过连接所述组成半导体器件的相应键合焊盘的键合接线。
所述方法进一步包括:由至少一个钝化层421来覆盖所述半导体管芯,并且对所述至少一个钝化层421进行图案化,从而形成开口以便暴露所述半导体管芯的金属接触区422,例如,从而暴露半导体管芯中的集成电路的键合焊盘。
所述对所述至少一个钝化层进行图案化可以包括:将所述开口(例如,接触孔)蚀刻穿过所述至少一个钝化层,从而暴露金属接触区422。
所述至少一个钝化层可以例如包括二氧化硅层和/或氮化硅层。
例如,如图12中所展示的,所述至少一个钝化层可以包括半导体管芯上的第一钝化层122或第一钝化层堆叠、以及所述第一钝化层122上或所述第一钝化层堆叠上的至少一个重钝化层123。换言之,由所述至少一个钝化层覆盖所述半导体管芯可以包括:在钝化层上(例如,直接在钝化层上方并与钝化层接触)沉积重钝化层,比如聚酰亚胺层。同样,对所述至少一个钝化层进行图案化可以包括:对所述钝化层和所述重钝化层两者进行图案化,从而形成开口以便通过所述(多个)钝化层和所述(多个)重钝化层暴露所述半导体管芯的所述金属接触区。例如,可以将第一钝化层或第一钝化层堆叠中的开口与所述至少一个重钝化层中的开口进行对准,例如以公共几何中心为中心,从而暴露金属接触区。这种(此类)重钝化层的优点是:通过附加的重钝化物可以进一步改进钝化物的化学耐性和机械鲁棒性。
所述重钝化物中的暴露所述金属接触区的开口可以小于(多个)第一钝化层中的开口。这具有的优点是:聚酰亚胺可以充当(对大型热膨胀敏感的)所电镀的贵金属424与芯片的钝化物(例如,氮化钝化物)之间的弹性缓冲。然而,如果不能确认恶劣环境中的化学活性原子或分子不能扩散穿过重钝化物(例如,聚酰亚胺)到达键合焊盘金属,则可以优选的是使重钝化层中的开口大于(多个)第一钝化层中的开口但仍小于之后所沉积的贵金属层的占用区。
根据本发明的实施例的方法进一步包括:在暴露金属接触区上(例如,在被钝化层中的开口所暴露的金属接触区上、或者在被钝化层和重钝化层中的已对准开口所暴露的金属接触区上)形成包括耐火金属的接触层428。例如,可以在暴露金属接触区上形成接触层,从而直接物理地接触暴露金属接触区。
接触层428包括至少粘合层和至少阻挡层。例如,所述接触层可以被称为粘合层/阻挡层,例如,被称为被适配用于提供粘合功能以及扩散阻挡功能的一层或多层。
形成接触层428可以包括:将至少所述耐火金属溅射至所述暴露金属接触区上以及所述至少一个钝化层上。
例如,可以通过溅射标准CMOS加工中所使用的耐火金属比如W、Ti、TiW、TiN、Co、Ni、Mo、Ta和/或Pd来提供接触层。形成接触层428因而可以包括溅射多层的粘合层/阻挡层。
例如,提供所述接触层可以包括:溅射一层钛(Ti),例如,其可以提供良好的粘合。例如,提供接触层可以包括利用不同的金属进行溅射从而获得粘合层和扩散阻挡物的堆叠。例如,在钛溅射工艺的第二半过程中,通过添加氮等离子,可以在钛(Ti)粘合层的顶部提供氮化钛(TiN)扩散阻挡物。
参照图4,根据本发明的实施例的方法进一步包括:对接触层428进行图案化(例如,通过应用光刻技术),从而通过围绕所述接触层的连续部分的整个边缘暴露所述至少一个钝化层421来在所述暴露金属接触区422上方限定所述连续部分301,其中,所述接触层的所述连续部分301与所述至少一个钝化层中的所述开口重叠并完全覆盖所述开口,例如,通过(多个)钝化层、或通过(多个)钝化和重钝化层暴露金属接触区422的开口。这个连续部分301可以与接触层428的任何其他部分断开连接,如果这样的话,其他部分保持,例如,通过所述至少一个钝化层421围绕所述连续部分的整个边缘而被暴露处的接触层的已移除材料。
换言之,可以对接触层428(例如,粘合层/阻挡层)进行图案化,其方式为使得,限定并隔离接触层中的结构,其中,这个结构完全覆盖开口(例如,覆盖由所述开口形成的凹度的内壁),并从所述开口的边缘向外延伸,例如,从而使得这个结构在平行于衬底的平面内具有比所述开口的相应占用区更大的占用区。
例如,围绕所述连续部分的整个边缘而暴露所述至少一个钝化层421可以包括:将接触层的围绕所述开口形成封闭轮廓的部分302移除(例如,蚀刻掉)。这个部分302可以在沿其整个圆周的每个点处与开口的边缘间隔开。因而可以对接触层428进行图案化,从而使得在所述方法的随后步骤中将限定贵金属的边缘之处移除接触层428。
围绕开口形成封闭轮廓的部分302(例如,接触层下方的所述至少一个钝化层421被局部暴露之处)沿其整个圆周可以具有至少0.5μm(例如,在0.5μm至5μm的范围内)的宽度(例如,轮廓线宽度)。
对所述接触层进行图案化可以包括:在所述接触层中在连续部分301外部的区域中限定狭缝,例如在通过围绕所述开口形成封闭轮廓的已移除部分302而与连续部分301间隔开的区域中,例如从而使能在开口上方限定连续部分的区域外部的例如贵金属晶种层429的所述溅射的贵金属的良好粘合。
而且,如图9中所展示的,图案化的步骤还可以包括:对接触层128进行图案化以使得所述接触层的连续部分在远离所述开口的方向上延伸从而形成在金属接触区422上方并远离所述金属接触区而延伸的重分布键合焊盘区域150,所述接触层的所述连续部分与所述至少一个钝化层中的所述开口重叠并完全覆盖所述开口。
所述方法进一步包括:在接触层428上方提供贵金属,从而完全覆盖接触层的所述连续部分301。所述贵金属在所述接触层的连续部分的边缘上方延伸从而接触围绕所述连续部分的边缘的被暴露的所述至少一个钝化层,例如在整个边缘上方延伸,例如在沿着整个边缘的圆周的每个点中。
提供所述贵金属包括:将所述贵金属溅射至所述接触层的连续部分301上和围绕所述连续部分的边缘的被暴露的所述至少一个钝化层上,从而通过在所述溅射的贵金属与所述接触层之间并且在所述溅射的贵金属与所述至少一个钝化层之间进行原子键合来建立机械连接。
这种溅射的贵金属层的优点是:可以在贵金属与接触层428的顶表面和侧壁(例如,由连续部分301所形成的顶表面和侧壁)之间实现非常好的粘合。进一步的优点是:在贵金属与钝化层421之间同样实现了良好粘合,例如,其中,将接触层的部分302移除以限定连续部分301。溅射的优点是:贵金属原子以足够高以形成良好键合的动能轰击接触层和所述至少一个钝化层。
因而,可以确保贵金属与同覆盖并环绕所述开口的接触层的结构相邻的钝化物之间的良好机械粘合,从而使得侵略性介质无法到达在接触层中限定的这个结构,例如,无法到达扩散阻挡层/粘合层。
图5至图8展示了根据本发明的实施例的方法的第一示例性过程流的进一步步骤。在这个第一示例性过程流中,可以通过电镀在用于恶劣介质中的半导体器件中实现保护性贵金属层。
参照图5,在根据本发明的实施例的方法中,溅射所述贵金属可以包括:溅射贵金属晶种层429以用于电镀,例如具有低电阻的一层贵金属以便适合作为晶种层而用于电镀贵金属。溅射这个贵金属晶种层429从而提供与接触层428的所述开口重叠并完全覆盖所述开口的连续部分301的边缘的良好机械连接以及与所述被暴露钝化层的机械连接。
所沉积的贵金属晶种层429可以具有在20nm至500nm范围内的厚度,例如,在40nm至300nm范围内,例如,在50nm至200nm范围内。
根据本发明的实施例的方法还可以包括:在贵金属晶种层429的顶部沉积临时粘合层431(例如,再次通过溅射),从而确保电镀模具433的良好粘合。例如,这个临时粘合层可以包括任何合适的材料,例如,不一定是贵金属。
参照图6,所述方法可以进一步包括:在晶种层上方形成电镀模具433,例如在贵金属晶种层429上或直接与所述贵金属晶种层接触、或可替代地在临时粘合层431上或直接与所述临时粘合层接触。所述电镀模具可以限定模具开口。例如,这个电镀模具433可以包括由掩模材料(例如,抗蚀剂材料)形成的模具壁。
由电镀模具433所限定的这个模具开口在平行于所述衬底的平面内的占用区可以大于接触层428的连续部分301,所述接触层的所述连续部分与所述至少一个钝化层中的所述开口重叠并完全覆盖所述开口。例如,模具开口的边缘可以与连续部分301的边缘间隔一定的间隙,例如,较小间隙,例如在0.5μm至5μm范围内的间隙,例如在围绕连续部分301的圆周的每个点中。
所述方法可以进一步包括:在临时粘合层431未被电镀模具433覆盖之处移除所述临时粘合层,例如,以便暴露模具开口内部(例如,电镀模具所限定的电镀体积的内部)的贵金属晶种层429。
所述方法可以进一步包括:在电镀模具的内部电镀贵金属424,例如,在模具开口的内部,例如在模具壁所限定的腔体内部。例如,可以将贵金属424电镀至0.25μm至40μm范围内的厚度。
参照图7,所述方法还可以包括:在电镀贵金属424之后,将电镀模具433移除,例如,将形成模具开口的壁的掩模材料移除。
所述方法还可以包括:将临时粘合层431移除,例如,通过应用溶剂和/或蚀刻溶液。
参照图8,所述方法还可以包括:在贵金属晶种层429未被经电镀的贵金属424覆盖之处移除所述贵金属晶种层。而且,还可以在接触层428未被经电镀的贵金属424覆盖之处移除所述接触层。
这种在贵金属晶种层429和接触层428未被经电镀的贵金属424覆盖之处移除贵金属晶种层和接触层可以包括选择性蚀刻和/或溅射蚀刻。例如,可以将经电镀的贵金属424的体积从原始电镀体积435降至图8中所描绘的体积。优点是:通过这种蚀刻,由贵金属晶种层429的残余形成的倾斜侧壁可以形成于经电镀的贵金属424的基底处,在此处,所述基底与所述至少一个钝化层421接触。
电镀模具433的模具开口在平行于所述半导体管芯的平面内的占用区可以大于所述接触层的所述连续部分的相应占用区,从而使得所述模具开口的圆周边缘在所述连续部分的所述占用区的外部并且在沿着所述圆周边缘的每个点中与所述连续部分的所述占用区间隔开至少预定的裕度。
优选地,这个预定裕度的宽度(例如,上文所提及的间隙)可以至少是(例如,大于或等于)当在贵金属晶种层429未被经电镀的贵金属424覆盖之处移除所述贵金属晶种层时用于蚀刻贵金属晶种层429的蚀刻深度的二倍。
例如,当蚀刻贵金属晶种层429时,经电镀的贵金属424还可能在体积上减小,如上文所描述的。因此,通过对电镀模具进行适当的尺寸调整,经电镀的贵金属424可以在接触层的连续部分上方延伸并越过所述接触层的所述连续部分大于被蚀刻掉的材料的厚度,例如,以便确保经电镀的贵金属的适当层依然覆盖并保护接触层的连续部分。因而,可以由通过根据本发明的实施例的方法而获得的器件中的贵金属将金属接触区422上的接触层428结构完全覆盖并因而保护其免于恶劣介质,所述结构提供粘合并充当扩散阻挡物。而且,可以获得贵金属与相邻于接触层的钝化层的良好粘合。例如,可以注意到的是,已经观察到,无电镀不提供所沉积的金属与钝化物之间的这种粘合。
参照图9,如果在根据本发明的实施例的方法中在对接触层128进行图案化时形成了重分布键合焊盘区域150,则可以由将经电镀的贵金属424连接到所述至少一个钝化层421以及接触层128的经溅射的贵金属晶种层429来确立良好的机械强度。覆盖开口的接触层结构和重分布键合焊盘区域150的边缘同样有利地由贵金属晶种层的经溅射的贵金属所覆盖。可以由贵金属与钝化物的经溅射连接的强度来提供化学耐性。由于溅射,这种连接可能足够强以确保恶劣介质无法穿透这种金与钝化物之间。
参照图10,在提供用于比较的替代性方法中,可以通过延伸由电镀模具限定的模具开口来形成重分布键合焊盘区域150,例如,在所述区域处,在沉积和图案化钝化层121之前沉积和图案化接触层228。所以,贵金属晶种层将提供键合焊盘区域150与钝化物121之间的机械连接。然而,这种连接与图9中所示的器件相比可能具有有限的强度,其中,粘合通过充当专用粘合层的接触层来确保。因此,当贵金属与钝化物之间的界面受到机械应力时(例如在以超声键合力进行接线键合的过程中或者在通过诸如模具化合物等材料封装在封装体中时),图10中所示的比较性结构的键合强度可能不足。
参照图11,示出了如可以通过根据本发明的实施例的方法制造的半导体器件。所述半导体器件可以包括有待互连的多个组成半导体器件,例如通过连接所述组成半导体器件的相应接触焊盘的键合接线。图12中示出了相似的器件,其中,包括了重钝化层。
图13至图16展示了根据本发明的实施例的方法的第二示例性过程流的进一步步骤。在这个第二示例性过程流中,可以通过剥离工艺在用于在恶劣介质中使用的半导体器件中实现保护性贵金属层。
例如,如上文参照图3所解释的,所述方法包括:提供包括金属接触区422的半导体管芯420,由至少一个钝化层421来覆盖半导体管芯420,并且对所述至少一个钝化层421进行图案化,从而形成开口以便暴露半导体管芯420的所述金属接触区422。所述至少一个钝化层还可以包括重钝化层,例如,如上文所描述的。
所述方法进一步包括:在暴露金属接触区422上形成包括耐火金属的接触层528(例如,通过溅射),其中,所述接触层包括至少粘合层和至少扩散阻挡层。通过上文参照接触层428所提供的描述,与形成这种接触层528有关的示例性特征将是清楚的。
参照图13,根据本发明的实施例的方法进一步包括:对接触层528进行图案化(例如,通过应用光刻技术),从而通过围绕所述接触层的连续部分的整个边缘暴露所述至少一个钝化层421来在所述暴露金属接触区422上方限定所述连续部分301,其中,所述接触层的所述连续部分301与所述至少一个钝化层中的所述开口重叠并完全覆盖所述开口,例如,通过(多个)钝化层、或通过(多个)钝化和重钝化层暴露金属接触区422的开口。
对接触层528进行图案化可以包括:将接触层528的在连续部分301外部的剩余部分移除,例如,从而使得没有保留接触层528的其他部分。然而,在本发明的实施例中,其中,可以通过剥离工艺在用于在恶劣介质中使用的半导体器件中实现保护性贵金属层,比如由第二示例性过程流所展示的,可以通过移除(例如,蚀刻掉)接触层的围绕开口形成闭合轮廓的部分302将接触层同等地图案化,例如,如图4中所展示的。而且,如图16中所示的被制造的设备所展示的,图案化的步骤还可以包括:对接触层128进行图案化以使得所述接触层的连续部分在远离所述开口的方向上延伸从而形成在金属接触区422上方并远离所述金属接触区而延伸的重分布键合焊盘区域150,所述接触层的所述连续部分与所述至少一个钝化层中的所述开口重叠并完全覆盖所述开口。
参照图14,所述方法进一步包括:在接触层528上方提供贵金属层,从而完全覆盖接触层的所述连续部分301。所述贵金属在所述接触层的连续部分的边缘上方延伸从而接触围绕所述连续部分的边缘的被暴露的所述至少一个钝化层,例如在整个边缘上方延伸,例如在沿着整个边缘的圆周的每个点中。
在根据本发明的实施例的方法中,提供所述贵金属可以包括创建剥离掩模。所述剥离掩模可以限定围绕接触层的连续部分301的壁。因此,所述剥离掩模在平行于所述衬底的平面内、在其基底处可以具有大于接触层428的连续部分301的占用区,所述剥离掩模在所述基底处接触所述至少一个钝化层421,所述接触层的所述连续部分与所述至少一个钝化层中的所述开口重叠并完全覆盖所述开口。例如,所述剥离掩模在其基底处的边缘可以与连续部分301的边缘间隔一定的间隙,例如,较小间隙,例如在0.5μm至5μm范围内的间隙,例如在围绕连续部分301的圆周的每个点中。
所述剥离掩模可以包括下掩模层535和上掩模层533。下掩模535中的开口可以大于上掩模533中的开口,从而使得创建了上掩模层533的悬突部w。而且,下掩模层535可以具有厚度h,从而使得与下掩模535的基底间隔距离h的悬突部w在通过其来沉积贵金属的溅射工艺中创建周缘部。这种阴影效果可以足够大,例如,通过适当地选择厚度h和悬突部w,从而防止下掩模层535的侧壁在溅射工艺的过程中被贵金属覆盖。这个下侧壁可以优选地免于经溅射的金属,从而允许剥离溶液与掩模材料进行反应。
可以通过厚度h与被溅射穿过剥离掩模开口的金属的最终金属厚度之比来确定晶片上的所溅射层的斜率。
提供所述贵金属可以包括在溅射工艺之前施加溅射蚀刻剂。在这种溅射蚀刻过程中,具有高能量的原子可以从有待溅射到的表面移除薄层,从而移除天然氧化物,并使表面极化。
提供贵金属可以包括:直接在接触层528上并直接在被暴露的所述至少一个钝化层421上溅射粘合层529。可以通过剥离掩模来进行这种溅射。例如,可以将这种粘合层529溅射至2nm至20nm范围内的厚度。溅射穿过剥离掩模的这种掩模开口是特别有利的,因为它允许在良好限定区内进行溅射的过程中递增地沉积所溅射的材料。因此,不需要对所溅射的材料进行图案化的进一步步骤,这可能以其他方式形成会受到恶劣环境中的腐蚀性化学品攻击的边缘。而且,沉积材料的边缘由于通过溅射穿过掩模导致的材料堆积而可能有利地倾斜,从而使得当通过剥离掩模溅射多个层和/或多种材料时,每个之前沉积的层被完全覆盖(包括其侧壁)并因此受到随后沉积的(多个)层的保护。而且,由于溅射工艺而最终产生的锥形边缘可以防止机械力(比如由振动所引起的)沿着边缘作用于竖直侧壁,这会在基底的由于杠杆效应而机械地接触(重)钝化物之处产生缺陷,因而潜在地允许腐蚀性化学品到达(重)钝化物。
提供所述贵金属包括:将所述贵金属溅射至接触层528的连续部分301上和围绕所述连续部分的边缘的被暴露的所述至少一个钝化层上,从而通过在所述溅射的贵金属与所述接触层之间并且在所述溅射的贵金属与所述至少一个钝化层之间进行原子键合来建立机械连接。
溅射所述贵金属可以进一步包括:将贵金属524溅射穿过所述剥离掩模,例如在溅射粘合层529之后,例如同时在溅射粘合层529与溅射贵金属524之间维持剥离掩模上方的真空。例如,可以在溅射粘合层529之后溅射所述贵金属,而不会将晶片暴露于氧气或氮气下,从而防止形成天然氧化物或氮化物。
可以例如将所述贵金属溅射至50nm至500nm范围内的厚度。所述贵金属的厚度优选地小于1000nm(例如,在50nm至500nm的范围内),从而允许易于实施所述剥离工艺并将成本保持在合理限制内。所述贵金属的厚度优选地大于50nm,例如在100nm至500nm的范围内,例如在150nm至350nm的范围内,比如200nm,从而提供足够的材料来建立可靠的接线键合。
可以将所述贵金属溅射到至少与所述接触层(例如,与扩散阻挡层)相同的厚度。例如,由接触层提供的扩散阻挡物可以至少是100nm厚,并且还可以将贵金属溅射到至少100nm的厚度。
可以将贵金属524溅射至是粘合层529厚度的10倍至50倍范围内的厚度,例如从而使得薄粘合层被贵金属充分地覆盖并且未暴露于恶劣环境下。
例如,粘合层529可以是具有约5nm厚度的钽层,并且贵金属524可以由溅射至约200nm厚度的铂组成。这种组合可以提供用于接线键合的特别好的粘合质量以及对恶劣介质的良好抵抗力。
这种溅射的贵金属层的优点是:可以在贵金属与接触层528的顶表面和侧壁(例如,由连续部分301所形成的顶表面和侧壁)之间实现非常好的粘合。进一步的优点是:在贵金属与钝化层421之间同样实现了良好粘合,例如,其中,将接触层的部分302移除以限定连续部分301。溅射的优点是:贵金属原子以足够高以形成良好键合的动能轰击接触层和所述至少一个钝化层。
因而,可以确保贵金属与同覆盖并环绕所述开口的接触层的结构相邻的钝化物之间的良好机械粘合,从而使得侵略性介质无法到达在接触层中限定的这个结构,例如,无法到达扩散阻挡层/粘合层。
剥离工艺可以有利地提供对粘合层529的良好封装。例如,当在所述至少一个钝化层421与贵金属524之间溅射粘合层529时,在粘合层和贵金属层的堆叠上使用蚀刻掩模将在边缘底部产生粘合层的被暴露边缘。然而,通过作为剥离工艺的一部分溅射所述堆叠,粘合层可以被贵金属完全覆盖,包括粘合层的侧壁。例如,粘合层的边缘可以完全被贵金属覆盖,因为与之前溅射穿过的粘合金属相比,可以将实质上更多的贵金属溅射穿过同一剥离掩模开口。
参照图15,在溅射贵金属524之后,可以例如使用剥离溶液来移除剥离掩模(例如,下掩模层535和上掩模层533)。
而且,根据本发明的实施例的方法可以包括:对所述溅射的层进行热退火以放松所述溅射的层中的应力,例如以在200℃至600℃范围内的温度。在金属溅射的过程中,所溅射的原子的动能可以如此高以至于原子渗透到它们被溅射到的表面上并在横向方向上推动周围的原子。虽然这可以有利地实现良好粘合,但是这也会导致压缩应力。通过以给原子足够的热能来重新安置的温度来加热晶片,可以放松这个应力。
在第二方面,本发明还涉及一种用于在恶劣介质中使用的半导体器件。
参照图8、图9、图11、图12、图15和图16,示出了根据本发明的实施例的用于在恶劣介质中使用的各示例性半导体器件1、2、3、4、5、6。
这些半导体器件包括硅管芯420,所述硅管芯包括金属接触区422,例如键合焊盘区。
所述半导体器件还包括至少一个钝化层421,所述至少一个钝化层覆盖所述半导体管芯420并且被图案化从而形成通向所述半导体管芯420的所述金属接触区422的开口。
参照图12,所述至少一个钝化层可以包括:半导体管芯420上的第一钝化层122或第一钝化层堆叠、以及所述第一钝化层122上或第一钝化层堆叠上的至少一个重钝化层123。可以对第一钝化层(或第一钝化层堆叠)和重钝化层两者进行图案化,从而形成通向半导体管芯的金属接触区422的开口,例如延伸穿过第一钝化层(或第一钝化层堆叠)并穿过重钝化层的开口。而且,可以提供第一钝化层122中(或所述第一钝化层堆叠中)的第一开口和重钝化层123中的第二开口,其中,所述第二开口小于所述第一开口。
半导体器件1、2、3、4、5、6进一步包括接触层428、128、528的连续部分301,所述接触层包括耐火金属。所述接触层包括至少粘合层和至少扩散阻挡层。
这个连续部分301与所述至少一个钝化层421中的所述开口重叠并完全覆盖所述开口,在所述开口中与所述金属接触区422接触并沿着所述连续部分301的整个边缘接触所述至少一个钝化层421。
根据本发明的实施例的半导体器件1、2、3、4、5、6包括布置在接触层上方的贵金属层。所述贵金属层完全覆盖所述接触层的连续部分301。所述贵金属层还在接触层的连续部分301的整个边缘上方延伸,从而接触围绕连续部分301的边缘的所述至少一个钝化层421。
所述贵金属层可以包括围绕其整个圆周的朝向所述至少一个钝化层421逐渐变窄的倾斜边缘,所述贵金属层在倾斜边缘处接触围绕所述连续部分301的边缘的至少一个钝化层421。
参照图11和图12,半导体器件3可以包括多个组成半导体器件,例如共同集成在同一半导体管芯420中。
参照图9、图11、图12和图16,在根据本发明的实施例的半导体器件2、3、4、6中,接触层的连续部分301可以在远离开口的方向上延伸,从而形成在金属接触区422上方并远离所述金属接触区而延伸的重分布键合焊盘区域150。
参照图8和图9,根据本发明的实施例的半导体器件1、2中的贵金属层可以包括:贵金属晶种层429,具有被溅射在连续部分301上和围绕所述连续部分的边缘的所述至少一个钝化层上的贵金属,其中,在所述溅射的贵金属与所述接触层之间并且在所述溅射的贵金属与所述至少一个钝化层之间建立借助原子键合的机械连接。所述贵金属层可以进一步包括被电镀至贵金属晶种层429上的贵金属424。
参照图15和图16,根据本发明的实施例的半导体器件5、6中的贵金属层可以包括:贵金属层524,具有被溅射在连续部分301上和围绕所述连续部分的边缘的所述至少一个钝化层上的贵金属,其中,例如经由中间粘合层529在所述溅射的贵金属与所述接触层之间并且在所述溅射的贵金属与所述至少一个钝化层之间建立机械连接。

Claims (10)

1.一种用于制造在恶劣介质中使用的半导体器件的方法,所述方法包括:
提供包括金属接触区的半导体管芯;
由至少一个钝化层来覆盖所述半导体管芯,并且对所述至少一个钝化层进行图案化,从而形成开口以便暴露所述半导体管芯的所述金属接触区;
在暴露的金属接触区上形成包括耐火金属的接触层,其中,所述接触层包括至少粘合层和至少扩散阻挡层;
对所述接触层进行图案化,从而通过围绕所述接触层的连续部分的整个边缘暴露所述至少一个钝化层以在所述暴露的金属接触区上方限定所述连续部分,其中,所述接触层的所述连续部分与所述至少一个钝化层中的所述开口重叠并完全覆盖所述开口;以及
在所述接触层上方提供贵金属层,从而完全覆盖所述接触层的所述连续部分,其中,所述贵金属层还在所述接触层的所述连续部分的所述边缘上方延伸,从而粘合至围绕所述连续部分的边缘的被暴露的所述至少一个钝化层,
其中,所述提供所述贵金属层包括:在所述接触层的所述连续部分上并且在围绕所述连续部分的边缘的被暴露的所述至少一个钝化层上溅射所述贵金属,从而通过在所述溅射的贵金属与所述接触层之间并且在所述溅射的贵金属与所述至少一个钝化层之间进行原子键合来建立机械连接;并且
其中,溅射所述贵金属包括:溅射贵金属晶种层以便在所述接触层的所述连续部分上并且在围绕所述连续部分的边缘的被暴露的所述至少一个钝化层上进行电镀,并且其中,提供所述贵金属层进一步包括:将所述贵金属电镀至所述贵金属晶种层上。
2.如权利要求1所述的方法,其中,所述对所述接触层进行图案化包括:对所述接触层进行图案化,从而使得所述接触层的所述连续部分在远离所述开口的方向上延伸,从而形成在所述金属接触区上方并远离所述金属接触区而延伸的重分布键合焊盘区域。
3.如权利要求1所述的方法,其中,提供所述贵金属层进一步包括:在所述贵金属晶种层上方形成电镀模具,
其中,电镀所述贵金属包括:将所述贵金属电镀至由所述电镀模具限定的模具开口内部的所述贵金属晶种层上,
其中,提供所述贵金属层进一步包括:在电镀所述贵金属之后,移除所述电镀模具,
并且其中,提供所述贵金属层进一步包括:在所述贵金属晶种层和/或所述接触层未被经电镀的贵金属覆盖之处移除所述贵金属晶种层和/或所述接触层。
4.如权利要求3所述的方法,其中,所述模具开口在平行于所述半导体管芯的平面内具有占用区,所述占用区比所述接触层的所述连续部分的相应占用区更大。
5.如权利要求4所述的方法,其中,所述模具开口的圆周边缘在所述连续部分的所述占用区的外部,并且在沿着所述圆周边缘的每个点中与所述连续部分的所述占用区间隔开至少预定的裕度。
6.如权利要求1所述的方法,其中,由所述至少一个钝化层覆盖所述半导体管芯包括:在所述半导体管芯上提供第一钝化层或第一钝化层堆叠,并且在所述第一钝化层上或所述第一钝化层堆叠上提供至少一个重钝化层,并且
其中,对所述至少一个钝化层进行图案化包括:对所述第一钝化层或所述第一钝化层堆叠和所述重钝化层两者都进行图案化,从而形成开口以便通过所述第一钝化层或所述第一钝化层堆叠并通过所述重钝化层暴露所述半导体管芯的所述金属接触区。
7.如权利要求6所述的方法,其中,对所述至少一个钝化层进行图案化包括:在所述第一钝化层中或所述第一钝化层堆叠中形成第一开口,并且在所述重钝化层中形成第二开口,其中,所述第二开口小于所述第一开口。
8.如权利要求1所述的方法,其中,形成所述接触层包括:将至少所述耐火金属溅射至所述暴露金属接触区上并溅射至所述至少一个钝化层上。
9.一种用于制造在恶劣介质中使用的半导体器件的方法,所述方法包括:
提供包括金属接触区的半导体管芯;
由至少一个钝化层来覆盖所述半导体管芯,并且对所述至少一个钝化层进行图案化,从而形成开口以便暴露所述半导体管芯的所述金属接触区;
在暴露的金属接触区上形成包括耐火金属的接触层,其中,所述接触层包括至少粘合层和至少扩散阻挡层;
对所述接触层进行图案化,从而通过围绕所述接触层的连续部分的整个边缘暴露所述至少一个钝化层以在所述暴露的金属接触区上方限定所述连续部分,其中,所述接触层的所述连续部分与所述至少一个钝化层中的所述开口重叠并完全覆盖所述开口;以及
在所述接触层上方提供贵金属层,从而完全覆盖所述接触层的所述连续部分,其中,所述贵金属层还在所述接触层的所述连续部分的所述边缘上方延伸,从而粘合至围绕所述连续部分的边缘的被暴露的所述至少一个钝化层;
其中,所述提供所述贵金属层包括:在所述接触层的所述连续部分上并且在围绕所述连续部分的边缘的被暴露的所述至少一个钝化层上溅射所述贵金属,从而通过在所述溅射的贵金属与所述接触层之间并且在所述溅射的贵金属与所述至少一个钝化层之间进行原子键合来建立机械连接;
其中,提供所述贵金属层包括:创建剥离掩模,所述剥离掩模限定了围绕所述接触层的所述连续部分的壁,并且其中,在所述连续部分上并且在围绕所述连续部分的边缘的被暴露的所述至少一个钝化层上溅射所述贵金属包括:将所述贵金属溅射穿过所述剥离掩模;
其中,提供所述贵金属层进一步包括:在将所述贵金属溅射穿过所述剥离掩模之前,通过所述剥离掩模直接在所述接触层上并且直接在被暴露的所述至少一个钝化层上溅射粘合层;并且
其中,所述粘合层被溅射至在所述接触层的厚度的五十分之一至五分之一的范围内且在所述溅射的贵金属的厚度的五十分之一至十分之一的范围内的厚度。
10.一种用于制造在恶劣介质中使用的半导体器件的方法,所述方法包括:
提供包括金属接触区的半导体管芯;
由至少一个钝化层来覆盖所述半导体管芯,并且对所述至少一个钝化层进行图案化,从而形成开口以便暴露所述半导体管芯的所述金属接触区;
在暴露的金属接触区上形成包括耐火金属的接触层,其中,所述接触层包括至少粘合层和至少扩散阻挡层;
对所述接触层进行图案化,从而通过围绕所述接触层的连续部分的整个边缘暴露所述至少一个钝化层以在所述暴露的金属接触区上方限定所述连续部分,其中,所述接触层的所述连续部分与所述至少一个钝化层中的所述开口重叠并完全覆盖所述开口;以及
在所述接触层上方提供贵金属层,从而完全覆盖所述接触层的所述连续部分,其中,所述贵金属层还在所述接触层的所述连续部分的所述边缘上方延伸,从而粘合至围绕所述连续部分的边缘的被暴露的所述至少一个钝化层;
其中,所述提供所述贵金属层包括:在所述接触层的所述连续部分上并且在围绕所述连续部分的边缘的被暴露的所述至少一个钝化层上溅射所述贵金属,从而通过在所述溅射的贵金属与所述接触层之间并且在所述溅射的贵金属与所述至少一个钝化层之间进行原子键合来建立机械连接;
其中,由所述至少一个钝化层覆盖所述半导体管芯包括:在所述半导体管芯上提供第一钝化层或第一钝化层堆叠,并且在所述第一钝化层上或所述第一钝化层堆叠上提供至少一个重钝化层,并且
其中,对所述至少一个钝化层进行图案化包括:对所述第一钝化层或所述第一钝化层堆叠和所述重钝化层两者都进行图案化,从而形成开口以便通过所述第一钝化层或所述第一钝化层堆叠并通过所述重钝化层暴露所述半导体管芯的所述金属接触区;并且
其中,对所述至少一个钝化层进行图案化包括:在所述第一钝化层中或所述第一钝化层堆叠中形成第一开口,并且在所述重钝化层中形成第二开口,其中,所述第二开口小于所述第一开口。
CN201810107192.4A 2017-02-02 2018-02-02 用于恶劣介质应用的键合焊盘保护 Active CN108461407B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP17154431.5A EP3358616B1 (en) 2017-02-02 2017-02-02 Bond pad protection for harsh media applications
EP17154431.5 2017-02-02

Publications (2)

Publication Number Publication Date
CN108461407A CN108461407A (zh) 2018-08-28
CN108461407B true CN108461407B (zh) 2020-12-11

Family

ID=57965755

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810107192.4A Active CN108461407B (zh) 2017-02-02 2018-02-02 用于恶劣介质应用的键合焊盘保护

Country Status (5)

Country Link
US (1) US10262897B2 (zh)
EP (1) EP3358616B1 (zh)
JP (1) JP2018125533A (zh)
KR (1) KR20180090200A (zh)
CN (1) CN108461407B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11404310B2 (en) * 2018-05-01 2022-08-02 Hutchinson Technology Incorporated Gold plating on metal layer for backside connection access
US11244915B2 (en) 2019-10-31 2022-02-08 Globalfoundries Singapore Pte. Ltd. Bond pads of semiconductor devices
CN114730701A (zh) * 2020-05-29 2022-07-08 桑迪士克科技有限责任公司 包括嵌入接合焊盘的扩散阻挡层的半导体裸片及其形成方法
US11450624B2 (en) 2020-05-29 2022-09-20 Sandisk Technologies Llc Semiconductor die including diffusion barrier layers embedding bonding pads and methods of forming the same
US11444039B2 (en) 2020-05-29 2022-09-13 Sandisk Technologies Llc Semiconductor die including diffusion barrier layers embedding bonding pads and methods of forming the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015204393A (ja) * 2014-04-15 2015-11-16 サンケン電気株式会社 半導体装置
US9502248B1 (en) * 2015-10-16 2016-11-22 Infineon Technologies Ag Methods for making a semiconductor chip device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2007052335A1 (ja) 2005-11-01 2009-04-30 株式会社日立製作所 半導体圧力センサ
US7468556B2 (en) * 2006-06-19 2008-12-23 Lv Sensors, Inc. Packaging of hybrid integrated circuits
JP2012175089A (ja) * 2011-02-24 2012-09-10 Fujitsu Ltd 半導体装置及び半導体装置の製造方法
US9040352B2 (en) * 2012-06-28 2015-05-26 Freescale Semiconductor, Inc. Film-assist molded gel-fill cavity package with overflow reservoir
JP2015024393A (ja) * 2013-07-29 2015-02-05 株式会社村田製作所 接着剤塗布方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015204393A (ja) * 2014-04-15 2015-11-16 サンケン電気株式会社 半導体装置
US9502248B1 (en) * 2015-10-16 2016-11-22 Infineon Technologies Ag Methods for making a semiconductor chip device

Also Published As

Publication number Publication date
EP3358616B1 (en) 2021-10-27
JP2018125533A (ja) 2018-08-09
US10262897B2 (en) 2019-04-16
KR20180090200A (ko) 2018-08-10
CN108461407A (zh) 2018-08-28
EP3358616A1 (en) 2018-08-08
US20180218937A1 (en) 2018-08-02

Similar Documents

Publication Publication Date Title
CN108461407B (zh) 用于恶劣介质应用的键合焊盘保护
KR100658547B1 (ko) 반도체 장치 및 그 제조 방법
US8163629B2 (en) Metallization for chip scale packages in wafer level packaging
US6518092B2 (en) Semiconductor device and method for manufacturing
KR100647760B1 (ko) 반도체 장치 및 그 제조 방법
KR100682434B1 (ko) 반도체 장치 및 그 제조 방법
US7947592B2 (en) Thick metal interconnect with metal pad caps at selective sites and process for making the same
CN101740490B (zh) 半导体装置制造方法和半导体装置
US8709876B2 (en) Electronic device
TWI529867B (zh) 具多層覆墊金屬化部的黏接墊與形成方法
JP2006237594A (ja) 半導体装置及びその製造方法
US8946896B2 (en) Extended liner for localized thick copper interconnect
TWI438852B (zh) 形成遠後端製程(fbeol)半導體元件之方法
US9324611B2 (en) Corrosion resistant via connections in semiconductor substrates and methods of making same
US9627335B2 (en) Method for processing a semiconductor workpiece and semiconductor workpiece
US20150194398A1 (en) Conductive Lines and Pads and Method of Manufacturing Thereof
JP2010251791A (ja) 半導体装置及びその製造方法
US20060183312A1 (en) Method of forming chip-type low-k dielectric layer
TW200930173A (en) Package substrate having embedded semiconductor element and fabrication method thereof
CN103367243B (zh) 通过氧化形成浅通孔
JP5036127B2 (ja) 半導体装置の製造方法
US9455239B2 (en) Integrated circuit chip and fabrication method
JP2011071175A (ja) 半導体装置および半導体装置の製造方法
JP2006120803A (ja) 半導体装置及び半導体装置の製造方法
US20220328434A1 (en) Oxidation and corrosion prevention in semiconductor devices and semiconductor device assemblies

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant