TWI438852B - 形成遠後端製程(fbeol)半導體元件之方法 - Google Patents

形成遠後端製程(fbeol)半導體元件之方法 Download PDF

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TWI438852B
TWI438852B TW096111680A TW96111680A TWI438852B TW I438852 B TWI438852 B TW I438852B TW 096111680 A TW096111680 A TW 096111680A TW 96111680 A TW96111680 A TW 96111680A TW I438852 B TWI438852 B TW I438852B
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Taiwan
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layer
stack
terminal
copper pad
blm
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TW096111680A
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TW200739776A (en
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Daniel C Edelstein
Mukta G Farooq
Robert Hannon
Ian D Melville
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Ibm
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Description

形成遠後端製程(FBEOL)半導體元件之方法
本發明大致係有關半導體元件處理技術，且更特定係有關用以去除遠後端製程(far back end of line,FBEOL)半導體結構上的鋁端子墊材的方法及結構。
在製造半導體時，一製作完成的積體電路(IC)元件一般係組裝成一種可用於印刷電路板上的封裝，以作為該電路板的一部份。為了使封裝中的鉛能與所製作完成的積體電路元件上的黏接墊彼此電性接觸，會形成一金屬鍵來連接該IC元件的黏接墊與一延伸至封裝鉛框的鉛。在其他設計中，例如，控制崩潰晶片連接(C4)，可在陶瓷或聚合物晶片載體上連接上一焊錫球。
過去，係以鋁或鋁合金作為傳統晶片連線材料。最近，逐漸以銅及銅合金來取代鋁連線材料，因為相較於鋁或鋁合金，銅連線可提供較佳的晶片效能和優異的可靠度。但是，使用銅連線來封裝IC元件須克服幾項相關的技術問題，這些問題都與銅會和焊錫球製程中的材料反應和/或銅易受環境因素攻擊與腐蝕相關， 在目前的C4實務中，係在被動層中形成端子通孔開口直達其下方的端子墊銅連線層。之後，在該端子墊銅上以習知方式形成一端子金屬(terminal metal,TD)鋁墊結構，接著在使用BLM(ball limiting metallurgy,BLM)的C4鉛-錫焊球來連接至TD墊之前，施以一最終有機鈍化層沉 積、圖案化及硬化製程。該TD金屬製程代表會增加製造步驟以及與該半導體結構相關的成本。因此，希望能消除該鋁TD墊，讓所有晶片連線都能直接由鋁連接至銅。但是，簡單地從製程中除去該TD鋁結構本身的製造步驟，會使銅暴露在有機鈍化材料中和大氣環境下，導致不好的反應。
可利用一種用以形成遠後端製程(far back end of line,FBEOL)半導體元件之方法來克服或減少上述相關前技討論中前技的缺點或不足。在一例示的實施方案中，所述方法包括形成一端子銅墊在一半導體晶圓之一上層，形成一絕緣堆疊在該端子銅墊上，及圖案化和打開該絕緣堆疊一部分中的一端子通孔，以留下該絕緣堆疊之一底帽蓋層來保護該端子銅墊。形成一有機鈍化層在該絕緣堆疊上並加以圖案化，且除去覆蓋在該端子銅墊上方的底帽蓋層。在該有機鈍化層和該端子銅墊上沉積一BLM堆疊，並在該BLM堆疊的一已圖案化部份上形成一焊錫球連接點。
在另一實施方案中，一半導體元件，其包括一形成在一半導體晶圓之一上層的端子銅墊，一形成在該端子銅墊上之絕緣堆疊，一直接形成在該端子銅墊和一已圖案化的鈍化層側壁上的BLM堆疊，及一形成在該BLM堆疊的一已圖案化部份上的焊錫球連接點。
在此揭示用以移除在遠後端製程之半導體結構上的鋁端子材料之方法及結構。簡單地說，形成為一絕緣堆疊(其中形成有端子銅)之一部份的SiC(N,H)帽蓋層(或氮化物或其他適當的層)，在鈍化層的形成、圖案化及硬化期間係被留在其中，但接續在BLM沉積前將其移除。
參照第1圖，示出依據傳統FBEOL處理技術所形成之具有一端子金屬鋁墊結構102的半導體元件100的剖面示圖。該元件100也包括一端子銅層104，形成在一半導體晶圓106之最上層。一如此技藝中熟知的，此最上層端子銅層104可在晶圓106中的下方元件區和該鋁墊結構102間形成一界面。該鋁墊結構102，則可用以支撐一C4組態的焊錫球連接點108，例如，用於接合晶片至一外部元件(例如，陶瓷晶片載體)。
第2(a)~2(e)圖繪示出現行用以形成第1圖之半導體元件100的製程。
藉由在一圖案化開口中進行沉積而來形成銅層104，其中該圖案化開口係形成於一絕緣層110(例如，一氟化的TEOS(四乙氧矽烷)或一氟化的矽酸玻璃(FSG))中。可選擇性地將多個垂直的氧化物支柱112涵括在該端子銅區域，以防止該銅層在其之CMP研磨期間被深度碟化。接續在該銅層104的CMP研磨後，在該元件100上方形成一絕緣堆疊114，經由此而打開一TD通孔116(第2(b)圖)。此堆疊114包括SiC(N,H)(摻雜氮之氫化的碳化矽)帽蓋層118、氧化物層120(亦即，利用矽烷沉積而得)及氮化矽層122(亦 即，利用電漿強化化學氣相沉積(PECVD)而得)。
接著，微影蝕刻以圖案化該TD通孔116，並使用一反應性離子蝕刻(RIE)(其使用CF4 、氧氣、氬氣或其之組合)來打開該堆疊層118(亦即，氮化物層122、氧化物層120及SiC(N,H)帽蓋層118)中的每一層，以顯露出該銅層104，如第2(b)圖所示。之後，在第2(c)圖中，實施習知的TD鋁製程，包括沉積一薄線堆疊124(包含一或多種下列材料：Ti、TiN、Ta、TaN，每一層的厚度約200~800Å)作為TD鋁和銅層104間的擴散阻障，接著進行TD鋁沉積(亦即，1.2微米的鋁-銅合金，其中銅濃度約為0.5%)。第2(c)圖示出在沉積、微影及蝕刻後的TD鋁墊102。
接著，在最上層墊氮化物層122上方，形成一最終鈍化聚醯亞胺層(如，光敏性聚醯亞胺(PSPI)層126)，如第2(d)圖所示。將聚醯亞胺層126圖案化以界定出一開口，並於該開口中沉積及圖案化該焊錫BLM，如第2(e)圖所示。一如此領域所習知的，該BLM包括一堆疊128，其包含一或多種以下材料，例如：TiW、CrCu及Cu。最後，在形成光阻後，微影及蝕刻該BLM堆疊128，之後沉積該焊錫材料(即，97%鉛/3%錫)的C4鍍層，以獲得如第1圖所示之結構。
如前述，藉由減少該FBEOL結構的成本以及藉由提高與上述製造步驟相關之產率，來移除TD鋁墊的能力將會非常有利。但是，簡單地從目前製程移除該TD鋁墊會導致銅-聚醯胺酸或銅-聚醯亞胺間的交互作用。不幸的是，這樣的交互作用會對電的效能及可靠度帶來不利的後果。
因此，第3(a)至3(e)圖示出用以移除FBEOL之半導體結構上的鋁端子材料的方法和結構。詳言之，第3(a)圖繪示在FBEOL處理的一點上，即蝕刻端子通孔116的圖樣穿過氮化矽層122和氧化物層120，但不會穿過摻雜有氮(或氮化物材料)的SiC-系層118，因此可保護銅墊104。之後，因SiC(N,H)層118仍在原處，接著沉積、圖案化及硬化該有機聚醯亞胺鈍化層126(即，PSPI)，如第3(b)圖所示。此時，該結構已準備好可用來沉積該BLM，一旦該SiC(N,H)層118被移除之後，如第3(c)圖所示。
在一實施方式中，可以一種不會強烈攻擊銅的蝕刻劑來移除該SiC(N,H)層118(較佳係在聚醯亞胺被硬化之後立即移除)。隨著晶圓被轉移至另一處理室或另一位置進行BLM處理，可在沉積BLM之前，以BLM背濺鍍蝕刻來將少量的銅氧化後以清潔之。或者，可在聚醯亞胺被硬化之後仍讓該SiC(N,H)層118留在原地，直到其被放入BLM沉積室為止。接著，可在BLM處理室中，於沉積BLM之前，利用物理性背濺鍍蝕刻來移除該SiC(N,H)層118本身。
另一種用來保護銅墊104的方式為以一種有機焊錫性保護層(organic soldrability preservative,OSP)(例如，苯並三唑(BTA))來塗佈該墊104，其可有效地防止表面被腐蝕，例如，可於60℃下將其浸漬在0.2%的水溶液中2分鐘。此層可輕易地在濺鍍蝕刻期間被移除，就在BLM沉積之前。必要時，也可實施額外的步驟，例如，在氮氣或混合氣體(forming gas)環境下所進行的高溫烘烤。另一種用來保護銅墊104的方式是在圖案化端子通孔之後，晶圓上 塗佈一層TaN或其他導電性氧化阻障層。在此之後，即接續進行一平坦化處理，使得只有端子通孔內，而非上表面上，仍留有該TaN材料。
無論是哪一種狀況，一旦該SiC(N,H)層118被移除之後，即在鈍化層126上和直接在銅墊104上，形成該BLM堆疊128，如第3(d)圖所示。最後，在第3(e)圖中，在該圖案化的BLM堆疊128上形成焊錫球連接點108，因此可獲致不含TD鋁的結構300。此外，相對於習知元件(即，BLM結構形成在一TD鋁墊上)，該結構300表現出較佳的拉伸測試結果。
雖然已經參考較佳具體實施例來說明本發明，習知技藝人士應知在不悖離本發明精神範疇下，仍可對本發明技術作多種改良，且可以等效物來替代其元件。所以，本發明並不希望受限於本文所揭示之被視為用於實行本發明之最佳模式的特殊具體實施例，相反地，本發明將包含屬於所附申請專利範圍之範疇與精神之所有具體實施例。
100‧‧‧半導體元件
102‧‧‧端子金屬鋁墊結構
104‧‧‧端子銅層
106‧‧‧半導體晶圓
108‧‧‧焊錫球連接點
110‧‧‧絕緣層
112‧‧‧氧化物支柱
114‧‧‧絕緣堆疊
116‧‧‧TD通孔
118‧‧‧SiC(N,H)帽蓋層
120‧‧‧氧化物層
122‧‧‧氮化矽層
124‧‧‧薄線堆疊
126‧‧‧聚醯亞胺層
128‧‧‧BLM堆疊
300‧‧‧不含TD鋁的結構
參照範例性圖式，其中在多個圖式中相同的元件命名相同的符號：第1圖為一以習知技術形成之具有端子墊鋁的控制崩潰晶片連接(C4)半導體元件的橫斷面圖；第2(a)~2(e)圖為用以形成第1圖結構的處理流程圖；及 第3(a)~3(e)圖為依據本發明一實施方案，用來移除在遠後端製程半導體結構上之鋁端子材料的處理流程圖。
104‧‧‧端子銅層
106‧‧‧半導體晶圓
108‧‧‧焊錫球連接點
110‧‧‧絕緣層
114‧‧‧絕緣堆疊
118‧‧‧SiC(N,H)帽蓋層
120‧‧‧氧化物層
122‧‧‧氮化矽層
126‧‧‧聚醯亞胺層
128‧‧‧BLM堆疊
300‧‧‧不含TD鋁的結構

Claims (8)

  1. 一種用以形成遠後端製程半導體元件的方法，包含以下步驟：形成一端子銅墊在一半導體晶圓之一上層；形成一絕緣堆疊在該端子銅墊上；圖案化和打開該絕緣堆疊之一部分中之一端子通孔，以留下該絕緣堆疊之一底帽蓋層來保護該端子銅墊；當該底帽蓋層仍正在保護該端子銅墊時，在該絕緣堆疊上形成一有機鈍化層並加以圖案化；一旦完成該形成一有機鈍化層並加以圖案化，則移除覆蓋在該端子銅墊上方的該底帽蓋層；在該有機鈍化層和該端子銅墊上沉積一球形受限冶金化(BLM)堆疊(ball limiting metallurgy(BLM)stack)；及在該BLM堆疊之一已圖案化部份上形成一焊錫球連接點。
  2. 如申請專利範圍第1項所述之方法，其中該底帽蓋層包含一摻雜氮之氫化的碳化矽帽蓋層。
  3. 如申請專利範圍第2項所述之方法，其中在該有機鈍化層硬化後，即以化學性蝕刻來移除該摻雜氮之氫化的碳化矽帽蓋層。
  4. 如申請專利範圍第2項所述之方法，其中在沉積該BLM堆疊之前，以背濺鍍蝕刻來移除該摻雜氮之氫化的碳 化矽帽蓋層。
  5. 如申請專利範圍第2項所述之方法，更包含以一有機焊錫保護(organic solderability preservative,OSP)層來塗佈該端子銅墊，並在沉積該BLM堆疊之前，以背濺鍍蝕刻來移除該OSP層。
  6. 如申請專利範圍第2項所述之方法，更包含在該端子通孔被圖案化之後，以一種導電氧化保護阻障層來塗佈該有機鈍化層與該端子銅墊，之後並從該有機鈍化層上移除部份的該導電氧化保護阻障層。
  7. 如申請專利範圍第1項所述之方法，其中該有機鈍化層更包含一聚醯亞胺層。
  8. 如申請專利範圍第1項所述之方法，其中該絕緣堆疊更包含一摻雜氮之氫化的碳化矽帽蓋層、一氧化矽層(其係沉積在該摻雜氮之氫化的碳化矽帽蓋層上方)、及一氮化矽層(其係沉積在該氧化矽層上方)。
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JP2009532917A (ja) 2009-09-10
US20070232049A1 (en) 2007-10-04
CN101410965B (zh) 2010-11-03
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US7375021B2 (en) 2008-05-20
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