TWI594385B - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TWI594385B
TWI594385B TW099133831A TW99133831A TWI594385B TW I594385 B TWI594385 B TW I594385B TW 099133831 A TW099133831 A TW 099133831A TW 99133831 A TW99133831 A TW 99133831A TW I594385 B TWI594385 B TW I594385B
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Taiwan
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layer
conductive
passivation layer
contact
metal contact
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TW099133831A
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TW201115703A (en
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劉重希
余振華
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台灣積體電路製造股份有限公司
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Description

半導體元件及其製造方法
本發明係有關於半導體元件，特別有關於在半導體晶片形成接點的系統與方法。
一般而言，半導體晶片包括主動元件，連接至主動元件的金屬化層，以及提供信號及電力至金屬化層與主動元件的輸入/輸出接點(I/O contact)。金屬化層一般包括一系列的介電層與金屬層，以提供主動元件與輸入/輸出接點之間以及個別的主動元件之間所需的全部連接。這些介電層可由低介電常數介電材料形成，其介電常數(k值)介於約2.9至3.8之間；或者由超低介電常數(ultra low-k；ULK)介電材料形成，其介電常數(k值)小於約2.5；或者由極低介電常數(extra low-k；ELK)介電材料形成，其介電常數(k值)介於約2.5至約2.9之間；或者由低介電常數介電材料的組合形成。
然而，當使用這些低介電常數、超低介電常數(ULK)及極低介電常數(ELK)材料改善金屬化層的電性特徵，並藉此增加半導體元件的整體速度或效率時，這些材料也具有主要的結構缺點。在半導體元件中，相較於其他介電材料，這些材料比較難應付施加在其上的應力，當太多應力施加至低介電常數、超低介電常數(ULK)及極低介電常數(ELK)材料時，這些低介電常數、超低介電常數(ULK)及極低介電常數(ELK)材料本身會傾向於脫層或裂開，此脫層或裂開現象會損傷或破壞半導體元件。
依據一實施例，半導體元件包括具有複數個介電層與複數個導電層的基底，金屬接點與這些導電層的最上層電性連接，金屬接點的厚度大於約15000，連接器與金屬接點電性連接。
依據另一實施例，半導體包括具有複數個金屬層的基底，金屬接點與這些金屬層的最上層電性連接，其中金屬接點的厚度大於約15000，導電柱與金屬接點電性連接。
依據又另一實施例，半導體元件的製造方法包括提供基底，在基底之上形成複數個導電層與複數個介電層，介電層位於導電層之間，在這些導電層的最上層之上形成鈍化層，在鈍化層內形成金屬接點，並且金屬接點與這些導電層的最上層連接，金屬接點的厚度大於約15000，在鈍化層之上形成導電柱，導電柱電性連接至金屬接點。
為了讓本發明之上述目的、特徵、及優點能更明顯易懂，以下配合所附圖式，作詳細說明如下：
以下詳述各實施例的製造與使用，然而，可以理解的是，在此所揭示的這些實施例提供許多可應用的發明概念，其可以在各種不同的特定背景中實施。在此所討論的特定實施例僅用於說明這些實施例製造與使用的特定方式，並非用於限定發明的範圍。
在此所揭示的實施例稱為導電柱結構，然而，此揭示也可應用在其他的接觸結構。
除非特別指出，在不同圖式中的標號及符號係對應至其相關的部分，這些圖式的繪製是用於清楚說明與各種實施例有關的概念，並且可以不需按尺寸繪製。
參閱第1圖，其顯示包括基底101、金屬化層103、第一金屬接點105以及第一鈍化層107的晶圓100之剖面示意圖。基底101可包括巨塊矽(bulk silicon)、摻雜或未摻雜的基底，或者為矽覆蓋絕緣層(silicon-on-insulator；SOI)基底的主動層。一般而言，矽覆蓋絕緣層基底包括一層半導體材料，例如矽、鍺、矽鍺化合物、矽覆蓋絕緣層(SOI)、在絕緣層上的矽鍺化合物(silicon germanium on insulator；SGOI)或前述之組合，其他可以使用的基底還包含多層基底、梯度(gradient)基底或混合式方向(hybrid orientation)基底。可以利用任何合適的方法，在基底101的表面上或基底內形成各種主動元件(未繪出)，例如電晶體、電容器、電阻器以及類似的元件。
金屬化層103在基底101之上形成，並用於連接各種主動元件，形成功能性電路。金屬化層103可由交替的介電層(如第一介電層109與第二介電層111)以及導電層(如第一導電層113與最上面的第二導電層115)形成，並且可經由任何合適的製程(如沈積、鑲嵌、雙鑲嵌等)形成。雖然第1圖顯示四層交替的介電層與導電層，但是在金屬化層103內的介電層與導電層的精確數量是取決於晶圓100的整體設計，並且可以大於或小於四層(如第二介電層111與第一導電層113之間的虛線所標示)。
金屬化層103的介電層(如第一介電層109與第二介電層111)可由例如介電常數(k值)介於約2.9至3.8之間的低介電常數介電材料形成，或者由介電常數(k值)小於約2.5的超低介電常數(ULK)介電材料形成，或者由介電常數(k值)介於約2.5至約2.9之間的極低介電常數(ELK)介電材料形成，或者由低介電常數介電材料的一些組合形成，或者由類似的材料形成。隨著介電常數(k值)的降低，在金屬化層103中的介電層變得更脆弱，並且變得容易脫層與裂開。
第一鈍化層107可以在最上面的導電層115之上形成，並且可包括介電材料，例如氧化物或氮化矽，而其他合適的介電質，例如高介電常數介電質或這些材料的任意組合也可以使用。第一鈍化層107可使用電漿增強型化學氣相沈積(plasma-enhanced chemical vapor deposition；PECVD)製程形成，而任何其他合適的製程也可以使用。第一鈍化層107的厚度可介於約0.6μm至約1.4μm之間，例如約為1μm。
第一金屬接點105位於第一鈍化層107內，第一金屬接點105是作為最上面的導電層115與外部接觸墊(如以下第2圖所示)之間的接點。第一金屬接點105可包括硬的材料，例如銅，而其他硬的材料，例如鎢、鋁或銅合金也可以使用。第一金屬接點105可使用鑲嵌或雙鑲嵌製程形成，其可包含在第一鈍化層107的開口內填充溢滿的(overfill)銅，接著經由例如化學機械研磨(chemical mechanical polishing；CMP)製程除去多餘的銅。然而，也可以使用任何合適的材料(例如鋁)與任何合適的製程(例如沈積與蝕刻)形成第一金屬接點105。
第一金屬接點105的厚度可以讓第一金屬接點105作為金屬化層103內的介電層(如第一介電層109與第二介電層111)之緩衝物，第一金屬接點105本身形成的厚度大於約15000，例如約為20000。當第一金屬接點105由硬的材料，例如銅，並且在此厚度範圍內製成，則第一金屬接點105可對金屬化層103內的低介電常數介電層、極低介電常數(ELK)介電層以及/或超低介電常數(ULK)介電層提供較佳的緩衝。此額外的緩衝作用可讓半導體元件在製程處理、運送以及使用中更堅固耐用，而不會讓金屬化層103內的介電層被其他物件破壞、脫層或裂開。
第2圖顯示形成第二鈍化層201與接觸墊203，第二鈍化層201可在第一鈍化層107與第一金屬接點105之上形成，藉此保護第一金屬接點105。第二鈍化層201可由與上述第1圖所示之第一鈍化層107相似的方式及相似的材料形成，或者第一鈍化層107與第二鈍化層201可由不同的材料形成。一旦形成第二鈍化層201之後，第二鈍化層201可經由合適的遮罩與移除製程(例如微影遮罩與蝕刻製程)圖案化，藉此讓接觸墊203與第一金屬接點105產生電性連接。
接觸墊203提供從晶圓100的電路(包含主動元件與金屬化層103)經由第一金屬接點105至其他晶圓100以外的元件(未繪出)之連接，接觸墊203可以是鋁/銅合金，並且可藉由在第二鈍化層201之上形成鋁/銅合金初始層，與第一金屬接點105產生電性接觸而形成。一旦鋁/銅合金初始層形成之後，接著可使用合適的技術，例如微影與蝕刻將鋁/銅合金圖案化，形成如第2圖所示之接觸墊203。接觸墊203的厚度可介於約10000至約50000之間，例如約為25000。
然而，在此技術領域中具有通常知識者當可瞭解，上述形成接觸墊203的製程只是一種材料與一種形成的方法，其他合適的材料也可以使用，包含(但不限於)例如鋁、金、銀、鎳、銅、鎢、鈦、鉭、前述之化合物、前述之合金、前述之多層結構、前述之複合物以及前述之組合。再者，不同的材料可能需要不同的形成方法，例如濺鍍或甚至是雙鑲嵌製程。所有這些材料以及形成的方法都可以擇一使用，並且每個材料與方法都包含在本發明的範圍內。
第3圖顯示在第二鈍化層201之上形成第三鈍化層301、凸塊下金屬化層(underbump metallization；UBM)302以及遮罩303。第三鈍化層301可在第二鈍化層201與接觸墊203之上形成，其在後續製程期間以及晶圓100可能遭遇的其他環境中保護第二鈍化層201與接觸墊203，避免受到物理與環境的損壞。第三鈍化層301可經由與第一鈍化層107及第二鈍化層201相似的製程，由相似的材料形成(分別如上述的第1圖與第2圖)，或者第三鈍化層301可由與第一鈍化層107及第二鈍化層201不同的材料形成。
一旦第三鈍化層301在第二鈍化層201與接觸墊203之上形成，可穿過第三鈍化層301形成開口，暴露出接觸墊203的一部份，用於另外的連接。此開口可經由合適的遮罩與移除製程形成，例如合適的微影遮罩與蝕刻製程。然而，在此揭示所討論的圖案化製程僅用於作為代表製程，任何其他合適的圖案化製程也可以用於暴露出接觸墊203的一部份。
在此階段，可使用選擇性的聚亞醯胺(polyimide；PI)塗層304保護第三鈍化層301，PI塗層304可藉由在第三鈍化層301上塗佈絕緣材料而形成，例如聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole；PBO)或環氧化物(epoxy)，其厚度介於約2.5μm至約12μm之間，例如約為4μm。此外，PI塗層304可經由噴灑聚亞醯胺溶液或者將第三鈍化層301浸泡在聚亞醯胺溶液中而形成，或者也可以使用任何合適的形成方法。PI塗層304可經由合適的遮罩與蝕刻製程而圖案化，暴露出接觸墊203的那些已經被第三鈍化層301暴露出來的部分，藉此讓與其底下的接觸墊203的連接形成。
一旦第三鈍化層301圖案化之後，可形成凸塊下金屬化層(UBM)302與接觸墊203接觸，凸塊下金屬化層(UBM)302可包括一層鈦與銅合金，然而，在此技術領域中具有通常知識者當可瞭解，有許多合適的材料與層的排列，例如鈦/銅/鎳的排列、鉻/鉻-銅合金/銅/金的排列、鈦/鈦鎢/銅的排列或銅/鎳/金的排列，這些都適合用於形成凸塊下金屬化層(UBM)302，任何用於凸塊下金屬化層(UBM)302的合適材料或材料層也包含在本發明的範圍內。
凸塊下金屬化層(UBM)302可藉由在PI塗層304與第三鈍化層301之上，並且沿著開口的內部順應性地形成每一層而產生，每一層的形成可使用濺鍍、化學氣相沈積(CVD)或電鍍製程進行，雖然其他製程，例如蒸鍍或電漿增強型化學氣相沈積(PECVD)製程也可以使用，其取決於使用的材料。凸塊下金屬化層(UBM)302的厚度可介於約0.1μm至約2μm之間，例如約為0.5μm。
一旦第三鈍化層301、PI塗層304與凸塊下金屬化層(UBM)302形成之後，可在凸塊下金屬化層(UBM)302之上形成遮罩303。在一實施例中，遮罩303可以是乾膜，其可包含有機材料，例如增層絕緣膜(Ajinimoto buildup film；ABF)。此外，遮罩303可由光阻材料形成。一旦遮罩303形成之後，接著可將遮罩303圖案化，形成在接觸墊203之上的凸塊下金屬化層(UBM)302的導電柱開口305。
在一實施例中，導電柱開口305配合後續形成在導電柱開口305內的導電柱400所需的尺寸與形狀(如下述的第4圖)而形成，導電柱開口305的寬度可介於約10μm至約200μm之間，例如約為80μm，並且其到第三鈍化層301底部表面的深度可介於約3000至約60000之間，例如約為40000。
第4圖顯示在導電柱開口305(參閱第3圖)內選擇性地填充導電柱400，導電柱400作為接觸墊203與晶圓100的元件之間的電性連接，藉此讓信號與電力按路線發送至金屬化層103，並且最後傳送至位於基底101上的主動元件(未繪出)。
可形成導電柱400與凸塊下金屬化層(UBM)302接觸，並且導電柱400可由導電材料形成。在一實施例中，導電材料可包含金屬，例如銅或銅合金，雖然其他金屬，例如鋁、銀、金、前述之組合以及類似的材料也可以使用。導電柱400可經由合適的製程形成，例如電性電鍍，並且其厚度可小於約60μm，或甚至介於約30μm至約50μm之間。一旦導電柱400形成，可以在導電柱400之上形成選擇性的導電阻障層(未繪出)，例如由含鎳層、含銅層或含錫層形成。
接著，如第5圖所示，使用合適的移除製程移除遮罩303(參閱第3及4圖)，將凸塊下金屬化層(UBM)302圖案化，並且在導電柱400之上形成保護層501。遮罩303移除後留下導電柱400，並且以導電柱開口305的形狀存在(參閱第3圖)。一旦遮罩303移除之後，凸塊下金屬化層(UBM)302的一部份可經由合適的微影遮罩與蝕刻製程移除，以移除不需要的材料，並且留下凸塊下金屬化層(UBM)302作為接觸墊203與導電柱400之間的連接。
在移除遮罩303與圖案化凸塊下金屬化層(UBM)302之後，可沿著導電柱400的側壁形成保護層501，保護層501覆蓋且保護其底下的導電柱400，避免導電柱400在後續製程期間或使用時受到環境或物理性的損壞。保護層501可由錫形成，並且可使用浸潤式電鍍(immersion plating)製程施加在側壁上，其形成的厚度介於約500 至約5000 之間，例如約為2000 。然而，這些材料與製程僅作為示範用，其他合適的方法與材料也可以使用。例如，保護層501可由鎳鈀合金形成，經由例如無電鍍鈀浸金(electroless palladium immersion gold；ENEPIG)的製程，或簡單地經由無電鍍鎳浸金(electroless nickel immersion gold；ENIG)的製程形成。
第6圖顯示另一實施例，其中接觸墊203(參閱第5圖)以後鈍化內連線(post-passivation interconnect；PPI)結構601取代，其沿著第二鈍化層201延伸。後鈍化內連線601可以讓導電柱400電性連接至第一金屬接點105，因此導電柱400可以放置在晶圓100的任何所需的位置上，而不需限制導電柱400的位置一定要直接位在第一金屬接點105上方的區域內。
在此實施例中，後鈍化內連線601的形成最初是經由合適的製程，例如化學氣相沈積(CVD)或濺鍍製程，形成鈦銅合金的晶種層(未繪出)，接著在晶種層之上形成光阻(未繪出)，然後將光阻圖案化，暴露出晶種層的一些部份，其位於後鈍化內連線601所需的位置上。
一旦光阻形成並圖案化，經由沈積製程例如電鍍，可在晶種層上形成導電材料603，例如銅。導電材料603的厚度可介於約1μm至約10μm之間，例如約為5μm。然而，上述用於形成導電材料603的材料與方法僅作為示範用，任何其他合適的材料，例如AlCu或Au，以及任何其他合適的製程，例如化學氣相沈積(CVD)或物理氣相沈積(PVD)也可以用於形成導電材料603。
一旦導電材料603形成之後，可經由合適的移除製程移除光阻。此外，移除光阻之後，被光阻覆蓋的晶種層的這些部分使用導電材料603作為遮罩，經由例如合適的蝕刻製程除去。
在移除晶種層之後，可在後鈍化內連線601的任何所需的部分之上形成第三鈍化層301、PI塗層304、凸塊下金屬化層(UBM)302、導電柱400以及保護層501，維持與第一金屬接點105的接觸。在此實施例中，第三鈍化層301、PI塗層304、凸塊下金屬化層(UBM)302、導電柱400以及保護層501可經由任何合適的製程形成，例如上述第3至6圖所示之方式。使用後鈍化內連線601可以讓導電柱400放置在任何因應例如最佳化、配置或任何其他原因所需的位置上。
第7圖顯示另一實施例，其中導電柱400(參閱第6圖)以接觸凸塊701取代，在此實施例中，於凸塊下金屬化層(UBM)302與遮罩303形成之後，在遮罩303的開口內形成接觸凸塊701。接觸凸塊701的材料可包括例如錫或其他合適的材料，例如銀、無鉛錫或銅。在一實施例中，接觸凸塊701為錫的銲錫凸塊，接觸凸塊701的形成最初是形成錫層，其係經由常用的方法，例如電鍍、蒸鍍、印刷等，形成厚度約為100μm的錫層。一旦接觸凸塊701在遮罩303的開口內形成，接著使用合適的移除製程，例如剝離(stripping)製程移除遮罩303，並且可如上述第5A圖所示之方式將凸塊下金屬化層(UBM)302圖案化。一旦遮罩303移除之後，可進行回銲步驟，使得接觸凸塊701形成圓滑的上表面。
第8至9圖顯示又另一實施例，其中不含接觸墊203(參閱第2至6圖)，並且形成導電柱400接觸第一金屬接點105。藉由形成導電柱400接觸第一金屬接點105，可以省略接觸墊203，藉此可簡化製造晶圓100的整個製程。
首先參閱第8圖，為了形成導電柱400接觸第一金屬接點105，第一金屬接點105與第二鈍化層201的形成與上述第1及2圖所示之形成方式相似，將第二鈍化層201圖案化，形成開口暴露出第一金屬接點105的一部份，然後取代接觸墊203的形成，在第二鈍化層201之上以及溝槽內形成PI塗層304，並且也覆蓋第一金屬接點105。
一旦PI塗層304形成之後，將PI塗層304從溝槽的底部移除，使得第一金屬接點105的上表面暴露出來，此移除步驟可使用合適的遮罩與移除製程進行，例如微影遮罩與蝕刻製程。另外，當移除製程可選擇性地從溝槽的側壁移除PI塗層304時，在一實施例中，不會從溝槽的側壁移除PI塗層304，藉此隔絕後續形成的導電柱400。
第9圖顯示在PI塗層304之上形成導電柱400與保護層501，導電柱400接觸第一金屬接點105。導電柱400可經由與上述第3至5圖所示之相似的製程形成，然而，在此實施例中，形成導電柱400接觸第一金屬接點105，以取代前述第2至6圖所示之接觸墊203，其可以讓從導電柱400至金屬化層103的流動產生較少的電阻。
第10圖顯示使用在此所述之實施例，於第一金屬接點105的厚度範圍內可以得到的意外好處。如第10圖所示，在一實施例中，對無鉛銲錫凸塊使用5/3μm Cu/Ni電鍍的UBM，並且鋁接觸墊的厚度約為14000。當第一金屬接點105的厚度沿著X軸增加至上述第1圖所示之關鍵範圍，在其底下的ELK介電層上的正規化應力(normalized stress)也隨之降低，到目前為止，其下方ELK介電層上的正規化應力低於ELK介電層的失效點。此外，第10圖也顯示在一實施例中，其中所使用的鋁接觸墊的厚度約為14000厚，增加頂端金屬的厚度可降低正規化ELK應力至失效點之下，藉此半導體晶片比較能夠抵抗製程及傳送中的危害，在使用時產生較少的失效，且更具有可靠度。
雖然揭示的實施例以及其優點已經詳述如上，可以理解的是，在不脫離申請專利範圍所定義的發明範圍及精神內，也可以進行各種變化、替換以及修改。例如，可以使用各種不同的材料以及製程形成導電柱，這些材料與製程全部都包含在揭示的範圍內。
雖然本發明已揭露較佳實施例如上，然其並非用以限定本發明，在此技術領域中具有通常知識者當可瞭解，在不脫離本發明之精神和範圍內，當可做些許更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定為準。
100．．．晶圓
101．．．基底
103．．．金屬化層
105．．．第一金屬接點
107．．．第一鈍化層
109．．．第一介電層
111．．．第二介電層
113．．．第一導電層
115．．．最上面的第二導電層
201．．．第二鈍化層
203．．．接觸墊
301．．．第三鈍化層
302．．．凸塊下金屬化層
303．．．遮罩
304．．．PI塗層
305．．．導電柱開口
400．．．導電柱
501．．．保護層
601．．．後鈍化內連線
603．．．導電材料
701．．．接觸凸塊
第1圖係顯示依據一實施例之半導體元件，其包括基底、金屬化層、第一金屬接點以及第一鈍化層。
第2圖係顯示依據一實施例，形成第二鈍化層與接觸墊。
第3圖係顯示依據一實施例，在第二鈍化層之上形成第三鈍化層及遮罩。
第4至5圖係顯示依據一實施例，形成導電柱。
第6圖係顯示依據一實施例，形成後鈍化內連線結構。
第7圖係顯示依據一實施例，形成接觸凸塊。
第8至9圖係顯示在一實施例中，導電柱與第一金屬接點接觸。
第10圖係顯示與第一金屬接點的厚度範圍有關的優點。
100．．．晶圓
101．．．基底
103．．．金屬化層
105．．．第一金屬接點
107．．．第一鈍化層
109．．．第一介電層
111．．．第二介電層
113．．．第一導電層
115．．．最上面的第二導電層
201．．．第二鈍化層
203．．．接觸墊
301．．．第三鈍化層
302．．．凸塊下金屬化層
304．．．PI塗層
400．．．導電柱
501．．．保護層

Claims (11)

  1. 一種半導體元件，包括：一基底，包括複數個介電層與複數個導電層，其中該些介電層的材料包括介電常數介於2.5至2.9之間的介電材料；一金屬接點，與該些導電層的一最上層電性連接，該金屬接點的厚度大於15000Å且不超過20000Å；以及一連接器，與該金屬接點電性連接。
  2. 如申請專利範圍第1項所述之半導體元件，其中該連接器為一導電柱。
  3. 如申請專利範圍第2項所述之半導體元件，更包括一接觸墊連接該金屬接點與該連接器，其中該接觸墊包括鋁。
  4. 如申請專利範圍第2項所述之半導體元件，更包括一後鈍化內連線連接該金屬接點與該導電柱，其中該後鈍化內連線包括鋁。
  5. 如申請專利範圍第2項所述之半導體元件，其中該導電柱為一銅柱，該金屬接點包括銅。
  6. 如申請專利範圍第1項所述之半導體元件，其中該連接器直接接觸該金屬接點。
  7. 如申請專利範圍第1項所述之半導體元件，其中該連接器為一銲錫凸塊。
  8. 如申請專利範圍第1項所述之半導體元件，更包括一鈍化層設置於該最上層的導電層之上，其中該金屬接點設置於該鈍化層內，且該金屬接點的頂部與該鈍化層 的頂部為共平面。
  9. 一種半導體元件的製造方法，包括：提供一基底；在該基底之上形成複數個導電層與複數個介電層，該些介電層位於該些導電層之間，且該些介電層的材料包括介電常數介於2.5至2.9之間的介電材料；在該些導電層的一最上層之上形成一鈍化層；在該鈍化層內形成一金屬接點，並且與該些導電層的該最上層連接，該金屬接點的厚度大於15000Å且不超過20000Å；以及在該鈍化層之上形成一導電柱，該導電柱電性連接至該金屬接點。
  10. 如申請專利範圍第9項所述之半導體元件的製造方法，更包括在形成該導電柱之前，在該金屬接點之上形成一接觸墊。
  11. 如申請專利範圍第9項所述之半導體元件的製造方法，其中該金屬接點的頂部與該鈍化層的頂部為共平面。
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