TWI712141B - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TWI712141B
TWI712141B TW106108627A TW106108627A TWI712141B TW I712141 B TWI712141 B TW I712141B TW 106108627 A TW106108627 A TW 106108627A TW 106108627 A TW106108627 A TW 106108627A TW I712141 B TWI712141 B TW I712141B
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Taiwan
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conductive
pseudo
conductive pads
pads
layer
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TW106108627A
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TW201824494A (zh
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許峯誠
鄭心圃
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台灣積體電路製造股份有限公司
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Abstract

一種包括積體電路、介電層、多個連接端子及至少一個 擬導體的半導體裝置。積體電路具有多個連接墊，且介電層配置於多個連接墊上並藉由在介電層中界定的多個開口而局部地暴露出多個連接墊。多個連接端子配置於藉由多個開口而暴露出的多個連接墊上。擬導體配置於介電層上並與積體電路電性隔離。在多個連接端子與擬導體之間存在實質性拓樸變化。

Description

半導體封裝
本發明的實施例是有關於一種半導體裝置與半導體封裝。
積體電路被用於例如個人電腦、手機、數碼相機及其他電子裝備等各種各樣的電子應用中。許多積體電路可與其他半導體裝置或管芯一起進行加工或封裝，且已開發出各種技術。
本發明的實施例提供一種半導體裝置包括積體電路、介電層、多個連接端子以及至少一個擬導體。積體電路具有多個連接墊，且介電層配置於多個連接墊上並藉由在介電層中界定的多個開口而局部地暴露出多個連接墊。多個連接端子配置於藉由多個開口而暴露出的多個連接墊上。至少一個擬導體配置於介電層上並與積體電路電性隔離。在多個連接端子與至少一個擬導體之間存在實質性拓樸(topology)變化。
本發明的實施例提供一種半導體封裝包括電路基板以及 半導體裝置。所述半導體裝置配置於所述電路基板上且包括積體電路、介電層、多個連接端子以及至少一個擬導體。所述積體電路具有多個連接墊，且所述介電層配置於所述多個連接墊上並藉由在所述介電層中界定的多個開口而局部地暴露出所述多個連接墊。所述多個連接端子配置於藉由所述多個開口而暴露出的所述多個連接墊上。所述至少一個擬導體配置於所述介電層上並與所述積體電路電性隔離。在所述多個連接端子與所述至少一個擬導體之間存在實質性拓樸變化。所述半導體裝置經由所述多個連接端子及所述至少一個擬導體而結合至所述電路基板上。
本發明的實施例提供一種半導體封裝包括積體電路、介電層、多個連接端子、至少一個擬導體以及重佈線路結構。所述積體電路具有多個連接墊，且所述介電層配置於所述多個連接墊上並藉由在所述介電層中界定的多個開口而局部地暴露出所述多個連接墊。所述多個連接端子配置於藉由所述多個開口而暴露出的所述多個連接墊上。所述至少一個擬導體配置於所述介電層上並與所述積體電路電性隔離。在所述多個連接端子與所述至少一個擬導體之間存在實質性拓樸變化。所述積體電路經由所述多個連接端子及所述至少一個擬導體而結合至所述重佈線路結構上。
10:晶圓
20、30、40、50:半導體封裝
100:積體電路
110:半導體基板
120:內連線結構
122:層間介電層
124:圖案化導電層
140:緩衝層
150:導電墊
162:連接端子
162a:第一導電部分
162b:第二導電部分
164:擬導體
200:電路基板
210:基板
220、320:焊罩層
220a:表面
230、330:第一焊墊
232、332:第一部分
234、334:第二部分
236:第三部分
240、340:第二焊墊
302:載體
303:剝離層
310:重佈線層
312:聚合物介電層
314:金屬層
DI:介電層
H1、H2、H3:高度
O1、O2:開口
P1:第一開口
P2:第二開口
PAD:連接墊
RS:重佈線路結構
SD:半導體裝置
SL:切割道
UF:底部填充物
△H:拓撲變化
圖1A至圖1D是根據本發明某些示例性實施例的半導體裝置 的製造過程中的各種階段的示意性剖視圖。
圖2是說明根據本發明某些示例性實施例的半導體封裝的示意性剖視圖。
圖3是說明根據本發明某些示例性實施例的另一半導體封裝的示意性剖視圖。
圖4是說明根據本發明某些示例性實施例的另一半導體封裝的示意性剖視圖。
圖5是說明根據本發明某些示例性實施例的另一半導體封裝的示意性剖視圖。
圖6A至圖6D是根據本發明某些示例性實施例的半導體封裝的製造過程中的各種階段的示意性剖視圖。
以下揭露內容提供用於實施所提供標的物的不同特徵的許多不同實施例或實例。下文描述組件以及配置的特定實例以簡化本發明。當然，此等組件以及配置僅僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包含第一特徵以及第二特徵直接接觸地形成的實施例，且還可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵與第二特徵可不直接接觸的實施例。另外，本發明可在各種實例中重複圖式元件符號以及/或字母。此重複是出於簡化以及清楚的目的，且本身並不指示所論述的各種實施例以及/或組態之間 的關係。
另外，為易於描述，本文中可使用諸如「在...之下」、「在...下方」、「下部」、「在...上方」、「上部」以及其類似者的空間相對術語，以描述如諸圖中所說明的一個元件或特徵相對於另一元件或特徵的關係。除了諸圖中所描繪的定向之外，空間相對術語意欲涵蓋裝置在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用的空間相對描述詞同樣可相應地進行解釋。
圖1A至圖1D是根據本發明某些示例性實施例的半導體裝置的製造過程中的各種階段的示意性剖視圖。參照圖1A，提供晶圓(wafer)10。在某些實施例中，晶圓10包括呈陣列形式排列的多個積體電路100。如圖1A中所示，在晶圓10上執行沿切割道SL(在圖1A至圖1D中示作虛線)進行的晶圓鋸切(sawing)或切割(dicing)製程之前，晶圓10的積體電路100是彼此連接的。在圖1A中，為說明起見，在圖1A中僅示出兩個積體電路100。
在圖1A中，積體電路100中的每一者包括半導體基板110及配置於半導體基板110上的內連線結構120。內連線結構120覆蓋半導體基板110。在某些實施例中，半導體基板110可為其中形成有主動元件(例如，二極體、電晶體等)及被動元件(例如，電阻器、電容器、電感器等)的矽基板。
在某些實施例中，內連線結構120可包括交替堆疊的多個層間介電層122及多個圖案化導電層124。例如，層間介電層 122可為聚醯亞胺、聚苯並惡唑(polybenzoxazole，PBO)、苯環丁烷(benzocyclobutene，BCB)、例如氮化矽等氮化物、例如氧化矽等氧化物、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼矽酸鹽玻璃(borosilicate glass，BSG)、摻雜硼的磷矽酸鹽玻璃(boron-doped phosphosilicate glass，BPSG)或上述材料的組合等，層間介電層122可利用微影製程(photolithography process)及/或蝕刻製程(etching process)而圖案化。在某些實施例中，可藉由例如旋轉塗佈(spin-on coating)、化學氣相沉積(CVD)、電漿增強型化學氣相沉積(plasma-enhanced chemical vapor deposition，PECVD)等適合的製作技術來形成層間介電層122。例如，圖案化導電層124是由藉由電鍍或沉積而形成的導電材料(例如，銅、銅合金、鋁、鋁合金或上述材料的組合)製成，圖案化導電層124可利用微影製程及蝕刻製程而圖案化。在某些實施例中，圖案化導電層124可為圖案化銅層或其他適合的圖案化金屬層。
在本說明通篇中，用語“銅”旨在包括實質上純的元素銅、含有不可避免的雜質的銅或含有少量例如鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁、鋯等元素的銅合金等。
在圖1A中，最頂層的層間介電層122中界定的多個開口O1可暴露出最頂部圖案化導電層124的一部分。可將具有開口O1的最頂層的層間介電層122稱作介電層DI。換句話說，如圖1A中所示，介電層DI(122)中的多個開口O1可暴露出最頂部 圖案化導電層124的一部分。在某些實施例中，介電層DI的厚度介於2微米與10微米之間。在某些實施例中，介電層DI充當保護層(passivation layer)，且介電層DI是由無機材料(例如氧化矽、氮化矽、氮氧化矽或任何適合的介電材料)製成，介電層DI可利用微影製程及/或蝕刻製程而圖案化。
在某些實施例中，積體電路100是藉由前端(front end of line，FEOL)製程來製造。然而，本發明並非僅限於此。應理解，在所有的附圖中，對積體電路100及其他組件的例示是示意性的且並非按比例繪示。
在圖1B中，在晶圓10的積體電路100上形成緩衝層140。在某些實施例中，緩衝層140共形地(conformally)配置於介電層DI上且具有多個開口O2，開口O2分別暴露出藉由介電層DI中的開口O1而暴露出的最頂部圖案化導電層124中的對應一者。在某些實施例中，緩衝層140可由有機材料(例如聚醯亞胺(PI)層、聚苯並惡唑(PBO)層、其他適合的聚合物層或任何適合的介電材料)製成。可例如藉由微影製程及/或蝕刻製程來執行圖案化製程。
如圖1A及圖1B中所示，以緩衝層140局部地覆蓋藉由介電層DI中的開口O1而暴露出的圖案化導電層124中的最頂部圖案化導電層124，以使得藉由緩衝層140中的開口O2而進一步暴露出藉由介電層DI中的開口O1而暴露出的最頂部圖案化導電層124。此處，可將藉由緩衝層140中的開口O2而暴露出的最頂 部圖案化導電層124稱作多個連接墊PAD。
在某些實施例中，藉由相應的介電層(例如，介電層DI及/或緩衝層140)而使藉由緩衝層140中的開口O2而暴露出的連接墊PAD彼此分開。在某些實施例中，使用連接墊PAD將積體電路100電性耦接至例如導電墊等外部連接。
在圖1C中，在緩衝層140上形成多個導電墊150，且在導電墊150上分別形成多個連接端子162及至少一個擬導體164。如圖1C中所示，將導電墊150的一部分形成為藉由緩衝層140中的開口O2以接觸連接墊PAD(例如，藉由緩衝層140中的開口O2而暴露出的內連線結構120的最頂部圖案化導電層124)，且將導電墊150的另一部分以不接觸連接墊PAD的方式形成於緩衝層140上。在某些實施例中，可將導電墊150與連接墊PAD接觸的部分稱作凸塊下金屬(under bump metallurgy，UBM)。
例如，形成導電墊150、連接端子162及擬導體164包括在緩衝層140上共形地且完全地形成晶種層(圖中未示出)。在某些實施例中，晶種層為金屬層，其可為單一層或包括由不同材料形成的多個子層的複合層。在某些實施例中，晶種層包括鈦層及位於鈦層之上的銅層，或者包括兩個鈦層及夾置於兩個鈦層之間的銅層。可利用例如濺鍍等來形成晶種層。
隨後，接著在晶種層上形成光阻層(圖中未示出)並將光阻層圖案化。可藉由旋轉塗佈(spin coating)等方式來形成光阻層並且可對光阻層進行曝光(exposure)以進行圖案化。光阻層 的圖案的至少一部分對應於藉由緩衝層140中的開口O2而暴露出的連接墊PAD。圖案化製程會形成藉由光阻層的開口以暴露出晶種層，其中晶種層的被暴露出的部分對應於並且接觸藉由緩衝層140中的開口O2而暴露出的連接墊PAD。
接著，在光阻層中界定的開口中及晶種層被暴露出的部分區域上形成導電材料(圖中未示出)，以在晶種層被暴露出且與連接墊PAD接觸的部分區域上形成連接端子162，而在形成連接端子162的同時，例如可在晶種層被暴露出但不與連接墊PAD接觸的部分區域上形成擬導體164。換句話說，連接端子162電性連接至積體電路100，且擬導體164與積體電路100電性隔離。在某些實施例中，可使用連接端子162來電性連接其他半導體裝置或電性接地。在某些實施例中，擬導體164可為電性浮置或電性接地的。本發明並非僅限於此。
可藉由電鍍(例如，有電電鍍或無電電鍍等)來形成導電材料。導電材料可包括金屬，例如銅、鋁、金、鎳、銀、鈀、錫等。在某些實施例中，連接端子162及擬導體164可為高鉛的導電材料或無鉛的導電材料。連接端子162及擬導體164可為金屬柱(如圖1D中所示)、球柵陣列封裝(ball grid array，BGA)連接件、焊球、受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊、無電鍍鎳浸金技術(electroless nickel-immersion gold technique，ENIG)所形成的凸塊、無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)所形成的凸塊等。另外，可執行回焊製程(reflow process)以將導電材料構形成所期望的凸塊形狀。
在形成連接端子162及擬導體164之後，可藉由例如使用氧電漿等的灰化製程(ashing process)或剝除製程(stripping process)來移除光阻層。當光阻層被移除時，利用蝕刻製程來移除晶種層未被導電材料所覆蓋的部分以形成導電墊150。在某些實施例中，蝕刻製程可為濕蝕刻(wet etching)或乾蝕刻(dry etching)。然而，本發明並非僅限於此。
在某些實施例中，利用連接端子162及擬導體164作為罩幕以移除晶種層未被導電材料所覆蓋的部分而達到執自對準圖案化製程(self-align patterning process)的目的，進而形成導電墊150。換句話說，連接端子162與其下的導電墊150具有實質上相同的圖案，且擬導體164與其下的導電墊150具有實質上相同的圖案。也就是說，如圖1C中所示，連接端子162的側壁與其下的導電墊150的側壁實質上對準，且擬導體164的側壁與其下的導電墊150的側壁實質上對準。
如圖1C中所示，連接端子162中的每一者包括第一導電部分162a及第二導電部分162b。第一導電部分162a配置於緩衝層140中的開口O2中，第二導電部分162b配置於緩衝層140中的開口O2外，第二導電部分162b連接第一導電部分162a，且第一導電部分162a的高度H1與第二導電部分162b的高度H2的總和實質上等於擬導體164的高度H3。由於第一導電部分162a的 結構，因此在連接端子162與擬導體164之間存在實質性拓樸變化△H，其中實質性拓樸變化△H傾向設計為至少3微米。在某些實施例中，實質性拓樸變化△H介於3微米至10微米之間。實質性拓樸變化△H發生的主要原因是由於介電層DI的存在，且實質性拓樸變化△H受介電層DI的厚度極大地影響，因此，本實施例可藉由修改介電層DI的厚度來調整實質性拓樸變化△H。連接端子162與擬導體164之間的實質性拓樸變化△H隨著介電層DI的厚度變大而變大。由於可控的實質性拓樸變化△H，因此連接端子162及擬導體164可具有更小的臨界尺寸，因此後續製程可獲得更好控制。
另一方面，連接端子162中的每一者實質上具有彼此相同的高度，且即便在連接端子162中的任意兩者之間存在高度差，連接端子162中的任意兩者之間的高度差仍處於可接受公差內，且因此是可被忽略的。可接受公差是連接端子162中的任意兩者之間的高度差，其中公差大約小於2微米。由於高度差落於可接受公差內，因此連接端子162中的任意兩者之間的高度差為不顯著的且被視為無意(意即，非刻意設計所產生)的。相似地，在某些實施例中，所述至少一個擬導體164包括例如兩個或更多個擬導體，擬導體實質上具有相同的高度，且即便在任意兩個擬導體之間存在高度差，任意兩個擬導體之間的高度差仍處於可接受公差內，高度差為可被忽略的。可接受公差是擬導體中的任意兩者之間的高度差，其中公差大約小於2微米。由於高度差落於可 接受公差內，因此擬導體中的任意兩者之間的高度差為不顯著的且被視為無意的。
在某些實施例中，如圖1C中所示，連接端子162中的至少一者的寬度(或直徑)不同於擬導體164的寬度(或直徑)。在某些實施例中，所述至少一個擬導體164包括例如兩個或更多個擬導體，其中兩個或更多個擬導體可具有不同寬度(或不同直徑)。
在圖1D中，執行切割製程(例如，單體化(singulation))以沿切割道SL將晶圓10分切成獨立且單體化的半導體裝置SD。在一個實施例中，切割製程為晶圓切割製程。截至此時，半導體裝置SD便已初步製造完成。另外，由於擬導體164的存在，在將半導體裝置結合至另一半導體裝置或載體之後，整體的機械強度可得到增強。
圖2是說明根據本發明某些示例性實施例的另一半導體封裝的示意性剖視圖。在圖2中，電路基板200與半導體裝置SD結合。圖2中的半導體裝置SD是圖1D中所繪示的半導體裝置SD，可在以上找到關於圖2中的半導體裝置SD的詳細說明，故不再對相同的技術內容予以贅述。
如上，半導體裝置SD包括積體電路、緩衝層140、導電墊150、連接端子162及擬導體164。積體電路具有半導體基板110及內連線結構120，其中內連線結構120配置於半導體基板110上。緩衝層140配置於積體電路的內連線結構120上，其中積體電路具有連接墊PAD(例如，內連線結構120中最頂部圖案化導 電層124的藉由緩衝層140中的開口O2而暴露出的部分)，且介電層DI(例如，內連線結構120的最頂層的層間介電層122)局部地暴露出連接墊PAD。
導電墊150的一部分配置於藉由緩衝層140(及介電層DI)而暴露出的連接墊PAD上並且電性連接至連接墊PAD，且導電墊150的另一部分則配置於緩衝層140上並且與藉由緩衝層140(及介電層DI)而暴露出的連接墊PAD電性隔離。連接端子162電性連接至導電墊150中與連接墊PAD電性連接的部分，且擬導體164連接至導電墊150中配置於緩衝層140上且與連接墊PAD電性隔離的部分。
由於連接端子162的結構，因此連接端子162與擬導體164之間的實質性拓樸變化△H是可被觀察到的，且為至少3微米。在某些實施例中，實質性拓樸變化△H介於3微米至10微米之間。由於上述可控的實質性拓樸變化△H，因此連接端子162及擬導體164可具有更小的臨界尺寸。在某些實施例中，連接端子162中的至少一者的直徑不同於擬導體164的直徑。在某些實施例中，擬導體164包括例如兩個或更多個擬導體，其中兩個或更多個擬導體可具有不同直徑。
如圖2中所示，電路基板200包括基板210、焊罩層220、多個第一焊墊230及多個第二焊墊240，其中第一焊墊230與第二焊墊240藉由焊罩層220而彼此電性隔離。在某些實施例中，基板210包括金屬跡線或金屬線(metal traces or metal lines)及位 於其下且連接至金屬跡線或其他半導體裝置的導通孔(vias)。焊罩層220配置於基板210上且將第一焊墊230與第二焊墊240分開。
在某些實施例中，第一焊墊230包括第一部分232及第二部分234，其中第一部分232配置於基板210上且藉由在焊罩層220中所界定的多個第一開口而局部地暴露出，第二部分234接觸第一部分232且配置於焊罩層220中的第一開口中，且第二部分232延伸至焊罩層220朝向半導體裝置SD的表面220a。在某些實施例中，第一焊墊230可被稱作凸塊下金屬類型的墊(UBM-like pads)。在某些實施例中，第一焊墊230分別電性連接至其下的金屬跡線(或金屬線)以經由第一部分232而耦接至基板210中的其他組件。
在某些實施例中，第二焊墊240配置於基板210上且藉由在焊罩層220中界定的多個第二開口而局部地被暴露出。在某些實施例中，第二焊墊240可被稱作焊罩層界定墊(solder mask defined pads)。在某些實施例中，第二焊墊240可分別電性連接至其下的金屬跡線(或金屬線)以耦接至基板210中的其他組件或電性浮置(或電性接地)。
在某些實施例中，第一焊墊230的第一部分232與第二焊墊240處於同一層中。例如，形成焊罩層220、第一焊墊230及第二焊墊240的方法可包括在基板210上沉積導電材料(圖中未示出)，接著，將導電材料圖案化以形成第一焊墊230的第一部 分232及第二焊墊240，在第一焊墊230的第一部分232及第二焊墊240上塗佈焊罩層220並將焊罩層220圖案化，以形成暴露出第一焊墊230的第一部分232的第一開口及暴露出第二焊墊240的第二開口。接著，第一焊墊230的第二部分234可藉由打線接合機(wire bonding machine)而形成於第一焊墊230的第一部分232上，且第二部分234可為螺栓狀凸塊(stud bump)。在某些實施例中，圖案化製程可為微影製程及/或蝕刻製程。
然而，本發明並不限制焊罩層220、第一焊墊230及第二焊墊240的形成製程。在其他實施例中，形成具有開口的圖案化光阻層，而開口僅暴露出第一焊墊230的第一部分232，接著，執行沉積製程以在第一部分232上及圖案化光阻層的開口中形成第一焊墊230的第二部分234。當第一焊墊230的第二部分234形成時，藉由灰化製程或剝除製程移除圖案化光阻層。
在圖2中，半導體裝置SD被翻轉(上下翻轉)並且配置於電路基板200上。換句話說，半導體裝置SD與電路基板200藉由覆晶結合技術(flip chip bonding technology)而結合。在某些實施例中，底部填充物UF至少填充半導體裝置SD與電路基板200之間的間隙。在一個實施例中，底部填充物UF可藉由底部填充物分配(underfill dispensing)或其他適合的方法來形成。
由於存在於半導體裝置SD中的實質性拓樸變化△H，因此連接端子162連接至第一焊墊230的第二部分234，且擬導體164連接至第二焊墊240。半導體裝置SD經由連接端子162及第 一焊墊230而電性連接至電路基板200。如上所述，實質性拓樸變化△H是可調節的，且可允許連接端子162及擬導體164具有更小的臨界尺寸，進而實現更好的程序控制。由於擬導體164的存在，在半導體裝置SD結合至電路基板200之後，半導體封裝的整體機械強度得到增強。在某些實施例中，當擬導體電性接地時，可實現半導體封裝的信號完整度的增強及/或雜訊的減少。
圖3是說明根據本發明某些示例性實施例的半導體封裝的示意性剖視圖。如在圖3中看出，半導體封裝30相似於圖2所示半導體封裝20。與先前所述的元件相似或實質上相同的元件將使用相同的參考編號，且本文中不再對相同元件予以贅述。不同之處是在圖3中，半導體封裝30的第二焊墊240藉由焊罩層220中的第二開口而完全地被暴露出。如圖3中所示，第二焊墊240與焊罩層220中的第二開口的側壁以間隙(gap)相互間隔開。也就是說，第二焊墊240不接觸焊罩層220。在某些實施例中，半導體封裝30的第二焊墊240可被稱作非焊罩層界定(non-solder mask defined，NSMD)墊。
圖4是說明根據本發明某些示例性實施例的另一半導體封裝的示意性剖視圖。如在圖4中看出，半導體封裝40相似於圖2所示半導體封裝20。與先前的元件相似或實質上相同的元件將使用相同的參考編號，且本文中不再對相同元件予以贅述。不同之處是在圖4中，半導體封裝40的第一焊墊230進一步包括連接至第二部分234的第三部分236，且第三部分236遠離第二部分 234突出(或是說朝半導體裝置SD突出)。如圖4中所示，半導體裝置SD經由第一焊墊230的第一部分232、第二部分234及第三部分236以及連接端子162而電性連接至電路基板200。在某些實施例中，第一焊墊230的第二部分234及第三部分236可藉由打線接合機而同時形成於第一焊墊230的第一部分232上，其中第二部分234及第三部分236被視作螺栓狀凸塊。然而，本發明並不限制第一焊墊230的第二部分234及第三部分236的製程。
圖5是說明根據本發明某些示例性實施例的另一半導體封裝的示意性剖視圖。如在圖5中看出，半導體封裝50相似於圖3所示半導體封裝30。與先前所述的元件相似或實質上相同的元件將使用相同的參考編號，且本文中不再對相同元件予以贅述。不同之處是在圖5中，半導體封裝50的第一焊墊230進一步包括連接至第二部分234的第三部分236，且第三部分236遠離第二部分234突出(或是說朝半導體裝置SD突出)。如圖5中所示，半導體裝置SD經由第一焊墊230的第一部分232、第二部分234及第三部分236以及連接端子162而電性連接至電路基板200。
本發明並非僅限於圖2至圖5中所繪示的實施例。在某些實施例中，由於存在於半導體裝置中的實質性拓樸變化△H，因此一個半導體封裝可在連接端子162與第一焊墊230(例如，凸塊下金屬類型的墊或具有另一突出部分的凸塊下金屬類型的墊)之間及/或擬導體164與第二焊墊240(例如，焊罩層界定墊或非焊罩層界定墊)之間包括不同構造。
圖6A至圖6D是根據本發明某些示例性實施例的半導體封裝的製造過程中的各種階段的示意性剖視圖。與先前所述的元件相似或實質上相同的元件將使用相同的參考編號，且本文中可不再對相同元件予以贅述。
在圖6A中，提供載體302，載體302可為玻璃載體或任何適合在其上製造重佈線路結構的載體。在某些實施例中，將載體302設置成上面塗佈有剝離層303，且剝離層303的材料可為任何能夠使載體302從配置其上的各膜層剝離的材料。然而，本發明並非僅限於此。剝離層303為可在其他實施例中被省略的選擇性膜層。
在圖6B中，在配置於載體302上的剝離層303上形成重佈線層310。例如，形成重佈線層310包括交替地依序形成一個或多個聚合物介電層312及一個或多個金屬層314。在某些實施例中，如圖6B中所示，金屬層314夾於聚合物介電層312之間，但暴露出最頂層的金屬層314的頂表面，並將最底層的金屬層314直接配置至剝離層203。
在某些實施例中，金屬層314的材料包括鋁、鈦、銅、鎳、鎢及/或其合金，且可藉由電鍍或沉積來形成金屬層314。在某些實施例中，聚合物介電層312的材料包括聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、苯環丁烷、聚苯並惡唑或任何其他適合的聚合物系介電材料。
如圖6B中所示，在重佈線層310上依序形成焊罩層320。 將焊罩層320配置於被暴露出的最頂層的金屬層314上，並藉由在焊罩層320中界定的多個第一開口P1及多個第二開口P2而暴露出最頂層的金屬層314的部分區域。例如，在某些實施例中，藉由塗佈而在重佈線層310的最頂層金屬層314上形成焊罩層320，接著，將焊罩層320圖案化以分別形成第一開口P1及第二開口P2以暴露出最頂層的金屬層314的部分。可例如藉由微影製程及/或蝕刻製程來執行圖案化製程。
藉由焊罩層320中的第一開口P1而暴露出的最頂層的金屬層314的部分稱作多個第一焊墊330的第一部分332，且藉由焊罩層320中的第二開口P2而暴露出最頂層的金屬層314的部分稱作多個第二焊墊340。第一焊墊330的第一部分332及第二焊墊340可包括導電墊(例如，鋁墊、銅墊等)、導電柱(例如，焊料柱、金柱、銅柱等)、導電凸塊(例如，經回焊的焊料凸塊、金凸塊、銅凸塊等)或其組合。
在圖6C中，在焊罩層320中的第一開口P1中形成第一焊墊330的第二部分334，且第二部分334延伸至焊罩層320的表面320a。第一焊墊330的第二部分334接觸第一部分332。如圖6B及圖6C中所示，將焊罩層320配置於基板210上，並使第一焊墊330與第二焊墊340分開。
在某些實施例中，藉由打線接合機在第一焊墊330的第一部分332上形成第一焊墊330的第二部分234，且第二部分234可為螺栓狀凸塊。在某些實施例中，第一焊墊330的第二部分334 的材料相同於第一焊墊330的第一部分332的材料，然而本發明並非僅限於此。在另一實施例中，第一焊墊330的第二部分334的材料不同於第一焊墊330的第一部分332的材料。
在某些實施例中，可將第一焊墊330稱作凸塊下金屬類型的墊。在某些實施例中，第一焊墊330的第一部分332為重佈線層310的一部分。在某些實施例中，可將第二焊墊340稱作焊罩層界定(SMD)墊。在某些實施例中，第二焊墊340為重佈線層310的一部分。在某些實施例中，第一焊墊330的第一部分332與第二焊墊340處於同一層中。截至此步驟，重佈線路結構RS製造便已初步完成。
在圖6D中，提供半導體裝置SD並將半導體裝置SD配置於重佈線路結構RS的第一焊墊330及第二焊墊340上。圖6D中的半導體裝置SD是圖1D中所繪示的半導體裝置SD，可在以上找到關於圖6D中的半導體裝置SD的詳細說明，且不再對相同的技術內容予以贅述。
如上所述，半導體裝置SD包括積體電路、緩衝層140、導電墊150、連接端子162及擬導體164。積體電路具有半導體基板110及內連線結構120，其中內連線結構120配置於半導體基板110上。緩衝層140配置於積體電路的內連線結構120上，其中積體電路具有連接墊PAD(例如，內連線結構120的最頂部圖案化導電層124的藉由緩衝層140中的開口O2而暴露出的部分)，且介電層DI(例如，內連線結構120的最頂層的層間介電層122) 局部地暴露出連接墊PAD。
導電墊150的一部分配置於被緩衝層140(及介電層DI)所暴露出的連接墊PAD上且電性連接至連接墊PAD，且導電墊150的另一部分配置於緩衝層140上且與被緩衝層140(及介電層DI)所暴露出的連接墊PAD電性隔離。連接端子162電性連接至導電墊150中被緩衝層140所暴露出的連接墊PAD，且擬導體164電性連接至導電墊150中被配置於緩衝層140上且與連接墊PAD電性隔離的部分。
由於連接端子162的結構，因此連接端子162與擬導體164之間的實質性拓樸變化△H是可觀察到的，且為至少3微米。在某些實施例中，實質性拓樸變化△H介於3微米至10微米之間。由於上述可控的實質性拓樸變化△H，因此可允許連接端子162及擬導體164具有更小的臨界尺寸。在某些實施例中，連接端子162中的至少一者的直徑不同於擬導體164的直徑。在某些實施例中，擬導體164包括例如兩個或更多個擬導體，其中兩個或更多個擬導體可具有不同直徑。
如圖6D中所示，將半導體裝置SD翻轉(上下翻轉)並且接著配置至重佈線路結構RS。換句話說，藉由覆晶結合技術而結合半導體裝置SD與重佈線路結構RS。在某些實施例中，底部填充物UF至少填充半導體裝置SD與重佈線路結構RS之間的間隙。在一個實施例中，可藉由底部填充物分配或其他適合的方法來形成底部填充物UF。
如圖6D中所示，在某些實施例中，經由配置於其間的連接端子162、擬導體164、第一焊墊330及第二焊墊340而將半導體裝置SD的積體電路結合至重佈線路結構RS。由於存在於半導體裝置SD中的實質性拓樸變化△H，因此可將半導體裝置SD的連接端子162連接至重佈線路結構RS的第一焊墊330的第二部分334，且將半導體裝置SD的擬導體164連接至重佈線路結構RS的第二焊墊340。經由連接端子162及第一焊墊330可將半導體裝置SD電性連接至重佈線路結構RS。截至此步驟，半導體封裝製造便已初步完成。
如上所述，實質性拓樸變化△H是可調節且可控制的，且可允許連接端子162及擬導體164具有更小的臨界尺寸，進而可實現更好的程序控制。由於擬導體164的存在，在將半導體裝置SD結合至重佈線路結構RS之後，半導體封裝的整體機械強度得到增強。
應注意，在某些實施例中，由於存在於半導體裝置SD中的實質性拓樸變化△H，因此半導體封裝可在連接端子162與第一焊墊330(例如，凸塊下金屬類型的墊或具有另一突出部分的凸塊下金屬類型的墊)之間及/或擬導體164與第二焊墊340(例如，焊罩層界定墊或非焊罩層界定墊)之間包括不同構造。本發明並非僅限於圖6D中所繪示的實施例。在某些實施例中，當擬導體電性接地時，可實現半導體封裝的信號完整度的增強及/或雜訊的減少。
根據某些實施例，提供一種半導體裝置包括積體電路、介電層、多個連接端子以及至少一個擬導體。所述積體電路具有多個連接墊，且所述介電層配置於所述多個連接墊上並藉由在所述介電層中界定的多個開口而局部地暴露出所述多個連接墊。所述多個連接端子配置於藉由所述多個開口而暴露出的所述多個連接墊上。所述至少一個擬導體配置於所述介電層上並與所述積體電路電性隔離。在所述多個連接端子與所述至少一個擬導體之間存在實質性拓樸變化。
在所述的半導體裝置中，所述多個連接端子中的每一者包括：第一導電部，配置於所述多個開口中；以及第二導電部，連接至所述第一導電部，其中所述第一導電部的高度與所述第二導電部的高度的總和等於所述擬導體的高度。
在所述的半導體裝置中，所述多個連接端子中的至少一者的直徑不同於所述擬導體的直徑。
在所述的半導體裝置中，所述擬導體是電性浮置或接地的。
所述的半導體裝置進一步包括：緩衝層，配置於所述介電層上且覆蓋藉由所述開口而暴露出的所述多個連接墊的一部分。
在所述的半導體裝置中，所述積體電路進一步包括：半導體基板；以及內連線結構，覆蓋所述半導體基板，其中所述內連線結構包括交替堆疊的多個圖案化導電層及多個層間介電層， 所述圖案化導電層中的最頂部圖案化導電層被所述層間介電層中的最頂層的層間介電層覆蓋，且所述最頂部圖案化導電層藉由在所述最頂層的層間介電層中界定的多個開口而局部地暴露出，其中所述介電層包括所述最頂層的層間介電層，且所述多個連接墊包括藉由所述多個開口而局部地暴露出的所述最頂部圖案化導電層。
根據某些實施例，提供一種半導體封裝包括電路基板以及半導體裝置。所述半導體裝置配置於所述電路基板上且包括積體電路、介電層、多個連接端子以及至少一個擬導體。所述積體電路具有多個連接墊，且所述介電層配置於所述多個連接墊上並藉由在所述介電層中界定的多個開口而局部地暴露出所述多個連接墊。所述多個連接端子配置於藉由所述多個開口而暴露出的所述多個連接墊上。所述至少一個擬導體配置於所述介電層上並與所述積體電路電性隔離。在所述多個連接端子與所述至少一個擬導體之間存在實質性拓樸變化。所述半導體裝置經由所述多個連接端子及所述至少一個擬導體而結合至所述電路基板上。
在所述的半導體裝置中，所述多個連接端子中的每一者包括：第一導電部，配置於所述多個開口中；以及第二導電部，連接至所述第一導電部，其中所述第一導電部的高度與所述第二導電部的高度的總和等於所述擬導體的高度。
在所述的半導體裝置中，所述多個連接端子中的至少一者的直徑不同於所述擬導體的直徑。
在所述的半導體裝置中，所述擬導體是電性浮置或接地的。
在所述的半導體裝置中，所述電路基板包括：焊罩層、多個第一焊墊以及多個第二焊墊，其中所述多個第一焊墊中的每一者的第一部分藉由在所述焊罩層中界定的多個第一開口而局部地暴露出且連接至所述多個連接端子，且與所述多個第一焊墊中每一者的所述第一部分連接的第二部分位於所述多個第一開口中並延伸至所述焊罩層的面朝所述半導體裝置的表面。所述多個第二焊墊藉由在所述焊罩層中界定的多個第二開口而至少局部地暴露出且連接至所述擬導體。
在所述的半導體裝置中，所述多個第一焊墊中的每一者進一步包括與所述第二部分連接的第三部分，且所述第三部分遠離所述第二部分突出。
在所述的半導體裝置中，所述多個第二焊墊藉由所述多個第二開口而完全暴露出，且所述多個第二焊墊中的每一者與所述多個第二開口中的對應一者的側壁間隔開。
根據某些實施例，提供一種半導體封裝包括積體電路、介電層、多個連接端子、至少一個擬導體以及重佈線路結構。所述積體電路具有多個連接墊，且所述介電層配置於所述多個連接墊上並藉由在所述介電層中界定的多個開口而局部地暴露出所述多個連接墊。所述多個連接端子配置於藉由所述多個開口而暴露出的所述多個連接墊上。所述至少一個擬導體配置於所述介電層 上並與所述積體電路電性隔離。在所述多個連接端子與所述至少一個擬導體之間存在實質性拓樸變化。所述積體電路經由所述多個連接端子及所述至少一個擬導體而結合至所述重佈線路結構上。
在所述的半導體裝置中，所述多個連接端子中的每一者包括：第一導電部，配置於所述多個開口中；以及第二導電部，連接至所述第一導電部，其中所述第一導電部的高度與所述第二導電部的高度的總和實質上等於所述擬導體的高度。
在所述的半導體裝置中，所述多個連接端子中的至少一者的直徑不同於所述擬導體的直徑。
在所述的半導體裝置中，所述擬導體是電性浮置或接地的。
在所述的半導體裝置中，所述重佈線路結構包括：焊罩層、多個第一焊墊以及多個第二焊墊，其中所述多個第一焊墊中的每一者的第一部分藉由在所述焊罩層中界定的多個第一開口而局部地暴露出且連接至所述多個連接端子，且與所述多個第一焊墊中每一者的所述第一部分連接的第二部分位於所述多個第一開口中並延伸至所述焊罩層的面朝所述半導體裝置的表面。所述多個第二焊墊藉由在所述焊罩層中界定的多個第二開口而至少局部地暴露出且連接至所述擬導體。
在所述的半導體裝置中，所述多個第一焊墊中的每一者進一步包括與所述第二部分連接的第三部分，且所述第三部分遠 離所述第二部分突出。
在所述的半導體裝置中，所述多個第二焊墊藉由所述多個第二開口而完全暴露出，且所述多個第二焊墊中的每一者與所述多個第二開口中的對應一者的側壁間隔開。
前文概述若干實施例的特徵，使得所屬領域中具通常知識者可較好地理解本發明的態樣。所屬領域中具通常知識者應瞭解，其可易於使用本發明作為設計或修改用於進行本文中所引入的實施例的相同目的以及/或達成相同優勢的其他製程以及結構的基礎。所屬領域中具通常知識者亦應認識到，此類等效構造並不脫離本發明的精神以及範疇，且其可在不脫離本發明的精神以及範疇的情況下在本文中進行各種改變、替代以及更改。
20:半導體封裝
110:半導體基板
120:內連線結構
122:層間介電層
124:圖案化導電層
140:緩衝層
150:導電墊
162:連接端子
164:擬導體
200:電路基板
210:基板
220:焊罩層
220a:表面
230:第一焊墊
232:第一部分
234:第二部分
240:第二焊墊
DI:介電層
PAD:連接墊
SD:半導體裝置
UF:底部填充物

Claims (8)

  1. 一種半導體封裝，包括：半導體裝置，包括：積體電路，具有多個連接墊；多個連接端子，配置於所述積體電路上並透過所述多個連接墊電連接至所述積體電路；以及多個擬導體，配置於所述積體電路上並與所述積體電路電性隔離；以及電路基板，與所述半導體裝置接合，包括：焊罩層，具有界定於其內的多個第一凹洞與多個第二凹洞；多個第一導電墊，所述多個第一導電墊中的每一者包括：第一部分，通過在所述焊罩層中界定的多個第一凹洞中的一者而局部地暴露出，其中其中所述第一部分連接至所述多個連接端子中的相應一者；以及第二部分，與所述第一部分連接，位於所述多個第一凹洞中的所述一者中並延伸至所述焊罩層的面朝所述半導體裝置的表面；以及多個第二導電墊，個別地與所述多個第一導電墊分隔開，所述多個第二導電墊通過所述多個第二凹洞而完全暴露出，所述多個第二導電墊中的每一者與所述多個第二凹洞中的對應一者的側壁間隔開， 其中所述多個連接端子電連接至所述多個第一導電墊，所述多個擬導體電連接至所述多個第二導電墊，且沿著所述電路基板與所述半導體裝置的堆疊方向，在所述多個連接端子與所述多個第一導電墊間的多個橫向介面與所述多個擬導體與所述多個第二導電墊間的多個橫向介面之間存在水平高度差異。
  2. 如申請專利範圍第1項所述的半導體封裝，其中所述多個連接端子中的每一者包括：第一導電部，配置在所述多個連接墊中的相應一個上；以及第二導電部，連接至所述第一導電部，其中所述第一導電部的高度與所述第二導電部的高度的總和等於所述多個擬導體中的每一者的高度。
  3. 如申請專利範圍第1項所述的半導體封裝，其中所述多個擬導體是電性浮動或接地的。
  4. 如申請專利範圍第1項所述的半導體封裝，其中所述積體電路更包括：半導體基底；以及內連線結構，配置且覆蓋於所述半導體基底上，其中所述內連線結構包括交替堆疊的多個圖案化導電層及多個層間介電層，所述多個圖案化導電層中的最外部圖案化導電層被所述多個層間介電層中的最外層的層間介電層覆蓋，且所述最外部圖案化導電層通過在所述最外層的層間介電層中界定的多個第三凹洞而局部地暴露出， 其中所述多個連接墊包括通過界定於所述最外層的層間介電層中的所述多個第三凹洞而局部地暴露出的所述最外部圖案化導電層。
  5. 一種半導體封裝，包括：電路基板，具有多個第一導電墊以及個別地與所述多個第一導電墊分隔開的多個第二導電墊，其中所述電路基板包括焊罩層，所述焊罩層具有界定於其內的多個第一凹洞與多個第二凹洞；以及半導體裝置，配置於所述電路基板上，且所述半導體裝置包括：積體電路，具有多個連接墊；介電層，配置於所述多個連接墊上並通過在所述介電層中界定的多個第三凹洞而局部地暴露出所述多個連接墊；多個連接端子，配置於通過所述多個第三凹洞而暴露出的所述多個連接墊上；以及至少一個擬導體，配置於所述介電層上並與所述積體電路電性隔離，其中所述半導體裝置經由所述多個連接端子及所述至少一個擬導體而接合至所述電路基板上，其中所述多個連接端子分別地連接至所述多個第一導電墊，所述至少一個擬導體連接至所述多個第二導電墊中的一者，且在所述多個連接端子與所述多個第一導電墊間的多個橫向介面和所述至少一個擬導體與所述多個第二 導電墊中的所述一者間的橫向介面之間存在水平高度差異，其中所述多個第一導電墊中的每一者的第一部分通過在所述焊罩層中界定的多個第一凹洞中的一者而局部地暴露出且連接至所述多個連接端子中的相應一者，且與所述多個第一導電墊中每一者的所述第一部分連接的第二部分位於所述多個第一凹洞中的所述一者中並延伸至所述焊罩層的面朝所述半導體裝置的表面，其中所述多個第二導電墊通過所述多個第二凹洞而完全暴露出，所述多個第二導電墊中的每一者與所述多個第二凹洞中的對應一者的側壁間隔開。
  6. 如申請專利範圍第5項所述的半導體封裝，其中所述多個第一導電墊中的每一者進一步包括與所述第二部分連接的第三部分，且所述第三部分遠離所述第二部分突出。
  7. 一種半導體封裝，包括：積體電路；多個連接端子，配置於所述積體電路上並與所述積體電路電連接；至少一個擬導體，配置於所述積體電路上並與所述積體電路電性隔離；以及重佈線路結構，具有多個第一導電墊以及個別地與所述多個第一導電墊分隔開的多個第二導電墊，其中所述重佈線路結構包括焊罩層，所述焊罩層具有界定於其內的多個第一凹洞與多個第二凹洞，其中所述積體電路經由分別地連接所述多個連接端子及 所述至少一個擬導體至所述多個第一導電墊及所述多個第二導電墊中的一者而接合至所述重佈線路結構上，其中在所述多個連接端子與所述重佈線路結構間的多個橫向介面和所述至少一個擬導體與所述重佈線路結構間的橫向介面之間存在水平高度差異，其中所述多個第一導電墊中的每一者的第一部分通過在所述焊罩層中界定的多個第一凹洞中的一者而局部地暴露出且連接至所述多個連接端子中的相應一者，且與所述多個第一導電墊中每一者的所述第一部分連接的第二部分位於所述多個第一凹洞中的所述一者中並延伸至所述焊罩層的面朝所述積體電路的表面，其中所述多個第二導電墊通過所述多個第二凹洞而完全暴露出，所述多個第二導電墊中的每一者與所述多個第二凹洞中的對應一者的側壁間隔開。
  8. 如申請專利範圍第7項所述的半導體封裝，更包括：介電層，配置於所述積體電路上並具有界定在所述介電層中的多個第三凹洞，其中所述多個連接端子中的每一者包括：第一導電部，配置於所述多個第三凹洞中；以及第二導電部，連接至所述第一導電部，其中所述第一導電部的高度與所述第二導電部的高度的總和等於所述至少一個擬導體的高度。
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